US 20080136827 A1
A PC-based computing system employing a silicon chip having a routing unit and a control unit for parallelizing multiple GPU-driven pipeline cores during a graphics application. The PC-based computing system includes system memory for storing software graphics applications, software drivers and graphics libraries, and an operating system (OS), stored in the system memory, and a central processing unit (CPU), for executing the OS, graphics applications, drivers and graphics libraries. The system also includes a CPU/memory interface module, a CPU bus, a silicon chip of monolithic construction interfaced with the CPU/memory interface module by way of the CPU bus. The routing unit (i) routes the stream of geometrical data and graphic commands from the graphics application to one or more of the GPU-driven pipeline cores, and (ii) routes pixel data output from one or more of GPU-driven pipeline cores during the composition of frames of pixel data corresponding to final images for display on the display surface. The control unit accepts commands from the software multi-pipe drivers, and controls components within the silicon chip, including the routing unit.
1. A PC-based computing system comprising:
system memory for storing software graphics applications, software drivers and graphics libraries;
an operating system (OS), stored in said system memory;
one or more graphics applications, stored in said system memory, for generating a stream of geometrical data and graphics commands supporting (i) the representation of one or more 3D objects in a scene having 3D geometrical characteristics and (ii) the viewing of images of said one or more 3D objects in said scene during an interactive process carried out between said PC-based computing system and a user of said PC-based computing system;
one or more graphic libraries, stored in said system memory, for storing data used to implement said stream of geometrical data and graphics commands;
a central processing unit (CPU), for executing said OS, said graphics applications, said drivers and said graphics libraries;
a CPU bus;
a CPU/memory interface module for interfacing with said CPU by way of said CPU bus;
a display surface for displaying said images by graphically displaying frames of pixel data;
a plurality of GPU-driven pipeline cores arranged in a parallel architecture and operating according to a parallelization mode of operation so that said GPU-driven pipeline cores process data in a parallel manner;
a silicon chip having a routing unit, and a control unit;
software multi-pipe drivers, stored in said system memory, and including a GPU driver module allowing said GPU-driven pipeline cores to interact with said OS and said graphic libraries;
wherein said CPU/memory interface module provides an interface between said software multi-pipe drivers and said silicon chip;
wherein said routing unit interfaces with said CPU/memory interface module and said GPU-driven pipeline cores, and (i) routes the stream of geometrical data and graphic commands from said graphics application to one or more of said GPU-driven pipeline cores, and (ii) routes pixel data output from one or more of said GPU-driven pipeline cores during the composition of each frames of pixel data corresponding to a final image, for display on said display surface;
wherein said control unit accepts commands from said software multi-pipe drivers, and controls components within said silicon chip, including said routing unit;
wherein said software multi-pipe drivers perform the following functions:
(i) controlling the operation of said silicon chip,
(ii) interacting with said OS and said graphic libraries, and
(iii) forwarding said stream of geometrical data and graphic commands, or a portion thereof, to each said GPU-driven pipeline core; and
wherein, for each image of said 3D object to be generated and displayed on said display surface, the following operations are performed:
(i) said silicon chip uses said routing unit to distribute said stream of geometrical data and graphic commands, or a portion thereof, to said GPU-driven pipeline cores,
(ii) one or more of said GPU-driven pipeline cores process said stream of geometrical data and graphic commands, or a portion thereof, during the generation of each said frame, while operating in said parallelization mode, so as to generate pixel data corresponding to at least a portion of said image, and
(iii) said silicon chip uses said routing unit to route said pixel data output from one or more of said GPU-driven pipeline cores and compose a frame of pixel data, representative of the image of said 3D object, for display on said display surface.
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This application is a Continuation of U.S. application Ser. No. 11/340,402 filed Jan. 25, 2006; which is a Continuation-in-Part of provisional Application No. 60/647,146 filed Jan. 25, 2005; International Application No. PCT/IL2004/000079 filed Jan. 28, 2004, published as WIPO Publication No. WO 2004/070652 A2 on Aug. 19, 2004; and International Application No. PCT/IL2004/001069 filed Nov. 19, 2004, published as WIPO Publication No. WO 2005/050557 A2 on Jun. 2, 2005, and entered in the U.S. National Stage on May 17, 2006 as U.S. application Ser. No. 10/579,682, and based on U.S. provisional Application Nos. 60/523,084 and 60/523,102, both filed Nov. 19, 2003; each Application being commonly owned by Lucid Information Technology Ltd, of Israel, and incorporated fully herein.
Over the past few decades, much of the research and development in the graphics architecture field has been concerned the ways to improve the performance of three-dimensional (3D) computer graphics rendering. Graphics architecture is driven by the same advances in semiconductor technology that have driven general-purpose computer architecture. Many of the same acceleration techniques have been used in this field, including pipelining and parallelism. The graphics rendering application, however, imposes special demands and makes available new opportunities. For example, since image display generally involves a large number of repetitive calculations, it can more easily exploit massive parallelism than can general-purpose computations.
In high-performance graphics systems, the number of computations highly exceeds the capabilities of a single processing unit, so parallel systems have become the rule of graphics architectures. A very high-level of parallelism is applied today in silicon-based graphics processing units (GPU), to perform graphics computations.
Typically these computations are performed by graphics pipeline, supported by video memory, which are part of a graphic system.
In the geometry subsystem, the graphics databases are regular, typically consisting of a large number of primitives that receive nearly identical processing; therefore the natural concurrency is to partition the data into separate streams and to process them independently. In the pixel subsystem, image parallelism has long been an attractive approach for high-speed rasterization architectures, since pixels can be generated in parallel in many ways. An example of a highly parallel Graphic Processing Unit chip (GPU) in prior art is depicted in
However, as shown in
A typical technology increasing the level of parallelism employs multiple GPU-cards, or multiple GPU chips on a card, where the rendering performance is additionally improved, beyond the converge limitation in a single core GPU. This technique is practiced today by several academic researches (e.g. Chromium parallel graphics system by Stanford University) and commercial products (e.g. SLI—a dual GPU system by Nvidia, Crossfire—a dual GPU by ATI).
Parallelization is capable of increasing performance by releasing bottlenecks in graphic systems.
There are different ways to parallelize the GPUs, such as: time-division (each GPU renders the next successive frame); image-division (each GPU renders a subset of the pixels of each frame); and object-division (each GPU renders a subset of the whole data, including geometry and textures), and derivatives and combinations of thereof. Although promising, this approach of parallelizing cluster of GPU chips suffers from some inherent problems, such as: restricted bandwidth of inter-GPU communication; mechanical complexity (e.g. size, power, and heat); redundancy of components; and high cost.
Thus, there is a great need in the art for an improved method of and apparatus for high-speed graphics processing and display, which avoids the shortcomings and drawbacks of such prior art apparatus and methodologies.
Accordingly, a primary object of the present invention is to provide a novel method of and apparatus for high-speed graphics processing and display, which avoid the shortcomings and drawbacks of prior art apparatus and methodologies.
Another object of the present invention is to provide a novel graphics processing and display system having multiple graphics cores with unlimited graphics parallelism, getting around the inherent converge bottleneck of a single GPU system.
Another object of the present invention is to provide a novel graphics processing and display system which ensures the best graphics performance, eliminating the shortages of a multi-chip system, the restricted bandwidth of inter-GPU communication, mechanical complexity (size, power, and heat), redundancy of components, and high cost.
Another object of the present invention is to provide a novel graphics processing and display system that has an amplified graphics processing and display power by parallelizing multiple graphic cores in a single silicon chip.
Another object of the present invention is to provide a novel graphics processing and display system that is realized on a silicon chip having a non-restricted number of multiple graphic cores.
Another object of the present invention is to provide a novel graphics processing and display system that is realized on a silicon chip which utilizes a cluster of multiple graphic cores.
Another object of the present invention is to provide a novel graphics processing and display system that is realized on a silicon chip having multiple graphic cores or pipes (i.e. a multiple-pipe system-on-chip, or MP-SOC) and providing architectural flexibility to achieve the advanced parallel graphics display performance.
Another object of the present invention is to provide a novel graphics processing and display system that is realized on a silicon chip having multiple graphic cores, and adaptively supporting different modes of parallelism within both its geometry and pixel processing subsystems.
Another object of the present invention is to provide a novel graphics processing and display system that is realized on a silicon chip having multiple GPU cores, and providing adaptivity for highly advanced graphics processing and display performance.
Another object of the present invention is to provide a novel graphics processing and display system and method, wherein the graphic pipeline bottlenecks of vertex (i.e. 3D polygon geometry) processing and fragment processing are transparently and intelligently resolved.
Another object of the present invention to provide a method and system for an intelligent decomposition of data and graphic commands, preserving the basic features of graphic libraries as state machines and tightly sticking to the graphic standard.
Another object of the present invention to provide a new PCI graphics card supporting a graphics processing and display system realized on a silicon chip having multiple graphic cores, and providing architectural flexibility to achieve the best parallel performance.
Another object of the present invention to provide a computing system having improved graphics processing and display capabilities, employing a graphics card having a silicon chip with multiple graphic cores, and providing architectural flexibility to achieve the best parallel performance.
Another object of the present invention to provide such a computing system having improved graphics processing and display performance required by applications including, video-gaming, virtual reality, scientific visualization, and other interactive application requiring or demanding photo-realistic graphics display capabilities.
These and other objects and advantages of the present invention will become apparent hereinafter.
For a more complete understanding of how to practice the Objects of the Present Invention, the following Detailed Description of the Illustrative Embodiments can be read in conjunction with the accompanying Drawings, briefly described below, wherein:
The techniques taught in Applicant's prior PCT application No. PCT/IL04/001069, published as WIPO Publication No. WO 2005/050557 A2, incorporated herein by reference, teaches the use of a graphics scalable Hub architecture, comprised of Hardware Hub and Software Hub Driver, which serves to glue together (i.e. functioning in parallel) off-the-shelf GPU chips for the purpose of providing a high performance and scalable visualization solution, object division decomposition algorithm, employing multiple parallel modes and combination thereof, and adaptive parallel mode management. Also, PCT Application No. PCT/IL2004/000079, published as WIPO Publication No. WO 2004/070652 A2, incorporated herein by reference, teaches the use of compositing image mechanism based on associative decision making, to provide fast and non-expensive re-compositing of frame buffers as part of Object Division parallelism.
The approaches taught in Applicant's PCT Applications identified above have numerous advantages and benefits, namely the ability to construct powerful parallel systems by use of off-the-shelf GPUs, transparently to existing applications. However, in many applications, it will be desirable to provide such benefits in conventional graphics systems, using an alternative approach, namely: by providing PCs with a graphics processing and display architecture employing powerful graphics processing and display system realized on monolithic silicon chips, for the purpose of delivering high performance, high frame-rate stability of graphic solutions at relatively low-cost, and transparency to existing graphics applications.
The benefits of this novel alternative approach include VLSI-based miniaturization of multi-GPU clusters, high bandwidth of inter-GPU communication, lower power and heat dissipation, no redundancy of components, and low cost. Details on practicing this alternative approach will now be described below.
In general, the present invention disclosed herein teaches an improved way of and a means for parallelizing graphics functions on a semiconductor level, as a multiple graphic pipeline architecture realized on a single chip, preferably of monolithic construction. For convenience of expression, such a device is termed herein as a “multi-pipe system on chip” or “MP-SOC”. This system “on a silicon chip” comprises a cluster of GPU-driven pipeline cores organized in flexible topology, allowing different parallelization schemes. Theoretically, the number of pipeline cores is unlimited, restricted only by silicon area considerations. The MP-SOC is driven by software driver modes, which resident to the host CPU. The variety of parallelization schemes enables performance optimization. These schemes are time, image and object division, and derivatives of thereof.
The illustrative embodiment of the present invention enjoys the advantages of a multi GPU chip, namely: bypassing the converge limitation of a single GPU, while at the same time it gets rid of the inherent problems of a multi-GPU system, such as restricted bandwidth of inter-GPU communication, mechanical complexity (size, power, and heat), redundancy of components, and high cost.
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A major feature of the present invention is its topological flexibility which enables revamping of performance bottlenecks. Such flexibility is gained by rearranging the cluster of graphics pipelines by means of routing center and different merging schemes at the compositing unit. Different parallelization schemes affect different performance bottlenecks. Therefore bottlenecks, identified by the profiling module, can be cured by utilizing the corresponding parallelization scheme.
The flowchart of
Let us assume that the Object Division (OD) path was taken. The Distributed Graphic Functions Control (S-DGFC) module configures the entire system for OD, characterized by distribution of geometric data and the compositing algorithm in use. This configuration is shown in
The left path in the flowchart is Image Division (ID) operation. The ID configuration, as set by the S-DGFC, is also shown in
The Time Division mode alternates frames among the GPU-driven pipe cores. It is set for alternation by the S-GDFC module, while each core is designated a frame data by S-DGFC and delivered by the C-RC unit. Each core (C-PC) generates a frame, in a line. Then the C-Ctrl moves the matured FB via compositing unit to the Display Interface, and out to the display. Actually, the compositing unit in this mode acts just as a transit. Finally there is a change-mode test by S-PA and S-PPM modules, same as in the other modes before.
Different parallelization schemes resolve different performance bottlenecks. Therefore bottlenecks must be identified and then eliminated (or reduced) by applying the right scheme at the right time.
As shown in
1. The profiling functions unit in MP-SOC
2. The driver
3. The pipeline cores
4. Chipset Architecture Performance (CHAP) Counters
Typically, the performance data is retrieved on a frame time basis, however, the periodicity can also be a configuration attribute of the profiler, or can be set based on a detected configuration event which the profiler is designed to detect before retrieving performance data.
The analysis, resulting in the selection of a preferred parallel method is based on the assumption that in a well defined case (described below), object-division method supersedes the other division modes in that it reduces more bottlenecks. In contrast to image-division, that reduces only the fragment/fill bound processing at each pipeline core, the object-division relaxes virtually all bottleneck across the pipeline: (i) the geometry (i.e. polygons, lines, dots, etc) transform processing is offloaded at each pipeline, handling only 1/N of polygons (N—number of participating pipeline cores); (ii) fill bound processing is reduced since less polygons are feeding the rasterizer, (iii) less geometry memory is needed; (iv) less texture memory is needed.
Although the time-division method releases bottlenecks by allowing to each pipeline core more time per frame generation, however this method suffers from severe problems such as CPU bottlenecks, the pipeline cores generated frame buffers that are not available to each other, and there are frequent cases of pipeline latency. Therefore this method is not suitable to all applications. Consequently, due to its superiority as bottleneck opener, object-division becomes the primary parallel mode.
The following object division algorithm distributes polygons among the multiple graphic pipeline cores. Typical application generates a stream of graphic calls that includes blocks of graphic data; each block consists of a list of geometric operations, such as single vertex operations or buffer based operations (vertex array). Typically, the decomposition algorithm splits the data between pipeline cores preserving the blocks as basic data units. Geometric operations are attached to the block(s) of data, instructing the way the data is handled. A block is directed to designated GPU. However, there are operations belonging to the group of Blocking Operations, such as Flush, Swap, Alpha blending, which affect the entire graphic system, setting the system to blocking mode. Blocking operations are exceptional in that they require a composed valid FB data, thus in the parallel setting of the present invention, they have an effect on all pipeline cores. Therefore, whenever one of the Blocking operations is issued, all the pipeline cores must be synchronized. Each frame has at least 2 blocking operations: Flush and Swap, which terminate the frame.
When the blocking operation is detected, all pipeline cores must be synchronized at step 1114 by at least the following sequence:
The Swap operation activates the double buffering mechanism, swapping the back and front color buffers. If Swap is detected at step 1115, it means that the composited frame must be terminated at all pipeline cores, except pipeline 0. All pipeline cores have the final composed contents of a FB designated to store said contents, but only the one connected to the screen (pipeline 0) displays the image at step 1116.
Another case is operations that are applied globally to the scene and need to be broadcasted to all the pipeline cores. If one of the other blocking operations is identified, such as Alpha blending for transparency, then all pipeline cores are flushed as before at step 1114, and merged into a common FB. This time the Swap operation is not detected (step 1115), therefore all pipeline cores have the same data, and as long as the blocking mode is on (step 1117), all of them keep processing the same data (step 1118). If the end of the block mode is detected at step 1117, pipeline cores return working on designated data (step 1113).
The relative advantage of object-division depends very much on depth complexity of the scene. Depth complexity is the number of fragment replacements as a result of depth tests (the number of polygons drawn on every pixel). In the ideal case of no fragment replacement (e.g. all polygons of the scene are located on the same depth level), the fill is reduced according to the reduced number of polygons (as for 2 pipeline cores). However, when depth complexity is getting high, the advantage of object-division drops down, and in some cases the image-division may even perform better, e.g. applications with small number of polygons and high volume of textures.
In addition, the present invention introduces a dynamic load-balancing technique that combines the object division method with the image division and time division methods in image and time domains, based on the load exhibits by previous processing stages. Combining all the three parallel methods into a unified framework dramatically increases the frame rate stability of the graphic system.
If at some point the system detects that the bottlenecks exhibited in previous frames occur at the raster stage of the pipeline, it means that fragment processing dominates the time it takes to render the frames and that the configuration is imbalanced. At that point the pipeline cores are reconfigured, so that each pipeline core will render a quarter of the screen within the respective frame. The original partition for time division, between pipeline cores 1,2,3,4 and between 5,6,7,8 still holds, but pipeline core 2 and pipeline core 5 are configured to render the first quarter of screen in even and odd frames respectively. Pipeline cores 1 and 6—render the second quarter, pipeline cores 4 and 7—the third quarter, and pipeline cores 3 and 8—the forth quarter. No object division is implied.
In addition, if at some point the system detects that the bottleneck exhibited in previous frames occurs at the geometry stage of the pipe, the pipeline cores are reconfigured, so that each pipeline core will process a quarter of the geometrical data within the respective frame. That is, pipeline cores 3 and 5 are configured to process the first quarter of the polygons in even and odd frames respectively. Pipeline cores 1 and 7—render the second quarter, pipeline cores 4 and 6—the third quarter and pipeline cores 2 and 8—the forth quarter. No image division is implied.
It should be noted, that taking 8 pipeline cores is sufficient in order to combine all three parallel modes, which are time, image and object division modes, per frame. Taking the number of pipeline cores larger than 8, also enables combining all 3 modes, but in a non-symmetric fashion. The flexibility also exists in frame count in a time division cycle. In the above example, the cluster of 8 pipeline cores was broken down into the two groups, each group handling a frame. However, it is possible to extend the number of frames in a time division mode to a sequence, which is longer than 2 frames, for example 3 or 4 frames.
Taking a smaller number of pipeline cores still allows the combination of the parallel modes, however the combination of two modes only. For example, taking only 4 pipeline cores enables to combine image and object division modes, without time division mode. It is clearly understood from
It should be noted, that similarly to the above embodiments, any combination between the parallel modes can be scheduled to evenly balance the graphic load.
It also should be noted, that according to the present invention, the parallelization process between all pipeline cores may be based on an object division mode or image division mode or time division mode or any combination thereof in order to optimize the processing performance of each frame.
The decision on parallel mode is done on a per-frame basis, based on the above profiling and analysis. It is then carried out by reconfiguration of the parallelization scheme, as described above and shown in
The MP-SOC architecture described in great detail hereinabove can be readily adapted for use in diverse kinds of graphics processing and display systems. While the illustrative embodiments of the present invention have been described in connection with PC-type computing systems, it is understood that the present invention can be use improve graphical performance in diverse kinds of systems including mobile computing devices, embedded systems, and as well as scientific and industrial computing systems supporting graphic visualization of photo-realistic quality.
It is understood that the graphics processing and display technology described in the illustrative embodiments of the present invention may be modified in a variety of ways which will become readily apparent to those skilled in the art of having the benefit of the novel teachings disclosed herein. All such modifications and variations of the illustrative embodiments thereof shall be deemed to be within the scope and spirit of the present invention as defined by the Claims to Invention appended hereto.