US 20080143408 A1
In accordance with some embodiments, a pulse width modulator having a comparator with an applied adjustable waveform to generate a bit stream with a controllably adjustable duty cycle is provided.
1. A circuit, comprising:
a pulse width modulator comprising:
a comparator having an associated reference level, and
an adjustable waveform generator coupled to said comparator to provide it with a periodic waveform, the comparator to generate a bit stream having a controllably adjustable duty cycle corresponding to adjustment of the position of the periodic waveform.
2. The circuit of
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8. A voltage regulator comprising at least one pulse width modulator as defined in
9. A method, comprising:
comparing a periodic waveform against a fixed reference to generate a bit stream having a controllably variable duty cycle; and
providing a control to adjust the periodic waveform relative to the fixed reference level in order to adjust the duty cycle.
10. The method of
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15. A computer system, comprising:
a voltage regulator coupled to the microprocessor to provide it with a regulated voltage supply, the voltage regulator comprising at least one a pulse width modulator comprising: a comparator having an associated reference level, and an adjustable waveform generator coupled to said comparator to provide it with a periodic waveform, the comparator to generate a bit stream having a controllably adjustable duty cycle corresponding to adjustment of the position of the periodic waveform; and
a power supply coupled to the voltage regulator to provide it with power to generate the regulated voltage supply.
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The present invention relates generally to signal generator circuits and in particular, to pulse width modulator circuits.
Switching type voltage regulators and other devices use pulse width modulators (PWMs) to generate pulse train (bit stream) signals with a controllably variable duty cycle. Duty cycle is the ratio of the duration during which the stream is a binary assertion (e.g., high level) compared to the duration during which the stream is a binary de-assertion (e.g., low level) over a period of the signal. For example, in a system where a high (‘1) is an assertion, a 60% duty cycle implies that the high state last 60% of the period, while the low state last only 40%.
With switching voltage regulators, a PWM is typically used to turn switches on and off in order to increase or decrease the amount of energy supplied to a regulated voltage in order to control the voltage. The switches are typically on when the bit stream is asserted and off when it is not asserted. Thus, more or less energy can be supplied to the load by increasing or decreasing, respectively, the bit stream duty cycle.
With reference to
Unfortunately, the comparator circuit and circuit used to create the variable reference can be relatively complex, especially if it is to perform with reasonable precision. With multi-phase switching regulators, which typically use a separate PWM for each phase, this becomes even more problematic. In addition, distributing the variable reference signal into the multiple comparators can result in inconsistent reference levels and in noise. Accordingly, an improved solution is desired.
Embodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.
Disclosed herein are PWM solutions with comparators not relying on a variable reference to adjust duty cycle. In accordance with some embodiments, a waveform (such as a triangle, sawtooth, or sinusoidal wave) is applied to a comparator with a fixed reference to generate a bit stream with a controllable duty cycle. In some embodiments, the offset level of the applied waveform can be varied to adjust the duty cycle. However, before describing such PWMs, a dual rail generator that may be used to create an adjustable waveform will be discussed.
Dual Rail Generator
The dual rail generator of
In the depicted embodiment, each adder circuit in the dual rail reference generator section 302 has a voltage gain of A=1 and is implemented with a difference adder, which subtracts a first value from a second value. As shown in
Each regulator (322H or 322L) is a unity gain linear regulator formed from an amplifier coupled to PMOS and NMOS transistors, all coupled together as shown. The High-side regulator 322H is formed from amplifier 323, PMOS transistor P1 and NMOS transistor N1. It receives at its input (negative input of amplifier 323) the High reference signal (VHref), while its output is coupled to the gates of transistors P1 and N1. In turn, the transistor outputs (at their drains) are coupled back to the positive input of amplifier 323. The Low side regulator 322L is configured in the same way except that it is formed from amplifier 325, PMOS transistor P2 and NMOS transistor N2. (Note the term “PMOS transistor” refers to a P-type metal oxide semiconductor field effect transistor. Likewise, “NMOS transistor” refers to an N-type metal oxide semiconductor field effect transistor. It should be appreciated that whenever the terms: “transistor”, “MOS transistor”, “NMOS transistor”, or “PMOS transistor” are used, unless otherwise expressly indicated or dictated by the nature of their use, they are being used in an exemplary manner. They encompass the different varieties of MOS devices including devices with different VTs and oxide thicknesses to mention just a few. Moreover, unless specifically referred to as MOS or the like, the term transistor can include other suitable transistor types, e.g., junction-field-effect transistors, bipolar-junction transistors, and various types of three dimensional transistors, known today or not yet developed.)
Because each amplifier is configured with negative feedback, the voltage at the input terminals are forced to equal one another. This results in the output voltages (VH, VL) tracking (or following) the input voltages (VHref, VLref) and at the same time, being able to drive actual loads. Note that transistors N1 and P2 are represented with dashed lines. This is so because in some embodiments, the High side rail VH may be used to primarily source current to its load, while the Low side rail VL may primarily be used to sink current from its load. In such a case, N1 and P2 could be smaller than P1 and N2 or even omitted.
The dual rail generator generally comprises a dual rail reference generator section 402 coupled to an output driver section 422. The reference generator portion 402 comprises Inverters U1, U2, U3 and resistors R1 to R8, while the output driver section 422 comprises inverters U4 to U11, transistors P1, P2, N1, N2, resistors RH and RL, and capacitors CH and CL, all coupled together as shown. In some embodiments, the inverters are formed from PMOS and NMOS transistors with their gates coupled together to provide an inverter input and their drains coupled together to provide an inverter output. In some embodiments, the inverters (except possibly U7 and U11) are designed to have the same trip points, and U1-U5, U8 and U9 are sized to have the same strengths. For example, the PMOS and NMOS transistors in U1-U6, and U8-U10 may be designed to have the same current carrying capability. The actual trip point value is not necessarily critical, so long as the values in the inverters are sufficiently close to one another, although it may be desirable to target the trip point at VCC/2 so that VH and VL may have a wider operating range. U6 and U10 may be designed to be weaker in strength. In contrast, U7 and U11 may be designed to be stronger, and their trip points need not necessarily be the same as the others.
The reference generator portion 402 will initially be discussed. Inverters U1 and U2, along with resistors R1-R4, make up a low-side section to generate a reference signal (VLref) for the low rail, while inverter U3 and resistors R7 and R8 make up the high-side section to generate the high rail reference (VHref). With the depicted embodiment, the high and low side sections generate inverted versions, relative to inverter trip points, of the high and low side rails. The output driver section thus comprises driver circuits that invert the reference signal to provide the high and low rails.
inverter U1 is configured to be an inverting amplifier having a gain of about R2/R1 acting on the Vamp component of Va, relative to Vref (the trip point of the inverter). That is, an inverter, with feedback, acts similarly to an amplifier with negative feedback, except that it has an inherent offset corresponding to its trip point. Therefore, with resistors R1 and R2 configured as shown, the inverter's output voltage is equal to: (−R2/R1)(Va−Vref)+Vref. When R1 and R2 are equal, this reduces to: 2Vref−Va, or Vref−Vamp. so, for example, if Vref=0.6V and Va=0.8V, then VU1 would be 0.4V. (Note that this analysis assumes that the inverter gain is high, which may not be completely accurate, especially when inputs are close to the trip point. Accordingly, in some embodiments, the gain terms may be “tweaked” to achieve desired results, e.g., for a particular operating range.)
Inverter amplifier circuits U2 and U3 are essentially the same. They are configured to function as summing inverter amplifiers (relative to the inverter trip points, i.e., the reference voltage). Summing inverter U2 sums the output from U1 (VU1, which is Vref−Vamp) with Voff (Voffset+Vref), while U3 sums Va with Voff. (Note that the high-side section doesn't have an inverter stage corresponding to U1 in the low-side path. This is so because in the high-side path, to generate VL, the Vamp component in Va is added rather than subtracted.)
The gain and relative weighting for the summed terms are determined by their associated resistors. With regard to U2, R4/R3 determines the gain for the VU1 term while R4/R5 determines the gain for the Voff term. The output of U2 (Vref) will be: VLref=−(R4/R3)(VU1−Vref)−(R4/R5)(Voff−Vref)+Vref. Similarly, with regard to U3, R8/R7 determines the gain of the applied Va term, while R8/R6 determines the gain of the offset term Voff. The output, VHref, is: VHref=−(R8/R7)(Va−Vref) (R8/R6)(Voff−Vref)+Vref. Thus, if R3, R4, and R5 are the same and if R6, R7, and R8 are the same, the output equations reduce to: VLref=−(VU1−Vref)−(Voff-Vref)+Vref and VHref=−(Va−Vref)−(Voff−Vref)+Vref. The outputs, VLref and VHref, result in inverted, relative to the inverter trip points, versions of the high and low rails. The amplifiers (or drivers) in the output driver section 422 correct this in providing the high and low rails.
As an example to illustrate how the dual rail reference generator 402 works, assume that R1=R2 (e.g., 10K Ohms), R3=R4=R5 (e.g., 10K Ohms) and R6=R7=R8 (e.g., 10K Ohms). Also assume, as with the above example, that Vref=0.6V, the offset is to be 0.1V (the applied Voff would thus be 0.7V), and Vamp is to be 0.2V (the applied Va would thus be 0.5V and VU1 would be 0.4V). with these values, the high and low rails should be 0.9V and 0.7V, respectively. Applying these values to the equations for U2 and U7, the Low reference voltage, VLref, would be 0.7 while the high reference voltage, VHref, would be 0.3V. This is correct because after being inverted by the output driver sections (relative to the 0.6V reference), they become 0.5V and 0.9V respectively, which are the correct values.
(Again, it should be appreciated that the actual resistor values, amplifier gains, and weights are not necessarily important, so long as the overall transfer functions for VH/(Va, Voff) and VL/(Va, Voff) provide for sufficiently consistent, predictable results for acceptable input and output operating ranges. This also applies to the circuits in the output driver section 422, discussed in the following section.)
The output driver section 422 comprises inverters U4 to U11, MOS transistors N1, N2, P1, P2, and load resistors and capacitors RH, RL, CH, and CL. The low side driver is formed from inverters U4 to U7, transistors P1, P2, resistor RL, and capacitor CL; while the high side driver comprises inverters U7 to U10, transistors P2, N2, resistor RH, and capacitor CH.
With the low side driver, inverters U4 and U5 are coupled together at their inverter outputs at node N1 in a mirrored configuration. With this configuration, they act like an inverting analog amplifier to provide at an input (VLref, VL) the analog inverse of the other input, relative to Vref (inverter trip points, which are to be the same). Therefore, the voltage at VL will be: VL−2Vref−VLref (Note that as used in this circuit, the inverter inputs (at VLref and VL) function both as inputs and outputs. It may be helpful to think of them as ends of a see-saw, with a fulcrum in the middle pushing up to the reference voltage level. As one side goes up, the other goes down and when perfectly balanced, the inputs and node N1 approach Vref. On the other hand, when VLref goes up or down, i.e., in response to changes in Va and/or Voff it forces the voltage (VL) at the other end of the “see-saw” to go down or up in the opposite direction accordingly.
Inverter U6 is a relatively weak inverter, designed to have its trip point at Vref. With its input shorted to its output, it generates at its output the reference signal, Vref, and is coupled to the inverter outputs of mirrored inverters U4, U5 (node N1) to provide them with a relatively weak load. It serves to reduce their gain, acting like ballast to stabilize their analog performance.
Inverter U7 is relatively large (e.g., twice the current carrying capability as inverters U1, U2, U3, U4, or U5) and has it trip point relatively close to those of the others, but this is not critical. It functions to drive push/pull output transistors P1, N1 to appropriately regulate VL. Thus, U4/U5, U6, and P1/N1 form the negative feedback loop to regulate VL. As VL goes up (e.g., due to changes in the output load), it causes N1 to go lower, which causes N2 to go up thereby turning down P1 and turning up N1 to bring VL back down. It works the same way, but in the opposite direction, when VL goes down. Resistor RL and capacitor CL are coupled in series between VL and VSS to provide stability at the output, VL.
The high side driver is configured and operates essentially the same as the low side driver, so it will not be described to the same extent. However, it's worth pointing out that in some embodiments, with the high side driver, because the high rail, VH, may serve primarily as a current source, the pull-up FET, P2, may be sized larger than the pull-down transistor N2 and in some cases, N2 may be omitted altogether. Conversely, with the low side driver, the pull-down transistor N1 may be sized larger than P1 when the low rail, VL, serves primarily as a current sink. In some embodiments, P1 may be omitted altogether.
PWM with Fixed Reference Comparator
The VR controller comprises a phase control section 504 coupled to fixed reference PWM (FRPWM) circuits (PWM1 to PWMN). It controls these PWMs to generate bit stream drive signals for their respective switches. For each PW M, it controls their duty cycle, in response to feedback from their associated sensor 507, to regulate the output voltage at a consistent level. It may also control their phase relationships, relative to each other and perform other tasks. Each PWM comprises a fixed reference comparator to generate its bit stream. Such PWMs will be discussed in more detail in the following sections.
With reference to
It should be noted that the depicted system could be implemented in different forms. That is, it could be implemented on a circuit board, or a chassis having multiple circuit boards. Similarly, it could constitute one or more complete computers or alternatively, it could constitute a component useful within a computing system.
The invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. For example, it should be appreciated that the present invention is applicable for use with all types of semiconductor integrated circuit (“IC”) chips. Examples of these IC chips include but are not limited to processors, controllers, chip set components, programmable logic arrays (PLA), memory chips, network chips, and the like.
Moreover, it should be appreciated that example sizes/models/values/ranges may have been given, although the present invention is not limited to the same. As manufacturing techniques (e.g., photolithography) mature over time, it is expected that devices of smaller size could be manufactured. In addition, well known power/ground connections to IC chips and other components may or may not be shown within the FIGS. for simplicity of illustration and discussion, and so as not to obscure the invention. Further, arrangements may be shown in block diagram form in order to avoid obscuring the invention, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present invention is to be implemented, i.e., such specifics should be well within purview of one skilled in the art. Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the invention, it should be apparent to one skilled in the art that the invention can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.