US 20080157207 A1
A method of fabricating a tri-gate semiconductor device comprising a semiconductor body having an upper surface and side surfaces and a metal gate that has an approximately equal thickness on the upper and side surfaces. Embodiments of a tri-gate device with conformal physical vapor deposition workfunction metal on its three-dimensional body are described herein. Other embodiments may be described and claimed.
1. A semiconductor apparatus comprising:
a semiconductor body having a top surface and laterally opposite sidewalls;
a metal gate with approximately equal thickness on the top surface and the laterally opposite sidewalls, wherein the metal gate contains columnar grains.
2. The apparatus of
3. The apparatus of
4. The apparatus of
5. A semiconductor apparatus comprising:
a semiconductor body having a top surface and laterally opposite sidewalls;
a dielectric layer on the top surface and the laterally opposite sidewalls of the semiconductor body;
a metal gate layer with approximately equal thickness on a top surface and laterally opposite sidewalls of the dielectric layer, wherein the metal gate layer contains columnar grains; and
a polysilicon layer on the metal gate layer.
6. The apparatus of
7. The apparatus of
This application is a divisional application of Ser. No. 11/418,295 filed May 3, 2006, entitled “TRI-GATE DEVICE WITH CONFORMAL PVD WORKFUNCTION METAL ON ITS THREE-DIMENSIONAL BODY AND FABRICATION METHOD THEREOF”.
The field of invention relates generally to the field of semiconductor integrated circuit manufacturing and more specifically, but not exclusively, relates to complementary metal oxide semiconductor (CMOS) devices having a conformal metal gate structure on a three-dimensional tri-gate fin body.
In a conventional metal oxide semiconductor field effect transistor (MOSFET), the source, channel, and drain structures are constructed adjacent to each other within the same plane. The gate dielectric is formed on the channel area and the gate electrode is deposited on the gate dielectric. The transistor is controlled by applying a voltage to the gate electrode thereby allowing a current to flow through the channel between source and drain. The area necessary to support these structures in a plane constrains the number of transistors that can be placed within the limited area of a semiconductor chip. Semiconductor manufacturers increase the packing density of transistors by scaling down the size of the transistor at each generation of technology.
With advances in technology, the physical dimensions of the gate dielectric thickness, the gate length, and the gate oxide thickness have been reduced significantly. Contemporary manufacturing methods currently allow semiconductors to be produced with a transistor gate length of 45 nanometers (nm) and a gate oxide thickness of about 1.2 nm. One conventional gate oxide, silicon dioxide, exhibits reliability issues when only a few atomic layers thick. Additionally, this very thin gate oxide allows leakage current to pass when the device is in an off state, thereby leading to high levels of power consumption and excess heat generation in the semiconductor chip.
Alternative gate dielectric materials have been introduced to help alleviate this problem. However, due to material incompatibility problems, the alternative gate dielectric materials have necessitated a change in gate electrode materials. The polysilicon that has been used as a gate electrode material for many generations is now being replaced with a metal gate. Fabrication of the device using a metal gate instead of a polysilicon gate allows the threshold voltage of a transistor to be better controlled.
An alternative to the standard methods of building planar MOSFETs has been proposed to help alleviate some of the physical barriers to scaling down existing designs. These proposals involve the construction of three dimensional MOSFETs either in the form of a dual-gate transistor (FinFET) or as a tri-gate transistor as a replacement for the conventional planar MOSFET.
Three-dimensional transistor designs such as the dual-gate FinFET and the tri-gate transistor allow tighter packing of the same number of transistors on a semiconductor chip by using vertical or angled surfaces for the gates. The designers use vertical space to accommodate the extra transistor gates, which is analogous to building multi-level buildings as opposed to building single story buildings over a larger plot of land. In a dual-gate FinFET, two gates are oriented along a very narrow strip of silicon known as a fin. The two gates have equivalent lengths because they are located along opposite sides of the fine. The physical size of the fin is typically on the order of 10 nm in width and 50 nm in height. A tri-gate device consists of three gates on a semiconductor body whereby the physical dimensions of the sides of the semiconductor body are equal, resulting in three equivalent transistor gate widths on the same semiconductor body.
Since the tri-gate device has one top gate and two side gates, the overall threshold voltage (Vt) of the tri-gate device is a function of the Vt contributed by the top gate and the Vt for each of the two side gates. The Vt of a transistor is a critical parameter in the operation of the transistor. When a voltage is applied to a gate, the electrons in the substrate become concentrated in the region of the substrate nearest the gate creating a depletion region, or a region where the concentration of electrons are equal to the electron holes. If the voltage applied to the gate is below the threshold voltage, the transistor will remain in an off state. If the voltage applied to the gate is above the threshold voltage, then the transistor is turned on and current is allowed to flow from the source to the drain.
The Vt is a function of the materials used for the conductor, such as a polysilicon layer and a metal layer, along with the respective thicknesses of these layers. One problem with the current method of fabricating a tri-gate device is that the Vt for the top gate may be different than the Vt contributed by each of the two side gates. As a result, when a tri-gate device with equal width gates on the top and two sides of the device is scaled, the Vt for the top gate scales differently than the Vt contributed by the two side gates. It would be an advance in the art to construct a tri-gate device whose physical dimensions can be scaled while maintaining an equivalent Vt on all three gates.
The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified:
Embodiments of methods and apparatus for a tri-gate device with a conformal workfunction metal of nearly equivalent thickness on all three gates are described herein. In the following description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
An example for how a conformal metal with a pre-determined work function having a nearly equivalent thickness on all three sides of a tri-gate transistor can be formed is described in
The workfunction metal can be formed using a directional sensitive PVD metal deposition process whereby ions of an inert gas are accelerated towards a workfunction metal target, which may comprise titanium nitride (TiN), tantalum nitride (TaN), or another transition nitride metal. Upon impact, the ions from the inert gas sputter-off a target material and the target material forms on the surface of the tri-gate device in an anisotropic manner. The deposition rate depends on the angle of incidence of incoming particles, resulting in a higher deposition rate on the top gate than the side gates of the tri-gate device. Deposition of the workfunction metal layer using the PVD process is characterized by a microstructure that comprises columnar grains.
In another embodiment, a workfunction metal layer may be formed using anisotropic layering techniques including molecular beam epitaxy (MBE), chemical vapor deposition (CVD), electroplating, or evaporation. In one embodiment, a target thickness of the workfunction metal layer is between 25 angstroms and 300 angstroms in thickness. The workfunction metal layer thickness selected by the device designer is a function of the targeted Vt for the tri-gate device.
After forming the workfunction metal layer, a sacrificial masking layer (element 102) is deposited as a blanket layer. The sacrificial masking layer is applied to mask and planarize vertical features on the wafer. In one embodiment, the sacrificial masking layer may be a thick layer (1100-1500 angstroms) of a sacrificial light absorbing material (SLAM). SLAM is a material that covers the surface of the wafer by filling vias and normalizing a topography, thereby providing a consistent hole-free and opaque surface. The sacrificial masking layer may comprise another organosiloxane film such as bottom anti-reflective coating (BARC) or an organic spin-on coating such as photoresist.
The sacrificial masking material is etched (element 104) to remove a top portion of the material to expose the workfunction metal on the top gate of the tri-gate device. The sacrificial masking material may be dry-etched using sulfur hexafluoride (SF6), octafluorocyclobutane (C4F8), or another fluorocarbon (CxFy) gas in a plasma enhanced chemical vapor deposition (PECVD) chamber. The dry-etch process may be terminated by sensing a workfunction metal surface on the top gate of the tri-gate device. However, the sacrificial masking material may also be eroded using a wet-etch process. In one embodiment, the wet-etch process may comprise HF or hydroxide containing solutions.
The workfunction metal on the top gate of the tri-gate device is eroded (element 106) so that the thickness of the workfunction metal on the top gate is nearly equal to the thickness of the workfunction metal on the two side gates of the tri-gate device. In one embodiment, the workfunction metal on the top gate of the tri-gate device is eroded using sulfur hexafluoride (SF6), octafluorocyclobutane (C4F8), or another fluorocarbon (CxFy) gas in a PECVD chamber. The two side gates are protected from erosion by the sacrificial masking material during this process and maintain their initial thickness. As a result, the thickness of the workfunction metal on the two side gates of the tri-gate device are left unchanged. Other erosion techniques may be employed to achieve equivalent results. Examples may include wet-etch, chemical mechanical polishing (CMP) or ion milling techniques.
The remaining sacrificial masking material may be stripped or removed (element 108) once a desired workfunction metal thickness has been achieved on the top gate of the tri-gate device. In one embodiment, the remaining SLAM material is removed using an aqueous buffered hydrogen fluoride (HF) stripping solution. The stripping solution should selectively remove the sacrificial masking material without eroding a material amount of the workfunction metal.
After removing the remaining sacrificial masking material, the workfunction metal is clean and free of polymer residue and a top surface of the workfunction metal is suitable for further processing. In one embodiment, a polysilicon layer may be deposited on the top surface of the workfunction metal. A polysilicon layer may be deposited to create a vertical or nearly vertical wall adjacent to a side gate of a tri-gate device. A polysilicon layer may also be deposited to protect the workfunction metal (element 110) from interacting with an atmosphere or during subsequent processing steps that would be harmful to a workfunction metal surface.
In one embodiment, a workfunction metal formed as a top gate of a tri-gate transistor is noticeably thicker than the workfunction metal formed as two side gates, as illustrated in
The workfunction metal 230, such as TiN is formed as a layer on the surface of the dielectric layer 220 on all three gates of the tri-gate device. The TiN layer may be formed by using physical vapor deposition (PVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), electroplating, or evaporation.
After forming the workfunction metal layer 230, a sacrificial masking layer 300 is deposited as a blanket layer as illustrated in
A top portion 400 of the sacrificial masking layer 300 is removed to reveal the workfunction metal 230 on the top gate of the tri-gate device, as shown in
After etching a top portion of the sacrificial masking layer 300, the workfunction metal 230 on the top gate of the tri-gate device is eroded, as illustrated in
The above description of illustrated embodiments of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.
These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the drawings. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.