Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20080172646 A1
Publication typeApplication
Application numberUS 12/002,617
Publication dateJul 17, 2008
Filing dateDec 17, 2007
Priority dateMar 8, 2002
Also published asEP1488367A1, EP1488367A4, US7310787, US20030172055, WO2003077184A1
Publication number002617, 12002617, US 2008/0172646 A1, US 2008/172646 A1, US 20080172646 A1, US 20080172646A1, US 2008172646 A1, US 2008172646A1, US-A1-20080172646, US-A1-2008172646, US2008/0172646A1, US2008/172646A1, US20080172646 A1, US20080172646A1, US2008172646 A1, US2008172646A1
InventorsShiv Prakash, Bryan Darrell Bowyer, Peter Pius Gutberlet
Original AssigneeShiv Prakash, Bryan Darrell Bowyer, Peter Pius Gutberlet
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Array transformation in a behavioral synthesis tool
US 20080172646 A1
Abstract
A behavioral synthesis tool for generating an integrated circuit design is described. The behavioral synthesis tool allows a designer to interactively allocate variables or arrays to memory resources without having to modify a source code description of the integrated circuit. The behavioral synthesis tool reads the source code description and generates a synthesis intermediate format stored in memory. The synthesis tool searches the in-memory synthesis intermediate format to find arrays for each process. The arrays are then listed in a graphical user interface (GUI). The GUI allows the designer to create memory resources, specifying the type of memory, the packing mode, etc. The designer is also provided the ability to vary the format among a plurality of formats used to pack arrays to memory during the memory packing process. Upon completion of modifying the memory allocation, the designer saves the changes and such changes are effectuated by automatically updating the synthesis intermediate format.
Images(19)
Previous page
Next page
Claims(21)
1.-51. (canceled)
52. A method of interactively allocating memory in a behavioral synthesis tool, comprising:
analyzing a source code description describing behavior of an integrated circuit, the source code description including one or more array variables;
representing the source code description in an intermediate format, the intermediate format including memory allocation information for the one or more array variables; and
allowing a user to change the memory allocation information for at least one of the one or more array variables while the source code description is represented in the intermediate format and before a register-transfer-level (RTL) description of the integrated circuit is generated using the memory allocation information.
53. The method of claim 52, wherein the method further comprises providing a graphical user interface through which the user can indicate desired changes to the memory allocation information.
54. The method of claim 52, further comprising modifying the memory allocation information in the intermediate format in response to changes input from the user.
55. The method of claim 52, further comprising modifying the source code description in response to changes input from the user.
56. The method of claim 52, wherein the memory allocation information for one of the one or more array variables includes an array length, and wherein the method further comprises changing the array length of the one of the one or more array variables in response to input from the user.
57. The method of claim 52, wherein the memory allocation information for one of the one or more array variables includes an array width, and wherein the method further comprises changing the array width of the one of the one or more array variables in response to input from the user.
58. The method of claim 52, wherein the memory allocation information for one of the one or more array variables includes a memory type, and wherein the method further comprises changing the memory type for the one of the one or more array variables in response to input from the user.
59. The method of claim 52, wherein the memory allocation information for one of the one or more array variables includes a memory packing format, and wherein the method further comprises changing the memory packing format for the one of the one or more array variables in response to input from the user.
60. The method of claim 52, further comprising displaying an area versus latency graph for at least one of the one or more array variables using current memory allocation information and before the RTL description of the integrated circuit is generated using the memory allocation information.
61. The method of claim 52, further comprising generating an RTL description of the integrated circuit using the memory allocation information.
62. A system, comprising:
means for representing a source code description describing behavior of an integrated circuit in an intermediate format, the source code description including one or more array variables, and the intermediate format including memory allocation information for the one or more array variables; and
means for allowing a user to change the memory allocation information for at least one of the one or more array variables while the source code description is represented in the intermediate format and before a register-transfer-level (RTL) description of the integrated circuit is generated using the memory allocation information.
63. The system of claim 62, further comprising means for modifying the memory allocation information in the intermediate format in response to changes input from the user.
64. The system of claim 62, further comprising means for modifying the source code description in response to changes input from the user.
65. A synthesis system, comprising:
a memory storing an intermediate format representation of a source code description, the source code description and the intermediate format representation describing behavior of an integrated circuit and including one or more array variables; and
a graphical user interface that allows a user to modify memory allocation information for at least one of the one or more array variables before a register-transfer-level (RTL) description of the integrated circuit is generated using the memory allocation information.
66. The synthesis system of claim 65, wherein the graphical user interface displays a list of processes associated with the source code description and array variables accessed with the processes.
67. The synthesis system of claim 65, wherein the graphical user interface allows a user to modify an array length of at least one of the one or more array variables.
68. The synthesis system of claim 65, wherein the graphical user interface allows a user to modify a memory type to allocated to at least one of the one or more array variables.
69. The synthesis system of claim 65, wherein the graphical user interface allows a user to modify a memory packing format of at least one of the one or more array variables.
70. The synthesis system of claim 65, further comprising a display configured to display an area versus latency graph for at least one of the one or more array variables using current memory allocation information and before the RTL description of the integrated circuit is generated using the memory allocation information.
71. The synthesis system of claim 65, further comprising an RTL generator configured to generate an RTL description of the integrated circuit using the memory allocation information.
Description
FIELD OF THE INVENTION

The present invention relates generally to behavioral synthesis tools for creating integrated circuits, and more particularly relates to behavioral synthesis tools that provide for improved packing of arrays to memory.

BACKGROUND

With the proliferation of data-intensive applications, such as sound, image and video processing, the memory subsystem has become an important focus of electronic system design. More than three-quarters of a data-intensive system can be made up of storage components, making the memory subsystem the most crucial part of the design of an integrated circuit. Most of these systems need to be high-speed due to the large amounts of data involved and must be designed carefully to avoid a solution that is larger than expected.

The design of an integrated circuit no longer begins with a circuit diagram. Instead, it begins with a software program that describes the behavior or functionality of a circuit. This software program is a source code description that defines an algorithm to be performed with limited implementation details. Designers direct behavioral synthesis tools to convert the source code description into a register transfer level (RTL) description. The RTL description is used to ultimately generate a netlist that includes a list of components in the circuit and the interconnections between the components. This netlist is used to create the physical integrated circuit.

Arrays provide a powerful and convenient method for modeling the behavior of memories in source code descriptions. That is, behavioral descriptions are used to manipulate groups of data in an abstract manner using arrays. These arrays are, under the control of the designer, packed to memory. Behavioral synthesis tools automatically construct the logic to control the memory, freeing the designer to explore architectures using different memories with different characteristics (e.g., synchronous versus asynchronous, single port versus dual port), and make intelligent decisions about an appropriate implementation for a design.

To pack arrays to a memory, the designer must specifically assign the variables representing the arrays to a memory in source code and specify the type of memory and other memory parameters. This is accomplished using a set of attributes or directives. For example, Synopsis® tools use a “pragma” statement.

After the designer designates the details of memory allocation in the source code description (using pragma statements or other directives), the designer runs the source code description through the synthesis tool. The synthesis tool generates a report that the designer can use to analyze the performance of the circuit. For example, the user can examine the speed and area of the circuit to determine whether the current memory allocation is acceptable. If the memory allocation is not acceptable, the designer must return to an editor, re-edit the source code description to change the details of memory allocation, and run the source code description through the synthesis tool again. Such a technique for modifying the memory allocation is time consuming and inefficient and gives the designer only a limited amount of options for designating how memory will be allocated.

It is desirable, therefore, to provide a method and synthesis tool that allows a designer to modify memory resources more quickly and simply as well as provide the designer with more advanced options for specifying how arrays will be packed to memory.

SUMMARY

Methods, systems, and behavioral synthesis tools are provided that allow a designer to change the format of how an array is packed to memory during the memory packing process when converting a source code description of a circuit to an RTL description. The designer can write a source code description at the algorithmic level describing the behavior of the circuit to be designed. The designer then uses a behavioral synthesis tool to generate a number of different architectural designs using synthesis techniques. Each design can implement differing memory allocation by allowing the designer to change a number of different constraints such as whether to use RAMs vs. registers, which type of RAM to use, how many memories to use, whether to use on or off-chip memory, etc. The designer is also provided the ability to transform the layout format of the arrays in the source code description such that the designer can quickly and easily control the packing of the arrays into the chosen memories. These constraints can be changed either using a graphical user interface, changing constraints within the behavioral synthesis tool, or by manually manipulating the source code description. The behavioral synthesis tool then creates a report for each design to analyze the performance of the circuit. For example, the designer can examine and compare the speed and area of the circuits created from each of the designs to determine whether the memory performance and size are acceptable.

A source code file having a description of the hardware is read into a database within the behavioral synthesis tool. The behavioral synthesis tool analyzes the source code description and generates a data structure associated with the source code description. The designer can then modify a number of constraints dictating the details of memory allocation such as type of memory, number of memories, memory size, etc. Thus, rather than having to re-edit the source code description, the designer can change these memory constraints interactively and dynamically during the memory packing process to control how arrays are packed into memory. Once the designer is satisfied with the design, an RTL description is produced from the data structure.

A number of additional options for packing arrays into memory are provided by the behavioral synthesis tool to the designer so that the designer may select one of a plurality of array layout formats during the memory packing process. Providing the designer the ability to transform the layout of arrays dynamically allows the designer a fast, efficient method of customizing the memory allocation of the circuit to be synthesized.

Further features and advantages of the invention will become apparent with reference to the following detailed description and accompanying drawings.

BRIEF DESCRIPTION OF T HE DRAWINGS

FIG. 1 is a block diagram of a system for allowing interactive memory allocation.

FIG. 2 is a detailed diagram illustrating a design flow for creating an integrated circuit using the system of FIG. 1.

FIG. 3 is an illustration of directly packing an array to a memory.

FIG. 4( a) is an illustration of packing multiple words of an array into a single word of a memory.

FIG. 4( b) is another illustration of packing multiple words of an array into a single word of a memory.

FIG. 5( a) is an illustration of packing an array into a memory using a Little Endian format.

FIG. 5( b) is an illustration of packing an array into a memory using a Big Endian format.

FIG. 6( a) is an illustration of packing an array into memory in an interlacing format.

FIG. 6( b) is another illustration of packing an array into memory in an interlacing format.

FIG. 7( a) is an illustration of packing a single word of an array into multiple words of a memory.

FIG. 7( b) is another illustration of packing a single word of an array into multiple words of memory.

FIG. 8 is an illustration of packing an array into a customized location in a memory.

FIG. 9( a) is an illustration of packing a single array into multiple memories.

FIG. 9( b) is another illustration of packing a single array into multiple memories.

FIG. 10 is an illustration of packing multiple arrays into a single memory.

FIG. 11 is an illustration of packing multiple arrays into a single memory with the arrays overlapping in memory usage.

FIGS. 12( a-c) are illustrations of using resolution modes to define default behavior and correct designer error.

FIG. 13 shows an example of a user interface allowing the designer to modify memory resources in a behavioral synthesis tool.

FIG. 14 is a block diagram of an embodiment of a network environment for implementing a behavioral synthesis tool.

FIG. 15 is a block diagram of an embodiment of a system to carry out methods, systems and tools in accordance with the present invention.

FIG. 16 is an example of applying memory allocation to a SIF.

DETAILED DESCRIPTION

FIG. 1 shows a system 10 for generating an integrated circuit. A designer typically creates a behavioral description of an integrated circuit by generating source code 12 using a separate editor (not shown). The source code description may be written in any programming language capable of describing a circuit at the behavioral level, such as C, C++, VHDL, Verilog, Pascal, etc. Once the source code description 12 is complete, a behavioral synthesis tool 14 reads in the source code description 12 and allows a designer to evaluate and modify the circuit architecture early in the design process. In particular, the source code description 12 is read into an intermediate database 16 that holds the behavioral description as a data structure. This data structure, called a synthesis intermediate format (SIF), is modifiable by the user through a graphical user interface (GUI) 18. The GUI 18 allows the designer to interactively and dynamically modify the memory allocation in the data structure. However, the designer may also modify the memory allocation by manually editing the original source code description, or modifying the SIF without the assistance of a GUI. For instance, the designer may issue commands to modify the memory allocation within the SIF. The designer may then quickly evaluate the area and latency associated with different memory architectures. Once the designer is satisfied with the architecture, the RTL code is generated as shown at 20. Further processing is then performed on the RTL code to ultimately generate the integrated circuit.

FIG. 2 shows a more detailed flow chart for generating an integrated circuit according to one embodiment of the invention. In process block 30, the behavioral synthesis tool reads in the source code describing the behavior of the integrated circuit as already described. The source code description can include a default set of constraints to establish the original memory allocation. Alternatively, the default constraints can be provided by a selected packing mode, or by the designer once the source code description is read into the behavioral synthesis tool. In process block 32, the behavioral synthesis tool 14 (see FIG. 1) reads the source code description into the intermediate database 16 and generates a data structure that is changeable by the designer. When generating the data structure, the synthesis tool performs an analysis of the source code description. For example, the synthesis tool searches for operators, signals, and variables in the source code description and generates the data structure based on these statements. Additionally, the synthesis tool searches for directives and uses the directives as defaults for the memory allocation in the data structure.

At this point in the flow, the memory allocation information is stored in the intermediate database independently, meaning the information is not yet fully integrated into the SIF. This allows the designer to interactively change the memory allocation and control when such changes are applied to the SIF. The memory allocation information is stored as a set of resources for the design, wherein each resource represents a memory resource that may potentially be present in the final integrated circuit design. Additionally, arrays in the source code description are also stored in the data structure. The data structure may be organized in many different ways. One possible organization is to have various fields associated with the resources and arrays stored in the data structure. For instance, in one embodiment the following fields could be associated with a resource stored in the data structure:

A unique identification for the resource

A type of memory to be used for the resource

A list of variables packed to the resource

A packing mode for the resource

A flag indicating whether the resource is external to the design

A format for packing variables to the resource

Likewise, in one embodiment the following fields could be associated with arrays stored in the data structure:

A unique identification for the resource

An array length

An array width

A start address in a resource

A start bit in the resource

A format for packing the array to the resource

In process block 34, the designer can interactively change the memory allocation for variables that are in the source code description. That is, the source code description includes variables representing arrays that are associated with memory storage (although in some cases arrays are not packed to memory). The memory allocation for variables representing the arrays is modified by allowing the designer to manipulate a number of constraints relating to memory allocation. For instance, a first constraint may allow the designer to choose from the many different memories available in circuit design. Additional constraints may vary the size and type of memory selected (e.g., dual port memory, single port memory, etc.). Thus, in process block 34, the designer can choose which memories to use, the variables associated with those memories, the packing mode, etc.

In order to give the designer more flexibility in design, the designer is also provided the ability in process block 34 to transform the layout of the arrays into a variety of formats. The format used to pack an array to memory can have a significant impact on the overall memory performance of the circuit. Often the format used will dictate the number of reads and/or writes necessary to access a given number of words of an array or memory. Various formats can be chosen that emphasize keeping the size of the circuit within given specifications, while other formats can be chosen that emphasize the speed of the circuit (reducing the number of clock cycles/reads/writes). Specific array layout formats will be discussed at length with respect to FIGS. 3-11.

The designer can modify any of the memory allocation constraints discussed above (i.e. size, number, and type of memories, packing mode, formats) in a number of ways. The designer can use the GUI 18 shown in FIG. 1 to change constraints controlling memory allocation. Alternatively, the designer could manually change the constraints in the SIF or manually edit the source code description to include the constraint.

After memory is properly allocated, the designer can perform an initial check to analyze the area and timing of the circuit (process block 36). This may be done, for example, by displaying an area versus latency graph that gives the designer some immediate feedback on whether the memory allocation is satisfactory. If the designer is unhappy with the area or timing, the designer can return to process block 34 to further modify the memory allocation, as shown by arrow 38. On the other hand, if the designer is satisfied with the memory allocation, the RTL code can be generated and simulated (process blocks 40 and 42). Finally, an RTL synthesis tool can perform RTL synthesis (process block 44) and the gate level design can be verified and analyzed (process block 46).

For each array or memory, there is a fixed data block, which is read from or written into it at the same time. This fixed data block is called a word. An array or memory can be characterized by the size and number of words. The first parameter of a memory or array is the word size, which is the number of bits read or written in a single access. The second parameter is the number of words a memory can store. Each word has a unique address under which it can be read or written, which is usually a number from 0 to the wordcount-1. Arrays can usually be indexed by an expression which is computed during runtime. Memories as hardware units can have additional parameters such as delays and number of ports.

Further details are now given on how the memory allocation is applied to the SIF. After the designer is satisfied with the memory allocation, the designer directs the GUI to apply the memory allocation information to the SIF. Thus, at this point any changes the designer has made to the memory allocation are reflected in the database by modifying the independent set of resources and their field information. Applying this information to SIF involves several steps:

1. Create a memory data object representing each memory resource. This involves determining the size of the memory based on the variables packed to the memory and the size of the variables, along with the packing mode. Also, since the original variable index may get packed to a different memory address (based on the packing mode and the order of variables on the memory), offsets are computed for each array/index.

2. Transform all read/write accesses to any of the variables packed to the memory resource into corresponding read/write(s) to the created memory data object in step 1. Transforming includes modifying the SIF appropriately to reflect the packing of the original array index to the actual memory address location. This packing is dependent on the ordering of the variables and the packing mode used. An appropriate offset is inserted for each array index access. This offset insertion is also known as address calculation.

Referring to FIG. 16, an example is given of how memory allocation is applied to the SIF. FIG. 16 shows three segments of code. The first code segment 160 is sample of basic code for declaring an array A and then assigning various words of the array to variables. In segment 160, array A is declared with an array length of 100 and word width of 32 bits. Subsequently, word 5 of array A is assigned to variable b and word 9 of array A is assigned to variable c.

Assume for purposes of this example that the designer has read code segment 160 into a behavioral synthesis tool and now wishes to transform the format of this array such that it is only 50 words in width, and 64 bits wide. At this point using prior methods, the designer would have to re-edit source code segment 160 to reflect the change, both when declaring the array and whenever the array is accessed, as shown in code segment 162. Code segment 162 shows the declaration of array A changed to reflect the new size, but also the changes that must be made to the subsequent accesses to the array. In order to ensure the array accesses will still assign the correct word of array A after the size change, a new address must be calculated for the desired word. Depending on the changes made, this calculation could be quite difficult. Thus, manually producing this new code requires substantial editing time on the part of the designer and is error prone even for the simplest code such as that shown in FIG. 16. Code written to describe the behavior of integrated circuits is often much more complex, and therefore the time and possibility of error rise accordingly.

However, the behavior synthesis tool of the current embodiment allows the designer to simply change a constraint to transform the layout of array A from 100 by 32 to 50 by 64. Since the source code segment 160 has already been read into the SIF, a provided GUI will display the array A along with its current size, 100 by 32. The designer then changes a size constraint for the array indicating the array should be transformed to a 50 by 64 format. Once confirmed, the constraint within the SIF for the size of array A is changed to reflect the designer's desired change, and the behavioral synthesis tool creates RTL code reflecting any changes in the constraints. In other words, even though code segment 160 was read into the SIF, due to the designer's configuration of the constraints through the GUI, the RTL code is created as if the code segment 162 had been originally read in. This can be accomplished by the behavioral synthesis tool by actually creating and editing the code segment 160 to reflect the functionality of code segment 162, editing the SIF of code 160 to reflect the functionality of code segment 162, or leave code segment 160 unchanged yet still create RTL code to reflect the functionality of code segment 162.

Alternatively, in another embodiment, the designer could have manually added a size constraint to the source code segment 160, such as that shown in code segment 164, and then read in code segment 164 to the SIF. In yet another embodiment, the size constraint within the SIF could be changed manually by the designer without the assistance of a GUI.

Allowing a designer control over how arrays are packed to memory during the memory packing process in synthesizing an integrated circuit is desirable because the chosen architecture will have a significant impact on the performance of the memory system. For example, depending upon how the array words are accessed, it may be more effective to have the RAM word size different from the array word size. If two consecutive words from the array are accessed together, it may be efficient to pack two array words into a single RAM word. Or, conversely, if half of the array word is accessed often, it may be effective to split the array word into two RAM words.

Consider two arrays A (word size: 16) and B (word size: 32) are to be packed together. The RAM word size could be chosen to be, for instance, 16 or 32. If a designer chooses 32, the array A words could be zero-padded to make all A and B words the same size. The solution just suggested is obviously quite wasteful in terms of memory usage. Another solution would be to pack two array A words into a single RAM word. A third solution would be to choose 16 as the RAM word size, and split each array B word into two RAM words. A choice between the second and third formats would be dictated by word access patterns for the two arrays. Often there are numerous formats available for the same design description, each having advantages and disadvantages compared to other formats.

FIG. 3 is an illustration of directly packing an array to a memory. In this example, array 50 and memory 52 are the same length (10 words) and width (4 bits). However, array 50 could also be packed to a sub-section of a larger memory. In order to pack array 50 to memory 52, word 0 of array 50 is packed directly to word 0 of memory 52, as are subsequent words 1 through 9. Each array access results in one memory access. There is no address conversion and array addresses can be used directly as memory addresses. Therefore, direct packing is fairly simple and is processed by the behavioral synthesis tool quickly.

In many cases, access to memory elements is the bottleneck of a design, because it limits the maximum parallelism of the performed functionality. One option is to increase the width of a memory word, so each memory access reads or writes multiple array words. Packing an array to a memory with larger word size is a typical transformation to increase the throughput of the memory port as an alternative to memories with multiple ports. FIG. 4( a) is an illustration of packing multiple words of an array into a single word of a memory. Array 60 shown in FIG. 4( a) has a length of 10 words and width of 4 bits. Array 60 is packed to a memory 62 that is 8 words in width, or twice the word width of array 60. Therefore, words 0 and 1 of array 60 can be packed into word 0 of memory 62. Likewise, words 2 and 3 of array 60 are packed to word 1 of memory 62, and so on.

FIG. 4( b) is another illustration of packing multiple words of an array into a single word of a memory. Array 64 in FIG. 4( b) has a word width of 4 bits. However, memory 66 has word width 12, or three times the word width of array 64. Therefore, words 0, 1 and 2 of array 64 can be packed into word 0 of memory 66. Likewise, words 3, 4 and 5 of array 64 are packed to word 1 of memory 66, and so on.

Packing multiple array words to a single word of memory requires each array access to be transformed into a memory access, where certain address calculations and sub-selections of memory words have to be performed. Writing an element of the array requires reading the memory word first or the array element sharing the same memory word is not overwritten. In other words, each array read transforms into a memory read and an array write transforms into multiple memory accesses. A designer would therefore find this format useful if multiple array accesses can be packed to a single memory access. This may be the case when the source code description contains numerous loops that access the array elements in sequential order, or if the source code description always, or often, accesses the array words in pairs.

FIGS. 5( a) and 5(b) are illustrations of packing an array into a memory using Endian formats. Array 70 in FIGS. 5( a) and 5(b) has an array length of 10 and word width of 4 bits. Array 70 is packed to a memory 72 with a word width of 8 bits, with two array words being packed to a single memory word, as discussed previously with respect to FIG. 4( a). However, the format, or the word width or length of the array or memory, are not important for purposes of using Endian formats. Endian formats, like all of the formats described herein, can be used in combination with other formats to transform array layouts.

FIG. 5( a) is an illustration of packing an array into a memory using a “Little Endian” format. This format packs array 70 to memory 72 beginning at the least significant bit of each word of memory 72. Therefore, memory 72 in FIG. 5( a) shows words 0 and 1 of array 70 packed to word 0 of memory 72 starting at the least significant bit, words 2 and 3 of array 70 packed to word 1 of memory 72 starting at the least significant bit, and so on. Little Endian format is used by most Intel processors for personal computers using a Microsoft Windows platform.

FIG. 5( b) is an illustration of packing array 70 into memory 74 using a “Big Endian” format. This format packs array 70 to memory 74 beginning at the most significant bit of each word of memory 74. Therefore, memory 74 in FIG. 5( b) shows words 0 and 1 of array 70 packed to word 0 of memory 74 starting at the most significant bit, words 2 and 3 of array 70 packed to word 1 of memory 74 starting at the most significant bit, and so on. Big Endian format is used by most Motorola processors for personal computer using a Macintosh platform.

Interlacing is a format which skips a specified number of words when reading from an array in order to pack the words to memory in a given order. A typical application would be if the odd addressed and even addressed words of the array are used in separate parts of the algorithm. FIG. 6( a) is an illustration of packing an array into memory in an interlacing format. Array 80 can be packed in an interlacing format skipping three words for every word packed such that the even words of array 80 are packed to the first five words of memory 82 and the odd words of array 80 packed to the second five words of memory 82.

FIG. 6( b) is another illustration of packing an array into memory in an interlacing format. In this example, only two words are skipped between each word of array 84 packed to memory 86, and memory 86 is twice the word width of array 84. Therefore, the first two words of array 84 to be packed to memory 86, words 0 and 3, are packed to the first word of the memory 86. Likewise, words 6 and 9 of array 84 are then packed to the next word of memory 86, and so on.

FIG. 7( a) is an illustration of packing a single word of an array into multiple words of a memory. FIG. 7( a) shows array 90 with a width of 8 bits being packed to memory 92 with a length of 4 bits. Therefore, the array words are split so that the first half of array word 0 is packed to the first word of memory 92, and the second half of array word 0 is packed to word 1 of memory 92. The rest of the array words are split in similar fashion, such that array word 1 is split and the first half is stored in memory word 2 and the second half in memory word 3, and so on. The array words can be split and packed to the memory words in order from high order bit to low order bit, or vice versa. For instance, memory words 0 and 1 each contain half of array word 0 in memory 92. The halves of array word 0 can be packed to memory 92 in any order. The first 4 bits (AB0-AB3) of array word 0 can be packed to memory word 0, or the last four bits (AB4-AB7) of array word 0 can be packed to memory word 0.

In this case each array access results in multiple memory accesses. This decreases the performance of the design but might be a design constraint, e.g. when only certain memory word sizes are available.

FIG. 7( b) is another illustration of packing a single word of an array into multiple words of memory. In FIG. 7( b), array 94 with a length of 10 words and width of 8 bits is packed onto memory 96 with a width of 6 bits. Selecting a memory word size which in not an exact multiple or devisor of the array word size results in one of the more complicated addressing conversions and slicing operations. The first array word, word 0 (8 bits), is packed to memory word 0 (6 bits), and the first 2 bits of memory word 1. This leaves 4 bits of unused space in memory word 1. Therefore, the first 4 bits of the second array word, word 1, are packed to the remaining 4 bits of free space in memory word 1, and the remaining 4 bits of array word 1 are packed to memory word 2. This continues until all array words have been packed to memory 96. In this case 14 memory words are required to hold all 80 bits of array 94. This leaves 4 unused bits 98 (80 array bits packed to 6*14=84 memory bits), which may be allocated anywhere in memory 96. In FIG. 7( b), these bits 98 are allocated at the end of the memory 96.

The packing shown in FIG. 7( b), like FIG. 7( a), requires extensive calculations to address a certain array element in the memory. However, such a packing could be useful where available memories are very constrained. Because array elements are distributed over two memory elements, multiple memory accesses might be necessary for each array access.

FIG. 8 is an illustration of packing an array into a customized location in a memory. Array 100 has a width of 8 bits and length of 4 words. Memory 102 is unspecified in length, but is larger than array 100 and has an array length of 12. The array 100 can be packed to any location in memory 102 large enough to be occupied by array 100. In FIG. 8, array 100 is packed such that the first word of array 100 is packed to memory word 6, and is located such that the first bit of array word 0 is packed to bit 4 of memory word 6. Each subsequent word of array 100 is packed to the subsequent word of memory 102, such that the first bit of the array word is located at bit 4 of the memory word.

FIG. 9( a) is an illustration of packing a single array into multiple memories. Array 110 is 10 words in length and 4 bits in width. There are two memories shown, 112 and 114, each of which are 4 bits in width and 5 words in length. Array 110 can be packed to the memories in a variety of ways. For instance, array 110 can be packed to the memories 112 and 114 by alternately packing each array word to the first memory 112 and then the second 114. Such is the case in FIG. 9( a). Word 0 of array 110 is packed to word 0 of memory 112, and word 1 of array 110 is packed to word 0 of memory 114. Word 2 of array 110 is then packed to word 1 of memory 112, and word 3 of array 110 is packed to word 1 of memory 114. This format continues until the remainder of the words in array 110 are packed to memory.

Alternatively, array 110 could also be packed such that the first 5 words of array 110 are packed sequentially into memory 112 and the second 5 words of array 110 are packed into memory 114, as shown in FIG. 9( b). Splitting an array into two separate memories increases the size of the overall circuit, but is effective in increasing the speed of the design because the two memories can be accessed independently. Thus, the designer has effectively enabled two words of array 110 to be accessed concurrently.

FIG. 10 is an illustration of packing multiple arrays into a single memory. Two arrays 120 and 122 are shown with a length of 4 words and width of 8 bits. The memory 124 is of an indeterminate width, but larger than arrays 120 and 122. The length of memory 124 is 12 words. Word 0 of array 120 is packed to word 2 of memory 120, with bit 0 of the array word being located at bit 4 of word 2 of memory 124. Each subsequent word of array 120 is packed to the subsequent word of memory 120 with the least significant bit of the array word located at bit 4 of the memory word.

Array 122 is packed so that it occupies space in memory 124 immediately adjacent array 120. Thus, word 0 of array 122 is packed to word 2 of memory 124, as was word 0 of array 120. However, word 0 of array 122 is displaced such that the least significant bit is located at bit 12 of the memory word. The subsequent words of array 122 are then packed to the subsequent words of memory 124, with the least significant bit of each array word located at bit 12 of the memory word.

A designer is thus given the alternative selection of increasing the speed of the circuit by packing one array onto multiple memories as shown in FIG. 9, or reducing the number of memories and therefore, the size of the circuit, by packing multiple arrays onto the same memory as shown in FIG. 10.

FIG. 11 is an illustration of packing multiple arrays into a single memory with the arrays overlapping in memory usage. The arrays 130 and 132 and memory 134 are the same dimensions as those described with respect to FIG. 10. However, in this example, arrays 130 and 132 have been packed such that the latter portions of word 0 and 1 of array 130 overlap in location with the beginning portions of words 2 and 3 of array 132. If arrays 130 and 132 have a common lifetime, then their sections must be disjoint and the packing shown will cause memory allocation errors. However, if the arrays have dissimilar lifetimes, this configuration may be an effective way of conserving memory resources.

The formats described with respect to FIGS. 3-11 allow a designer flexibility in adjusting the constraints that dictate an array layout format for packing the array into another array or into memory. For area-sensitive designs, it is tempting to merge all data into one memory; however this will constrain the memory accesses far more than if each array is packed to a separate memory. Greater speed through concurrency can be achieved by using multiple memories when available, with the drawback of a greater circuit size.

It is also noteworthy that the described formats can be used either in conjunction with resolution modes. FIG. 12 is an illustration of using resolution modes to set the default behavior of a design or to correct a designer error. Assume for the purposes of example that the four arrays shown in FIG. 12( a) were declared in source code read into a SIF, but only a first resolution mode was specified. Therefore, the positions of the arrays in FIG. 12( a) were determined by a set of constraints for each array according to the first resolution mode. FIG. 12( b) then shows the positions of the four arrays after the designer subsequently changed constraints corresponding to array 144 causing it to overlap with array 142. The designer can now be given the option of leaving the arrays positioned as shown in FIG. 12( b) (overlapping), changing constraints to move array 142 or 144 to an alternate position in memory to correct the problem, or have the array packed elsewhere automatically based upon the current resolution mode. Alternatively, the designer could have the array packed elsewhere in memory 140 based on a newly selected resolution mode. For instance, the designer could choose to correct the problem by selecting a second resolution mode as a basis for determining a new position for array 144, as shown in FIG. 12( c). The resolution mode can intelligently handle the task of repositioning the array 144 in a variety of ways, such as moving the array in any direction, resizing the array, packing the array to another memory resource, etc.

FIG. 13 shows an example of a user interface 150 for allowing the designer to modify memory resources interactively and dynamically. The user interface includes a display pane 152 that lists processes and array variables accessed within those processes. These processes and array variables represent the current memory allocation stored in the database 16 and are represented as graphical objects. When the synthesis tool 14 generates the data structure stored in database 16, the source code directives regarding variables and memory allocation are identified and are used as default settings for memory allocation. Using the GUI, a designer may choose to create the source code with no directives indicating memory allocation. In such a case, the designer interactively specifies the memory allocation via the GUI. Alternatively, the designer can include directives in the source code that are used as default settings.

For example, the array 154 selected in GUI 150 is a size 21 by 64, meaning it has words 64 bits in width, and length of 21 words. The display pane 152 provides a symbolic name of a resource associated with the variables. In this case, “dct_temp_rsc” is a memory resource used for the array 154, named “dct_temp”. The GUI 150 shows a settings tab 156 used by the designer to change the memory allocation of the circuit using the provided constraints. The setting tab 156 in this example shows only one of the many constraints that can be provided for customizing the memory allocation of a circuit design. Here, the array word width constraint can be changed via the input window 158 to a desired width. Once a new width in entered, the display pane 154 will reflect the new width for array dct_temp. At this point the designer may make other changes such as the format of array dct_temp, other arrays, change the memory type, etc. Or, if he is satisfied, he can then select the “OK” button to apply the changes to the SIF.

Any of the aspects of the methods, systems and behavioral synthesis tools described above may be performed in a distributed computer network. FIG. 14 shows an exemplary network. A server computer 170 may have an associated storage device 172 (internal or external to the server computer). The server computer 170 may be configured to perform any of the implementations of the method described above. The server computer 170 may be coupled to a network, shown generally at 174. One or more client computers, such as those shown at 176, 178, may be coupled to the network 174 and interface with the server computer 170 using a network protocol.

FIG. 15 shows that a GUI or alternative means for allowing a user to alter memory allocation may be provided on a client. The client then interacts with a server for providing other aspects of a behavioral synthesis tool. For instance, in process block 180, the client computer transmits source code describing the behavior of a circuit. The source code could be an original source code or could be an updated version of previously sent source code. In process block 182, the source code is received and read into a behavior synthesis tool provided by the server. The source code is then represented in a SIF in process block 184 that allows memory allocation constraints to be modified by the client. In process block 186, memory allocation information, such as memory allocation constraints, is transmitted to the client for display to a user. The client can modify the memory allocation information if they so desire in process block 184, or approve the constraints and leave them unmodified. If the user modifies the constraints, the modifications are transmitted to the server where process block 190 updates the memory allocation in the SIF based upon the modifications, and process blocks 186 and 188 can be repeated until the user approves the current memory allocation. When the user does approve the memory allocation, process block 192 is processed to create RTL code from the SIF containing the approved memory allocation. Process block 194 then shows the client receiving the RTL code from the server.

Having illustrated and described the principles of the illustrated embodiments, it will be apparent to those skilled in the art that the embodiments can be modified in arrangement and detail without departing from such principles.

For example, although a particular GUI was shown, the user interface can be modified to illustrate the variables and resources in a different way. The particular user interface used is not important to the invention.

Also, the transformation of arrays from one format to another during the packing process can be accomplished in a variety of ways. For instance, an array of a first format can be transformed into an intermediate array in a second format, and then directly packed into a memory. Alternatively, the array of the first format can be transformed as it is being packed into the memory, such that the array is then stored in memory in the desired second format.

Although the formats and methods described herein are generally illustrated in isolation for purposes of clarity, one of skill in the art will recognize that the methods and formats for transforming array layout described herein may be combined or modified. For instance, an array being packed into a customized location, such as shown in FIG. 8, may be packed to the customized location in either of the Endian formats shown in FIG. 5, or packed in an interlacing format as shown in FIGS. 6( a) and 6(b).

Additionally, the data structure stored in database 16 can be structured in a wide variety of ways. The particular data structure used is not important to the invention.

Moreover, although the description focuses on arrays, variables that are associated with single registers in an integrated circuit may also be modified using the formats or tools described. Furthermore, any single variable or non-array data can be represented as an array and processed by embodiments of the described behavioral synthesis tool.

Although a particular data structure is illustrated, those skilled in the art recognize that a wide variety of data structures may be used.

In view of the many possible embodiments to which the principles of our invention may be applied, it should be recognized that the illustrated embodiment is only a preferred example of the invention and should not be taken as a limitation on the scope of the invention. Rather, the scope of the invention is defined by the following claims. We therefore claim as our invention all that comes within the scope of these claims.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7735050Jun 13, 2006Jun 8, 2010Henry YuManaging and controlling the use of hardware resources on integrated circuits
US7831938Nov 21, 2007Nov 9, 2010Mentor Graphics CorporationInteractive interface resource allocation in a behavioral synthesis tool
US8726204Jun 3, 2010May 13, 2014Mentor Graphics CorporationManaging and controlling the use of hardware resources on integrated circuits
Classifications
U.S. Classification716/102, 716/108, 716/104
International ClassificationG06F17/30, G06F17/50
Cooperative ClassificationY10S707/99931, G06F17/5045
European ClassificationG06F17/50D
Legal Events
DateCodeEventDescription
Apr 25, 2008ASAssignment
Owner name: MENTOR GRAPHICS CORPORATION, OREGON
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:PRAKASH, SHIV;BOWYER, BRYAN DARRELL;GUTBERLET, PETER PIUS;REEL/FRAME:020860/0319
Effective date: 20030506