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Publication numberUS20080187018 A1
Publication typeApplication
Application numberUS 11/875,177
Publication dateAug 7, 2008
Filing dateOct 19, 2007
Priority dateOct 19, 2006
Also published asUS8502263, US20080093622, US20130252361, WO2008051503A2, WO2008051503A3
Publication number11875177, 875177, US 2008/0187018 A1, US 2008/187018 A1, US 20080187018 A1, US 20080187018A1, US 2008187018 A1, US 2008187018A1, US-A1-20080187018, US-A1-2008187018, US2008/0187018A1, US2008/187018A1, US20080187018 A1, US20080187018A1, US2008187018 A1, US2008187018A1
InventorsJizhong Li
Original AssigneeAmberwave Systems Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Distributed feedback lasers formed via aspect ratio trapping
US 20080187018 A1
Abstract
Structures including dielectric diffraction gratings. In some embodiments, laser devices include diffraction gratings defined by openings formed in a dielectric material.
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Claims(25)
1. A method of making a laser diode, the method comprising the steps of:
forming a dielectric layer over a top surface of the substrate comprising a first semiconductor material;
defining a plurality of openings in the dielectric layer, the openings extending to the top surface of the substrate;
forming a second semiconductor material in the openings; and
defining a plurality of layers over the second semiconductor material and the dielectric layer to form the laser diode,
wherein portions of the dielectric layer define a diffraction grating.
2. The method of claim 1, wherein the diffraction grating has a width and a spacing selected to provide a duty cycle ranging from 20% to 50%.
3. The method of claim 1, wherein defining the plurality of openings comprises reactive ion etching.
4. The method of claim 1, wherein forming the second semiconductor material comprises selective epitaxy.
5. The method of claim 1, wherein the first semiconductor material comprises silicon and the second semiconductor material comprises at least one of a III-V compound or a II-VI compound.
6. The method of claim 1, wherein the plurality of semiconductor layers comprises at least one of a cladding layer, a grating layer, a graded spacer layer, a graded confining layer, a quantum well region, or a cap layer.
7. The method of claim 1, wherein the laser diode is a distributed feedback laser diode.
8. The method of claim 1, further comprising defining a bottom contact layer over a bottom surface of the substrate.
9. The method of claim 1, wherein a bottom portion of the second semiconductor material comprises lattice-mismatch defects and a top portion of the second semiconductor material is substantially free of lattice-mismatch defects.
10. The method of claim 9, wherein each of the openings has a height sufficient for trapping a majority of the lattice-mismatch defects within the opening.
11. The method of claim 1, wherein each of the plurality of openings has a width less than or equal to a height thereof.
12. A semiconductor device comprising:
a plurality of openings defined in a dielectric layer disposed above a crystalline substrate comprising a first semiconductor material;
a diffraction grating defined by portions of the dielectric layer disposed between the openings;
a second crystalline material disposed within each of the openings, the second crystalline material having a lattice mismatch with the substrate, and a majority of defects arising from lattice mismatch between the second material and the substrate exiting at a surface of the second material within each of the openings; and
a plurality of semiconductor layers disposed above the second crystalline material and the diffraction grating, the plurality of semiconductor layers forming a laser diode.
13. The device of claim 12 wherein the first semiconductor material comprises silicon.
14. The device of claim 12 wherein the second crystalline material comprises at least one of a III-V compound or a II-VI compound.
15. The device of claim 12 wherein the diffraction grating provides a duty cycle ranging from 20% to 50%.
16. The device of claim 12 wherein the laser diode is a distributed feedback laser.
17. A distributed feedback laser device comprising:
a dielectric diffraction grating disposed over a crystalline substrate; and
a plurality of layers disposed above the diffraction grating,
wherein the layers define a laser diode, and at least some of the layers comprise a III-V material lattice-mismatched to the crystalline substrate.
18. The device of claim 17 wherein the diffraction grating comprises a dielectric layer defining a plurality of openings.
19. The device of claim 18, further comprising a crystalline material disposed within the openings, the crystalline material having a lattice constant mismatched to a lattice constant of the crystalline substrate.
20. The device of claim 19, further comprising a contact disposed on a bottom side of the crystalline substrate.
21. The device of claim 19, further comprising an input electrode and an output electrode disposed on a single side of the crystalline substrate.
22. The device of claim 19, wherein a top portion of the crystalline material is substantially free of defects.
23. The device of claim 17, wherein the crystalline substrate comprises a group IV material.
24. A method of making a laser diode, the method comprising the steps of:
forming a dielectric layer over a crystalline substrate comprising a first semiconductor material;
forming a first diffraction grating by:
defining a first plurality of openings in the dielectric layer above a top surface of the crystalline substrate, the first diffraction grating generating a first output wavelength;
forming a second diffraction grating by:
defining a second plurality of openings in the dielectric layer above the top surface of the crystalline substrate, the second diffraction grating generating a second output wavelength; and
defining a plurality of layers over the first and second diffraction gratings to form the laser diode.
25. A distributed feedback laser device comprising:
a dielectric layer disposed over a crystalline substrate comprising a first semiconductor material;
a first diffraction grating defined by a first plurality of openings in the dielectric layer above a top surface of the crystalline substrate, the first diffraction grating generating a first output wavelength;
a second diffraction grating defined by a second plurality of openings in the dielectric layer above the top surface of the crystalline substrate, the second diffraction grating generating a second output wavelength; and
a plurality of layers disposed over the first and second diffraction gratings defining a distributed feedback laser device active region.
Description
RELATED APPLICATION

This application claims priority to U.S. Provisional Patent Application Ser. No. 60/852,781, filed Oct. 19, 2006, the disclosure of which is hereby incorporated by reference in its entirety.

FIELD OF THE INVENTION

This invention relates generally to semiconductor processing and particularly to formation of light-emitting devices based on lattice-mismatched semiconductor structures.

BACKGROUND

Distributed feedback (DFB) lasers with stable longitudinal single-mode operation are critical for applications such as optical-information processing, interferometric measuring, holographic printing, optical gas sensing, atomic spectroscopy and medical diagnoses. Examples of various DFB lasers are shown and described in U.S. Pat. Nos. 5,295,150 and 5,953,361 and articles such as Japanese Journal of Applied Physics, Vol. 43, No. 4B, 2004, pp. 2019-2022, Japanese Journal of Applied Physics Vol. 44, No. 4B, 2005, pp. 2546-2548, and Journal of Crystal Growth 261 (2004) 349-354, incorporated herein by reference in their entireties.

In order to obtain a longitudinal single-mode output, a buried grating structure design is widely used to introduce a periodic refractive index change in the active region of the laser, i.e., the portion of the laser in which light is propagated. This grating structure selectively reflects a certain Bragg wavelength in the laser gain spectrum. By adjusting the grating pitch and the refractive index, single-mode lasing can be realized. Currently, commercial 0.7-2.0 micrometer (μm) DFB lasers are mainly fabricated by employing MOCVD-based two-step growth methods that have several technical challenges. Firstly, conventional holography and chemical wet etching are generally used for grating formation on GaAs or InP-based substrates or pre-growth layers. Since DFB performance characteristics are sensitive to grating pitch width, depth, surface morphology and shape profile, it is a technical challenge to meet specific wavelength requirements without comprehensive process optimization. Furthermore, epitaxial re-growth on a wafer surface having a grating disposed thereon is a common procedure to complete full DFB structure formation. It is well known that mass transport and grated surface oxidation (particularly for laser structures containing Al) are significant issues affecting device performance. Finally, conventional DFB lasers in the wavelength range of 700 nanometer (nm)-2000 nm are primarily fabricated using GaAs or InP as substrates. The costs of laser devices fabricated from non-silicon (Si) wafers are high due to the high cost of the wafers and the inherent low processing yields of laser devices.

SUMMARY OF THE INVENTION

Embodiments of the present invention include systems and methods for providing DFB laser structures on lattice-mismatched semiconductor substrates, e.g., Si, by employing aspect ratio trapping (ART) growth methods. The following benefits are provided by various embodiments.

Low-cost Si may be used as the substrate. Si-based device fabrication technology is more mature than that of III-V compound materials. In addition to significant wafer cost reduction, adapting large-wafer Si processing techniques for III-V laser device processing may enhance the DFB fabrication reliability and product yield, thus leading to better device performance and further reduction of fabrication cost. In addition, a Si substrate has better thermal conductivity and a higher physical hardness than conventional GaAs and InP materials. Using Si as a substrate therefore improves heat depletion control and device packaging.

Furthermore, it may be advantageous to use dielectric sidewalls defined by ART techniques for selective growth as well as for the grating media. In these embodiments, a dielectric mask has multiple functions. First, it enables trapping dislocation defects within a very thin transition layer. These defects are generated at an interface between different materials, e.g., a III-V/Si interface, due to lattice mismatch and thermal-expansion differences between Si and III-V compounds. By employing an ART-based surface engineering process, device-quality laser materials may be grown on lattice-mismatched, e.g., Si, substrates.

Second, since interface defects are trapped toward a bottom portion of the trench, the grating profile may be formed in an upper portion of epitaxial films, e.g., III-V materials, by utilizing a dielectric (e.g., oxide) pattern as an optical grating media. Since the first or second order grating pitch width for commonly used DFB lasers is on a submicron scale, ART masks have a good dimensional match to the grating pitch requirements for making DFB lasers.

Another benefit is that ART patterning can provide a large refractive index difference between the dielectric material, e.g., SiO2 (1.46), and the epitaxially grown material, e.g., GaAs (3.2). This refractive index difference is larger than the refractive index difference between conventionally used materials such as GaAs and AlGaAs, and leads to a high optical coupling constant. The simplified grating formation procedure, which avoids a re-growth process, is another significant benefit in comparison to conventional methods of forming DFB structures.

The use of well developed integrated circuit (IC) processes for forming the grating pattern allows for flexibility in grating geometry because selection of grating duty cycle and the variation of grating pitches can be realized in an initial photolithography process. This offers advantages over conventional post-growth holographic techniques.

The approaches described herein for realizing III-V/Si integration coupled with integration with conventional Si-based process enable a variety of other benefits as well, such as accommodating chip-scale integration of DFB lasers with other electronic devices.

In an aspect, the invention features a method of making a laser diode. The method includes forming a dielectric layer over a top surface of the substrate including a first semiconductor material. A plurality of openings are defined in the dielectric layer, with the openings extending to the top surface of the substrate. A second semiconductor material is formed in the openings. A plurality of layers are defined over the second semiconductor material and the dielectric layer to form the laser diode, with portions of the dielectric layer defining a diffraction grating.

One or more of the following features may be included. The diffraction grating may have a width and a spacing selected to provide a duty cycle ranging from 20% to 50%. Defining the plurality of openings may include reactive ion etching. Forming the second semiconductor material may include selective epitaxy. The first semiconductor material may include silicon and the second semiconductor material may include a III-V compound and/or a II-VI compound. The plurality of semiconductor layers may include a cladding layer, a grating layer, a graded spacer layer, a graded confining layer, a quantum well region, and/or a cap layer. The laser diode may be a distributed feedback laser diode.

A bottom contact layer may be defined over a bottom surface of the substrate. A bottom portion of the second semiconductor material may include lattice-mismatch defects and a top portion of the second semiconductor material may be substantially free of lattice-mismatch defects. Each of the openings may have a height sufficient for trapping a majority of the lattice-mismatch defects within the opening. Each of the plurality of openings may have a width less than or equal to a height thereof.

In another aspect, the invention features a semiconductor device. The semiconductor device includes a plurality of openings defined in a dielectric layer disposed above a crystalline substrate comprising a first semiconductor material. A diffraction grating defined by portions of the dielectric layer is disposed between the openings. A second crystalline material is disposed within each of the openings, the second crystalline material having a lattice mismatch with the substrate, and a majority of defects arising from lattice mismatch between the second material and the substrate exiting at a surface of the second material within each of the openings. A plurality of semiconductor layers are disposed above the second crystalline material and the diffraction grating, the plurality of semiconductor layers forming a laser diode.

One or more of the following features may be included. The first semiconductor material may include or consist essentially of silicon. The second crystalline material may include a III-V compound and/or a II-VI compound. The diffraction grating may provide a duty cycle ranging from 20% to 50%. The laser diode may be a distributed feedback laser.

In another aspect, the invention features a distributed feedback laser device including a dielectric diffraction grating disposed over a crystalline substrate and a plurality of layers disposed above the diffraction grating. The layers define a laser diode, and at least some of the layers comprise a III-V material lattice-mismatched to the crystalline substrate.

One or more of the following features may be included. The diffraction grating may include a dielectric layer defining a plurality of openings. A crystalline material may be disposed within the openings, the crystalline material having a lattice constant mismatched to a lattice constant of the crystalline substrate. A contact may be disposed on a bottom side of the crystalline substrate. An input electrode and an output electrode may be disposed on a single side of the crystalline substrate. A top portion of the crystalline material may be substantially free of defects. The crystalline substrate may include a group IV material.

In another aspect, the invention features a method of making a laser diode. The method includes forming a dielectric layer over a crystalline substrate including a first semiconductor material. A first diffraction grating is formed by defining a first plurality of openings in the dielectric layer above a top surface of the crystalline substrate, the first diffraction grating generating a first output wavelength. A second diffraction grating is formed by defining a second plurality of openings in the dielectric layer above the top surface of the crystalline substrate, the second diffraction grating generating a second output wavelength. A plurality of layers is defined over the first and second diffraction gratings to form the laser diode.

In yet another aspect, the invention features a distributed feedback laser device. The distributed feedback laser device includes a dielectric layer disposed over a crystalline substrate including a first semiconductor material. A first diffraction grating is defined by a first plurality of openings in the dielectric layer above a top surface of the crystalline substrate, the first diffraction grating generating a first output wavelength. A second diffraction grating is defined by a second plurality of openings in the dielectric layer above the top surface of the crystalline substrate, the second diffraction grating generating a second output wavelength. A plurality of layers disposed over the first and second diffraction gratings define a distributed feedback laser device active region.

BRIEF DESCRIPTION OF FIGURES

In the drawings, like reference characters generally refer to the same features throughout the different views. Also, the drawings are not necessarily to scale, emphasis instead being placed upon illustrating the aspects of the invention.

FIGS. 1-4 are schematic cross-sectional view illustrating structures formed in accordance with an embodiment of the invention.

DETAILED DESCRIPTION

Referring to FIG. 1, a method for forming a relatively low defect or defect-free semiconductor material on a lattice-mismatched substrate is illustrated. A substrate 100 includes a first crystalline semiconductor material S1. The substrate 100 may be, for example, a bulk silicon wafer, a bulk germanium wafer, a semiconductor-on-insulator (SOI) substrate, or a strained semiconductor-on-insulator (SSOI) substrate. The substrate 100 may include or consist essentially of the first semiconductor material S1, such as a group IV element, e.g., germanium or silicon. In an embodiment, substrate 100 includes or consists essentially of n-type (100) silicon. The substrate 100 may include a material having a first conductivity type, e.g., n+Si.

A dielectric layer 110 is formed over the semiconductor substrate 100. The dielectric layer 110 may include or consist essentially of a dielectric material, such as silicon nitride or silicon dioxide. The dielectric layer 110 may be formed by any suitable technique, e.g., thermal oxidation or plasma-enhanced chemical vapor deposition (PECVD). As discussed below, the dielectric layer may have a thickness t1 corresponding to a desired height h of crystalline material to be deposited in an opening formed through the dielectric layer. In some embodiments, the thickness t1 of the dielectric layer 110 may be in the range of, e.g., 25-1000 nm. In a preferred embodiment, the thickness t1 is 600 nm.

A mask (not shown), such as a photoresist mask, is formed over the substrate 100 and the dielectric layer 110. The mask is patterned to expose at least a portion of the dielectric layer 110. The exposed portion of the dielectric layer 110 is removed by, e.g., reactive ion etching (RIE) to define an opening 120. Opening 120 may be defined by at least one sidewall 130, and may extend to a top surface 135 of the substrate 100. The height h of the sidewall 130 corresponds to the thickness t1 of the dielectric layer 110, and may be at least equal to a predetermined distance H from a top surface 135 of the substrate.

The opening may be substantially rectangular in terms of cross-sectional profile, a top view, or both, and have a width w that is smaller than the length l (not shown) of the opening. For example, the width w of the opening may be less than about 500 nm, e.g., about 10-500 nm, and the length l of the opening may exceed each of w and H. The ratio of the height h of the opening to the width w of the opening 120 may be ≧0.5, e.g., ≧1. The opening sidewall 130 is configured to allow defects that arise within the material S2 to exit the material below the height h as described below. The opening sidewall 130 is not necessarily strictly vertical.

A second crystalline semiconductor material S2, i.e., crystalline material 140, is formed in the opening 120. The crystalline material 140 may include or consist essentially of a group IV element or compound, a III-V compound, or a II-VI compound. Examples of suitable group IV elements or compounds include germanium, silicon germanium, and silicon carbide. Examples of suitable III-V compounds include gallium antimonide, gallium arsenide, gallium nitride, gallium phosphide, aluminum antimonide, aluminum arsenide, aluminum nitride, aluminum phosphide, indium antimonide, indium arsenide, indium nitride, indium phosphide, and their ternary or quaternary compounds such as indium gallium arsenide, indium gallium nitride, indium gallium phosphide, etc. Examples of suitable II-VI compounds include zinc selenide, zinc sulfide, cadmium selenide, cadmium sulfide, and their ternary or quaternary compounds.

The crystalline material 140 may be formed by selective epitaxial growth in any suitable epitaxial deposition system, including, but not limited to, metal-organic chemical vapor deposition (MOCVD), atmospheric-pressure CVD (APCVD), low- (or reduced-) pressure CVD (LPCVD), ultra-high-vacuum CVD (UHCVD), molecular beam epitaxy (MBE), or atomic layer deposition (ALD). In the CVD process, selective epitaxial growth typically includes introducing a source gas into the chamber. The source gas may include at least one precursor gas and a carrier gas, such as, for example, hydrogen. The reactor chamber may be heated by, for example, RF-heating. The growth temperature in the chamber may range from about 300 C. to about 900 C., depending on the composition of the crystalline material. The growth system may also utilize low-energy plasma to enhance the layer growth kinetics.

The epitaxial growth system may be a single-wafer or multiple-wafer batch reactor. Suitable CVD systems commonly used for volume epitaxy in manufacturing applications include, for example, an Aixtron 2600 multi-wafer system available from Aixtron, based in Aachen, Germany; an EPI CENTURA single-wafer multi-chamber systems available from Applied Materials of Santa Clara, Calif.; or an EPSILON single-wafer epitaxial reactor available from ASM International based in Bilthoven, The Netherlands.

In an exemplary process, a two-step growth technique is used to form high-quality crystalline material 140, consisting essentially of GaAs, in the opening 120. First, the substrate 100 and dielectric layer 110 are thermally annealed with hydrogen at approximately 800 C. for approximately 15 minutes to desorb a thin volatile oxide from that substrate surface 135 that may be produced during pre-epitaxy wafer preparation. Chamber pressure during annealing may be in the range of approximately 50-100 Torr, for example 75 Torr. After annealing, the chamber temperature is cooled down with hydrogen flow. In order to suppress anti-phase boundaries (APDs) on substrate surface 135, a pre-exposure to As for about 1 to 5 minutes is performed. This step helps ensure uniform coverage of the opening surface with an AsAs monolayer. This pre-exposure is achieved by flowing AsH3 gas through the reactor at a temperature of approximately 460 C. Then, a gallium precursor, e.g., triethylgallium (TEG) or trimethylgallium (TMG), is introduced into the chamber together with AsH3 gas at a lower growth temperature, e.g., approximately 400 C. to 450 C. to promote the initial GaAs nucleation process on the As pre-layer surface. A slow growth rate of about 2 to 4 nm per minute with V/III ratio of about 50 may be used to obtain this initial GaAs buffer layer, with a thickness of the GaAs buffer layer being selected from a range of about 20 to 100 nm.

In one embodiment, a layer of n-type GaAs is grown above the buffer layer at a constant growth temperature of approximately 680 C. and a V/III ratio of approximately 80 to obtain relatively defect-free GaAs material inside the opening 120. The combined thickness t2 of the initial GaAs buffer layer and the n-type GaAs grown above the buffer layer may be less than or greater than the dielectric mask thickness t1. The top portion of the GaAs material may coalesce with GaAs formed in neighboring openings (not shown) to form an epitaxial layer. The width w2 of the crystalline material 140 extending over a top surface 160 of the dielectric layer 110 may be greater than the width w of the opening 120. The overall layer thickness t2 of the crystalline material 140 may be monitored by using pre-calibrated growth rates and in situ monitoring equipment, according to methods known in the art.

Dislocation defects 150 in the crystalline material 140 reach and terminate at the sidewalls of the opening 120 in the dielectric material 110 at or below the predetermined distance H from the surface 135 of the substrate, such that dislocations in the crystalline material 140 decrease in density with increasing distance from the bottom portion of the opening 120. Accordingly, the upper portion of the crystalline material has a substantially reduced number of dislocation defects. Various dislocation defects such as threading dislocations, stacking faults, twin boundaries, or anti-phase boundaries may thus be generally eliminated from the upper portion of the crystalline material.

The crystalline material 140 may be considered to have two portions: a lower portion for trapping dislocation defects and an upper portion which either (a) incorporates the laser or LED epitaxial layers or (b) serves as a template for the subsequent epitaxial growth of the laser or LED epitaxial layers. The height h of the crystalline material thus has two components: the height htrapping of the lower portion (where defects are concentrated) and the height hupper of the upper portion (which is largely free of defects). The height htrapping of the trapping portion may be selected from a range of about w≦htrapping≦2w, to ensure effective trapping of dislocation defects. The actual value of htrapping required may depend upon the type of dislocation defects encountered, which may depend on the materials used, and also upon the orientation of the opening sidewalls. In some instances, the height htrapping can be greater than that required for effective defect trapping, in order to ensure that the dislocation defects are trapped at a sufficient distance away from the upper portion, so that deleterious effects of dislocation defects upon device performance are not experienced. For example, htrapping may be, e.g., 10-100 nm greater than required for effective trapping of defects. For the upper portion, the height hupper may be selected from the range of approximately w≦hupper≦10 w.

Referring to FIGS. 2 a and 2 b, in an exemplary embodiment, the process described with respect to FIG. 1 is used to form a laser diode 200, e.g., a DFB laser diode that emits optical radiation at a wavelength less than 880 nm. The laser diode 200 is formed over the crystalline material 140. The laser diode 200 includes a plurality of openings 120 with dielectric layer 110 portions, i.e., ridges, disposed between the openings 120. The dielectric layer 110 is patterned to define a series of ridges defining a grid layer that forms a diffraction grating 210 of the laser structure 200.

The laser diode 200 includes a number of layers that may be formed by epitaxial growth in any suitable epitaxial deposition system, including, but not limited to, MOCVD, APCVD, LPCVD, UHVCVD, MBE, or ALD.

More particularly, laser diode 200 comprises a substrate 100 that includes a semiconductor material of one conductivity type. The described embodiment has an n-type substrate, including n+ type Si. One of skill in the art will recognize that other embodiments are possible including, e.g., other material compositions and conductivity types. The substrate 100 has a top surface 220 and a bottom surface 230. The diffraction grating 210 is defined by dielectric layer 110 portions formed on the top substrate surface 220. The openings 120 of the diffraction grating 210 have a selected width and a spacing ratio (duty cycle) ranging from 20% to 50% and preferably from 35% to 40%. The duty cycle is a ratio of the width of a dielectric ridge to the grating pitch, with the grating pitch Λ being equal to a sum of the opening width w and the spacing d between openings 120 (with spacing d being equal to a width of a diffraction grating 210 ridge.) For example, the width w of each opening 120 may be 250 nm and a spacing d between openings 120 may be 200 nm. The grating pitch Λ determines the wavelength λ of the laser diode 200, such that λ=2neΛ/m, where ne is the effective refractive index of grating layer 270, and m is an integer greater than zero (1, first order; 2, second order, . . . ).

To use the substrate as an electrical contact medium, the electrical conductivity (i.e., doping) type of the material initially formed on the substrate, e.g., the initial III-V materials on Si, should be the same as that of the substrate. In one embodiment, crystalline material 140 may include a low temperature buffer layer such as n-type GaAs deposited onto the exposed top Si surface 220. The GaAs buffer layer has a thickness of about 15 nm to 30 nm with a preferred n-type doping level of about 21018/cm3.

A first cladding layer 268 including n-type Al0.6Ga0.4As is grown on the crystalline material 140 at an elevated temperature to a doping level of 0.2-21018/cm3, with a preferred thickness of between 0.2-0.8 μm. The combined thickness of the crystalline material 140 and the first cladding layer 268 disposed within the openings 120 is less than a height of the grid layer.

A grating layer 270 is grown on the first cladding layer 268. The grating layer 270 may include n-type Al0.4Ga0.6As. The grating layer 270 is n-type doped at a doping level of between 21016/cm3 to 51018/cm3 and preferably about 51017/cm3. The grating layer 270 has a thickness of between about 20 and 500 nm, preferably about 120 nm. Since the grating layer 270 is partially grown inside the openings 120 and continuously grown after coalescence over the dielectric grids 110, the top parts of the dielectric grids defined by dielectric layer 110 portions are surrounded by the grating layer 270.

A graded spacer layer 272 is grown on the grating layer 270. The graded spacer layer 272 includes AlGaAs, preferably Al0.6Ga0.4As at the surface of grating layer and Al0.4Ga0.6As away from the grating layer 270. The spacer layer 272 is n-doped with a doping level of between 21016/cm3 to 51018/cm3 and preferably about 51017/cm3. The spacer layer 272 has a thickness selected from a range of between about 20 and 500 nm, preferably about 100 nm.

A graded first confining layer 274, i.e., a first waveguide, of undoped Al0.60-0.20Ga0.40-0.80As is formed over the graded spacer layer 272. The graded first confining layer 274 has a thickness selected from a range of between about 20 and 400 nm, preferably about 120 nm.

An active layer (also referred to herein as active region), including a multi-quantum well region 280 is formed over graded first confining layer 274. Referring also to FIG. 3, the multi-quantum well region 280 includes a first quantum well layer 276 of undoped GaAs having a thickness of, e.g., about 3 to 7 nm. Disposed over the first quantum well layer 276 is a barrier layer 275 of Al0.05-0.60Ga0.40-0.95As, preferably Al0.25Ga0.75As. The barrier layer 275 has a thickness of between 5 and 100 nm, and preferably has a thickness of 40 nm. A second quantum well layer 278 of undoped GaAs is disposed over the barrier layer 275. The second quantum well layer 278 has a thickness of about 3-7 nm.

A graded second confining layer 282, i.e., a second waveguide, of undoped Al0.20-0.60Ga0.80-0.40As is formed over the second quantum well layer 278. The graded second confining layer 282 has a thickness of between about 20 and 400 nm and preferably 120 nm.

A second cladding layer 284 is formed over the graded second confining layer 282. The second cladding layer 284 is graded p-type, and includes Al0.4-0.6Ga0.6-0.4As as the second confining layer, with a higher content Al at the surface away from the graded second confining layer 282. The second cladding layer 284 is p-type doped with, e.g., carbon, zinc, or magnesium to a level of between 11017 cm−3 to 51018 cm−3, and has a thickness of between 300 nm and 3000 nm, preferably 1000 nm.

The illustrated configuration forms a single mode laser with the indicated optical field distribution 285.

A p+ type cap layer 286 of GaAs is grown over the second cladding layer 284. The cap layer 286 is doped to a level of between 51017 cm−3 to 51020 cm−3, and preferably about 1-31019 cm−3, and has a thickness of between 10 nm and 500 nm, preferably about 300 nm thick.

A pair of spaced parallel grooves 288 (see FIG. 2 a) is formed in the cap layer 286 by photolithography and etch steps. The grooves 288 extend between the ends of the laser diode 200. The grooves 288 are spaced apart at a distance of about 1 μm to 10 μm and preferably about 10 μm, and extend into the second cladding layer 284 by a sufficient extent to restrict lateral transverse modes. An encapsulating layer 290 of an insulating material, such as SiO2 or SiNx is deposited over cap layer 286 and the surface of the grooves 288. The encapsulating layer 290 has an opening 292 formed therethrough over a portion of the cap layer 286 disposed between the grooves 288. A conducting top contact layer (electrode) 294, e.g., a p-type contact layer is formed over the insulating layer 290 and extends through the opening 292 to contact the surface of the cap layer 286. The conducting top contact layer 294 may be formed by, e.g., deposition, sputtering, or evaporation. The conducting top contact layer 294 includes a material that makes good electrical contact to the material of the cap layer 286, e.g., a Ti/Pt/Au tri-layer.

In an embodiment, an electrically insulated diode (EID) structure may be added (not shown).

After thinning the backside of the substrate by conventional wafer thinning techniques, preferably to 100 μm, a conducting bottom contact layer (electrode) 296 is formed on the bottom surface 230 of the substrate 100 by, e.g., deposition or evaporation. The conducting bottom contact layer 296 is formed from a material that makes good electrical contact to the material of the substrate 100; in a preferred embodiment, the conducting bottom contact layer 296 includes a tri-layer of AuGe/Ni/Au with n-type conductivity.

Referring to FIG. 2 c, input and output electrical contacts (electrodes) may be also fabricated on a single side, i.e., the same side, of the substrate to improve electrical pumping efficiency and to reduce optical coupling loss at the III-V/Si interface. This can be realized by techniques known to one of skill in the field, such as by use of an etch-stop layer (not shown) inserted between the graded first confining layer (waveguide) 274 and graded spacer layer 272, which are disposed between the active region or multiple quantum well 280 and the grating layer 270, as shown in FIG. 2 c. For example, after the formation of the cap layer 286 and grooves 288, portions of overlying materials may be removed by deep trench etching to expose a region of graded spacer layer 272. A dielectric insulator 291 is deposited to protect a sidewall exposed by the removed portions of overlying material, as well as to cover an exposed portion of graded spacer layer 272. The dielectric insulator 291 may include the same material and formed in the same step as encapsulating layer 290.

A mask is defined by photolithography, and a bottom portion of the dielectric insulator 291 disposed over graded spacer layer 272 is removed by e.g., etching, to define an opening 292′, as well as opening 292 in the encapsulating layer 290.

Opening 292′ is masked by photolithographic methods, and electrode 294 is deposited. Then, electrode 294 is masked and an n-contact electrode 297 is defined by the formation of a thin film metal coating in opening 292′ directly on top of the exposed top surface of graded spacer layer 272. Thus, the electrodes 294, 297 are disposed on the same side of the substrate. Electrode 297 may be an output electrode and electrode 294 may be an input electrode, or vice versa.

The ends of the laser diode 200 are reflective, with at least one of the ends being partially transparent to allow radiation to be emitted from the device.

FIG. 4 is a schematic illustration of a two-section DFB laser. Structure 200′ has two diffraction gratings 210 and 210′ with different grating duty cycles based on the two different grating sections defined by dielectric layers 110, 111. Top contacts 294, 298 correspond to the two diffraction gratings 210, 210′, respectively. When laser 200′ is electrically pumped, one or two wavelengths λ1, λ2 of laser output, depending on current driving selecting, may be obtained from the same laser facet 277 that includes the emitting surfaces of graded first confining layer 274, multi-quantum well region 280, and graded second confining layer 282. Each of the laser outputs is longitudinal single mode.

Based on above description and techniques illustrated in FIGS. 2 a-2 c and 3, those familiar with the art can apply the concepts and mask design functionalities available using ART techniques to implement a variety of different multi-section DFB lasers or related optoelectronic structures such as sensors, modulators, etc.

The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments are therefore to be considered in all respects illustrative rather than limiting on the invention described herein. Scope of the invention is thus indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are intended to be embraced therein.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US8034697Sep 18, 2009Oct 11, 2011Taiwan Semiconductor Manufacturing Company, Ltd.Formation of devices by epitaxial layer overgrowth
US8242510 *Nov 15, 2010Aug 14, 2012Intersil Americas Inc.Monolithic integration of gallium nitride and silicon devices and circuits, structure and method
US8574968 *Jul 25, 2008Nov 5, 2013SoitecEpitaxial methods and templates grown by the methods
US20090098343 *Jul 25, 2008Apr 16, 2009Chantal ArenaEpitaxial methods and templates grown by the methods
US20110180806 *Nov 15, 2010Jul 28, 2011Intersil Americas Inc.Monolithic integration of gallium nitride and silicon devices and circuits, structure and method
WO2010033813A2 *Sep 18, 2009Mar 25, 2010Amberwave System CorporationFormation of devices by epitaxial layer overgrowth
Classifications
U.S. Classification372/50.11, 257/E33.005, 257/E21.002, 438/32
International ClassificationH01S5/12, H01L21/02, H01L33/00, H01L33/12
Cooperative ClassificationH01L33/08, H01L21/02573, H01L21/0262, H01S5/227, H01L21/02524, H01L21/02639, H01L21/02381, H01L33/0066, H01L21/02647, H01S5/223, H01L33/16, H01S5/0207, H01L21/02546, H01S5/3202, H01L21/02538, H01S5/2234, H01L33/12
European ClassificationH01L33/00G3B, H01L33/12, H01S5/223, H01L21/02K4A1A3, H01L21/02K4E3S3, H01L21/02K4C1A, H01L21/02K4C1B3, H01L21/02K4C1B, H01L21/02K4E3S7, H01L21/02K4E3C
Legal Events
DateCodeEventDescription
Dec 6, 2007ASAssignment
Owner name: AMBERWAVE SYSTEMS CORPORATION, NEW HAMPSHIRE
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LI, JIZHONG;REEL/FRAME:020207/0067
Effective date: 20071129