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Publication numberUS20080191249 A1
Publication typeApplication
Application numberUS 11/703,965
Publication dateAug 14, 2008
Filing dateFeb 8, 2007
Priority dateFeb 8, 2007
Also published asUS7750470
Publication number11703965, 703965, US 2008/0191249 A1, US 2008/191249 A1, US 20080191249 A1, US 20080191249A1, US 2008191249 A1, US 2008191249A1, US-A1-20080191249, US-A1-2008191249, US2008/0191249A1, US2008/191249A1, US20080191249 A1, US20080191249A1, US2008191249 A1, US2008191249A1
InventorsYeou-Lang Hsieh, Chin-Min Lin, Jiann-Jong Wang
Original AssigneeTaiwan Semiconductor Manufacturing Co., Ltd.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Methods for planarization of dielectric layer around metal patterns for optical efficiency enhancement
US 20080191249 A1
Abstract
A method and system for improving planarization and uniformity of dielectric layers for providing improved optical efficiency in CCD and CMOS image sensor devices. In various embodiments, a dielectric planarization method for achieving better optical efficiency includes first depositing a first dielectric having an optically transparent property on and around a metal pattern. Optical sensors are formed in or on the substrate in areas between metal features. The metal pattern protects a sensor situated therebetween and thereunder from electromagnetic radiation. After the first dielectric layer is polished using CMP, a slanted or inclined surface is produced but this non-uniformity is eliminated using further planarization processes that produce a uniform total dielectric thickness for the proper functioning of the sensor.
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Claims(8)
1. A semiconductor structure for a complementary metal-oxide-semiconductor (CMOS) image sensor, comprising:
a first metal feature disposed above a semiconductor substrate;
a second metal feature disposed adjacent to the first metal feature on a same level thereat above the semiconductor substrate;
a first dielectric layer deposited between the first and second metal features; and
a second dielectric layer covering the first metal feature, the second metal feature and the first dielectric layer,
wherein the second dielectric layer is substantially flat over the first dielectric layer.
2. The semiconductor structure of claim 1, further comprising a sensing unit disposed on the semiconductor substrate under the first dielectric layer between the first and second metal features.
3. The semiconductor structure of claim 1, wherein the first dielectric layer has a maximum thickness smaller than that of the first or second metal feature.
4. The semiconductor structure of claim 1, wherein the first dielectric layer has a maximum thickness greater than that of the first or second metal feature.
5. The semiconductor structure of claim 1, wherein the first dielectric layer is substantially optical transparent.
6. The semiconductor structure of claim 1, wherein the second dielectric layer is substantially optical transparent.
7. The semiconductor structure of claim 1, further comprising a layer of color filter formed overlying the second dielectric layer.
8. The semiconductor structure of claim 1, further comprising a layer of microlenses formed overlying the second dielectric layer.
Description
RELATED APPLICATION

This divisional application is related to and claims priority of provisional U.S. Patent Application Ser. No. 60/562,086, filed Apr. 13, 2004 entitled “METHOD FOR PLANARIZATION OF DIELECTRIC LAYER BETWEEN TWO METAL PATTERNS” and U.S. patent application Ser. No. 11/084,228, filed Mar. 16, 2005 entitled “METHODS FOR PLANARIZATION OF DIELECTRIC LAYER AROUND METAL PATTERNS FOR OPTICAL EFFICIENCY ENHANCEMENT.”

BACKGROUND

The present invention relates generally to semiconductor processing, and more particularly to structures and methods for planarization of dielectric layers around metal patterns for optical efficiency enhancement.

The development and deployment of optical devices such as CMOS image sensor and charge-coupled devices (CCD) have been growing rapidly in recent years. These devices have many special requirement compared to general logic device. For example, one of the requirements is the reduction of thickness of optical transparent dielectric in a backend passivation layer such as silicon oxide, silicon nitride or silicon oxynitride. Another requirement is the uniform thickness of the optically transparent dielectric material in the regions between metal patterns, as well as the uniform thickness of the dielectric material over the patterned metal. The metal pattern is used to block electromagnetic radiation, especially light, in the optical wavelength range. The incident light will pass through locations between metal patterns to an optical sensing unit formed in or on the substrate. The non-uniform thickness of optical transparent dielectric in the areas between metal patterns will change the refractive index which results in discolor phenomenon.

Due to the loading effect of chemical mechanical polishing (CMP), the dielectric between adjacent metal patterns may not be planar; rather, the dielectric may include a slanted or inclined surface. The slanted or incline surface of dielectric is indicative of thickness non-uniformity, which not only causes visual discolor but also degrades a sensor's performance.

Therefore, desirable in the art of semiconductor processing are methods to improve planarization of dielectric layers for better optical efficiency.

SUMMARY

In view of the foregoing, the following provides methods for improving planarization of dielectric layers for better optical efficiency.

In various embodiments, various dielectric planarization methods for achieving better optical efficiency are provided. For example, a first dielectric layer having at least an optically transparent property is deposited on and around a metal pattern comprising one or more deposited metals. The metal of the metal pattern protects sensors situated therebetween and thereunder, from electromagnetic radiation. After the first dielectric layer is polished using chemical mechanical polishing (CMP), the resulting surface may be slanted or inclined, i.e. non-planar, and not parallel to the substrate. The slanted surface is removed from the first dielectric layer and a uniform and planarized dielectric surface for the proper functioning of the sensor, is formed.

According to one embodiment, a mask with the reverse of the metal pattern is utilized to planarize the dielectric. Photo processes and oxide etching processes are used to etch the dielectric and are followed by a CMP process to yield a planarized dielectric layer.

The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B illustrate a conventional flow for treating dielectric layers on and between metal patterns.

FIGS. 2A through 2D illustrate a flow for treating dielectric layers in accordance with the first exemplary embodiment of the present invention.

FIGS. 3A through 3C illustrate a flow for treating dielectric layers in accordance with the second exemplary embodiment of the present invention.

FIGS. 4A through 4C illustrate a flow for treating dielectric layers in accordance with the third exemplary embodiment of the present invention.

FIGS. 5A through 5C illustrate a flow for treating dielectric layers in accordance with the fourth exemplary embodiment of the present invention.

DESCRIPTION

The following detailed description provides methods for planarization of dielectric layers on and around metal patterns for enhancing optical efficiency.

FIGS. 1A and 1B illustrate a conventional flow for treating dielectric layers on and between metal patterns. The conventional flow includes two steps shown in the two figures. Metals 106 and 108 within both the steps are implemented to block electromagnetic radiation, especially light, in the optical wavelength range. The metals 106 and 108 may be formed from the same metal film or from different metal. Metals 106 and 108 may include different dimensions, and depending on the underlying topography and whether metals 106 and 108 are formed from the same or a different film, it is understood that the heights of metals 106 and 108 may be slightly different. The two steps shown in FIGS. 1A and 1B illustrate how this difference in height can create problems for sensor's performance.

Referring to FIG. 1A, a first dielectric layer 110 is deposited on and between the metals 106 and 108. First dielectric layer 110 is optically transparent. The height of the surface of the first dielectric layer 110 will vary throughout the entire surface due to its conformality and the gap between the metals 106 and 108 and the height will also vary due to the dimensional differences (vertical and horizontal) of the metals 106 and 108. The first dielectric layer 110 then undergoes chemical mechanical polishing (CMP) in the step as shown in FIG. 1B. Due to the loading effect of CMP and the non-uniformity height of the first dielectric layer 110, the polishing process will result in the dielectric material between and over the metals 106 and 108 having a slanted or inclined surface which is not uniformly parallel to the substrate over which it is formed and may be non-planar. The slanted or inclined surface of dielectric is indicative of thickness non-uniformity, which not only causes visual discoloration but also degrades sensors performance since it results in a different distance between features such as lenses formed over the dielectric, and the sensing units formed in or on the substrate and below the dielectric.

FIGS. 2A through 2D illustrate a flow for treating dielectric layers in accordance with the first embodiment of the present invention. This flow shows a method for uniform planarization of a dielectric surface, and is broken down into four steps for illustrative purposes, in one exemplary embodiment.

Referring to FIG. 2A, metals 210 and 212 are implemented to block electromagnetic radiation, especially light, in the optical wavelength range. The metals 210 and 212 are metal features and, collectively, are considered a metal pattern. The pattern may be formed by plasma etching, in one embodiment. The metals 210 and 212 can be lines, islands, or pads that are made of metal such as copper, aluminum, various metal compounds, or metal alloys. The metals 210 and 212 may be formed from the same metal film or from different metal films. Metals 210 and 212 may be different in dimension size, and depending on the underlying topography and whether metals 210 and 212 are formed from the same or a different film, the heights of metals 212 and 210 may be different. Sensing units 202 may be formed in or on the substrate 220 in region 222 that lies between the metals 210 and 212. The sensing units 202 may be used to form optical sensors such as a CCD, or a 3-transistor or 4-transistor pinned photodiode CMOS image sensor. For example, a 4-transistor pinned photodiode pixel sensor may be formed on semiconductor substrate 220.

A first dielectric layer 214 is deposited after the formation of the metals 210 and 212 through plasma deposition or chemical vapor deposition. The first dielectric layer 214 could be formed by plasma enhanced chemical vapor deposition (PECVD) or high density plasma chemical vapor deposition (HDPCVD) or a combination thereof. The first dielectric layer 214 may be a silicon oxide or another suitable dielectric material and is generally a substantially optical transparent material. The first dielectric layer 214 may be one or more films and may include a total thickness ranging from 10000 Å to 25000 Å and in one embodiment may be two films with a combined thickness of about 18000 Å. The height of the surface of the first dielectric layer 214 will vary throughout due to the conformality of the film(s), and the gap between the metals 210 and 211 and also due to the dimensional differences of the metals 210 and 212. A CMP process is then performed on the first dielectric layer 214 as shown in FIG. 2B. Due to the loading effect of CMP and the non-uniform height of the first dielectric layer 214, the polished dielectric material between the metals 210 and 212 will suffer a slanted or inclined surface which is not uniformly parallel to the substrate 220 over which it is formed and may be non-planar and uneven. The slanted or inclined surface of dielectric is indicative of thickness non-uniformity, which, in image sensor devices, not only causes visual discoloration but also degrades sensors and adversely affects optical performance. The thickness of dielectric layer 214 that remains over the first metal 210 and/or second metal 212 may vary and may be about 4000 A in one exemplary embodiment.

Referring to FIG. 2C, the first dielectric layer 214 is etched all the way down to the metals 210 and 212 using a selective etch process. Due to this etching process, the upper surface of the remaining first dielectric layer 214 is lower than the upper surfaces of the metals 210 and 212. The thickness of the remaining dielectric between the metal features may be about 50% or more of the thickness of one or both of the metals 210 and 212. The slanted surface of the first dielectric layer 214 is eliminated by the end of this step. Referring to FIG. 2D, a second dielectric layer 216, which is substantially an optical transparent material made by CVD or Spin-On method, is next deposited as a passivation layer above the first dielectric layer 214 and the metals 210 and 212. Various thicknesses may be used. Throughout the substrate 220, the total thickness of the dielectric materials over the metal areas is substantially the same and the total thickness of the dielectric material in areas between the metal areas i.e., over the optical sensors 202, is substantially the same. A layer 224 of color filters, microlenses or associated features are then formed over the optical sensors 202 formed in the substrate 220 to form CMOS image sensors and CCD devices. With improved uniformity of the dielectric layers, any visual discoloration is improved or eliminated, thereby allowing sensors and other devices to function properly.

FIGS. 3A through 3C illustrate a flow for treating dielectric layers in accordance with the second embodiment of the present invention. The flow shows another method used for uniform planarization of dielectric surface where both a first dielectric layer and metals are treated with CMP before depositing a second dielectric layer.

Referring to FIG. 3A, metals 308 and 310 are implemented to block electromagnetic radiation, especially light, in the optical wavelength range. The metals 308 and 310 are metal features and may be formed from the same metal film or from different metal films. Metals 308 and 310 may be different in dimension size, and depending on the underlying topography and whether metals 308 and 310 are formed from the same or a different film, the heights of metals 310 and 308 may be different. A first dielectric layer 312 is deposited after the metals 308 and 310 are formed by plasma etching. First dielectric layer 312 is as described in conjunction with first dielectric layer 214 and may by be multiple layers. Referring to FIG. 3B, CMP is then performed on the first dielectric layer 312 resulting in the uneven, slanted surface (not shown) also described in conjunction with FIG. 2B and shown in FIG. 1B. A further CMP operation is also performed on the metals 308 and 310, using a process in which the polishing rate of metal is greater than that of the first dielectric layer 312. This results in the upper surface of the remaining first dielectric layer 312 in the space between the metals 308 and 310 being higher than that of either of the metals 308 and 310. The slanted or inclined surface that was produced in the first dielectric layer 312 by the initial CMP, is eliminated by the end of this step.

Referring to FIG. 3C, a second dielectric layer 314, which is substantially an optically transparent material formed by CVD or Spin-On method, is deposited as a passivation layer. Various thicknesses may be used. Throughout the substrate, the thickness of the dielectric material over the metal areas is substantially the same and the total thickness of the dielectric material in areas between the metal areas i.e., over the optical sensors, is substantially the same. The second dielectric layer 314 may be one or more films and may include a total thickness ranging from 1000 Å to 10000 Å and may be 4000 A in one embodiment. A layer 316 of color filters, microlenses or associated features are then formed over the optical sensors formed in the substrate to form CMOS image sensors and CCD devices. With improved planarization and uniformity of the dielectric layers, any visual discoloration is improved or eliminated, thereby allowing sensors and other devices to function properly.

FIGS. 4A through 4C illustrate a flow for treating dielectric layers in accordance with a third embodiment of the present invention. The flow provides yet another method for uniform planarization of the dielectric surface in the illustrated embodiment.

Referring to FIG. 4A, metals 408 and 410 are implemented to block electromagnetic radiation, especially light, in the optical wavelength range. The metals 408 and 410, are metal features and collectively form a metal pattern, and they may be lines, islands, or pads that are made of metal such as copper, aluminum, various metal compounds, or metal alloys. The metals 408 and 410 may be formed from the same metal film or from different metal films. Metals 408 and 410 may include different dimensions, and depending on the underlying topography and whether metals 408 and 410 are formed from the same or a different film, the heights of metals 410 and 408 may differ to a degree. A first dielectric 412, like first dielectric layer 214 in FIG. 2A, is deposited after the metals 408 and 410 are formed. Referring to FIG. 4B, a CMP operation that polishes the dielectric layer 412 at a rate faster than it polishes metals, is then performed on the first dielectric layer 412 and recesses the first dielectric 412 below the metals 408 and 410. As a result, the upper surface of the remaining first dielectric layer 412 is substantially lower than the upper surfaces of the metals 408 and 410. The slant surface of the first dielectric layer 412 is improved or eliminated by the end of this step. Referring to FIG. 4C, a second dielectric layer 414, which is substantially an optically transparent material made by CVD or Spin-On method, is next deposited as a passivation layer above the first dielectric layer 412 and the metals 408 and 410. Various thicknesses may be used. Throughout the substrate, the thickness of the dielectric material over the metal areas is substantially the same and the total thickness of the dielectric material in areas between the metal areas i.e., over the optical sensors, is substantially the same. A layer 416 of color filters, microlenses and associated features are then formed over the optical sensors formed in the substrate to form CMOS image sensors and CCD devices. With improved planarization and uniformity of the dielectric layers, any visual discoloration is improved or eliminated, thereby allowing sensors and other devices to function properly.

While the first, the second, and the third embodiments are illustrated with only two dielectric layers, it is understood that this invention is not limited to two layers. For example, an alternative method and embodiment is to form a third dielectric layer, a substantially optical transparent layer, by a spin-on method or a CVD method to reduce the device color filter ultra violet light (CF/UL) stack while improving optical sensitivity and reducing refraction.

It is further noted that the second dielectric layers deposited in the described embodiments all serve as a passivation layer and may include a thickness of 50 nm to 2000 nm to protect the underlying optical sensor from moisture and contamination. For example, if the second dielectric layer is a stack of silicon oxide and silicon nitride, the thickness of silicon oxide is advantageously from 200 nm to 600 nm while the thickness of silicon nitride is advantageously from 100 nm to 300 nm. If the second dielectric layer is a single silicon nitride layer, the thickness may range from 50 nm to 600 nm. If the second dielectric layer is single silicon oxide layer, the thickness is advantageously from 50 nm to 600 nm.

FIGS. 5A through 5C illustrate a flow for treating dielectric layers in accordance with the fourth embodiment of the present invention. The flow presents yet another method for uniform planarization of the dielectric surface by using an additional mask.

Referring to FIG. 5A, metals 508 and 510 are present to block electromagnetic radiation, especially light, in the optical wavelength range. The metals 508 and 510 are metal features and collectively form a metal pattern, and may be lines, islands, or pads that are made of metal such as copper, aluminum, various metal compounds, or metal alloy. The metal pattern may be formed by plasma etching in one embodiment. The metals 508 and 510 may be formed from the same metal film or from different metal films. Metals 508 and 510 may include different dimensions, and depending on the underlying topography and whether metals 508 and 510 are formed from the same or a different film, the heights of metals 510 and 508 may be different. Sensing units 502 may be formed in or on the substrate 520 in regions 522 between metals 508 and 510. A first dielectric layer 512 which may be one or more dielectric films as described previously is also deposited after the formation of the metals 508 and 510. Referring to FIG. 5B, a photomask 516 is next used along with a photolithography process and an oxide etching process to produce recess 514 over one or more metals such as metal 510 and make the first dielectric layer 512 more uniform. In one exemplary embodiment, the photomask 516 may include the reverse tone of the metal pattern and produce a photo pattern that includes void areas over the metal with photoresist in other areas. Referring to FIG. 5C, after the photomask is removed, CMP is then performed on the first dielectric layer 512 to complete the process. After CMP, the total thickness of the dielectric material over the metal areas is substantially the same and the total thickness of the dielectric material in areas between the metal areas i.e., over the optical sensors, is substantially the same. Improved planarization and uniformity of the dielectric layer is achieved and the slanted or inclined surface avoided.

The various exemplary embodiments may include the following. The metals 508 and 510 may be covered by 8K to 14K of one or more an oxide films deposited over the metals 508 and 510 as the first dielectric layer 512. In one exemplary embodiment, around 8K of the oxide film from the first dielectric layer 512 is removed from over the top of the metal 510 to even the heights of the first dielectric layer 512 above the metals 508 and 510. This leaves around 6K of oxide film above the metal 510 as shown in FIG. 5B. CMP is then performed on the entire first dielectric layer 512 for a thickness of 2K as shown in FIG. 5C. Improved planarization of dielectric is achieved, since the produced surface will not be slanted or declined.

This invention provides various methods for eliminating thickness non-uniformity in the dielectric layers. By etching back the first dielectric layer or treating it with CMP until the uneven or slanted of the first dielectric layer is eliminated, the second dielectric layer may be deposited on the first dielectric layer and the metals to achieve improved planarization of surface. With such methods, the produced dielectric surface will be uniform and not slanted or inclined, thereby allowing the devices or sensors to function properly and without visual discoloration. The device CF/UL stack can also be reduced with these methods, thereby improving optical sensitivity as well as reducing refraction.

The above illustration provides many different embodiments or embodiments for implementing different features of the invention. Specific embodiments of components and processes are described to help clarify the invention. These are, of course, merely embodiments and are not intended to limit the invention from that described in the claims.

Although the invention is illustrated and described herein as embodied in one or more specific examples, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention, as set forth in the following claims.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US8173548 *May 28, 2010May 8, 2012Taiwan Semiconductor Manufacturing Company, Ltd.Reverse planarization method
US20110294286 *May 28, 2010Dec 1, 2011Taiwan Semiconductor Manufacturing Company, Ltd.Reverse planarization method
Classifications
U.S. Classification257/290
International ClassificationH01L31/113, H01L31/062
Cooperative ClassificationH01L27/14623, H01L27/14636, H01L27/14698, H01L27/14621, H01L21/31053, H01L27/14818, H01L21/31055, H01L27/14627
European ClassificationH01L27/146V16
Legal Events
DateCodeEventDescription
Dec 11, 2013FPAYFee payment
Year of fee payment: 4
Apr 27, 2010ASAssignment
Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.,TAIWA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HSIEH, YEOU-LANG;LIN, CHIN-MIN;WANG, JIANN-JONG;SIGNED BETWEEN 20050217 AND 20050310;US-ASSIGNMENT DATABASE UPDATED:20100427;REEL/FRAME:24297/20
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HSIEH, YEOU-LANG;LIN, CHIN-MIN;WANG, JIANN-JONG;SIGNED BETWEEN 20050217 AND 20050310;REEL/FRAME:24297/20
Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TAIW
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HSIEH, YEOU-LANG;LIN, CHIN-MIN;WANG, JIANN-JONG;SIGNING DATES FROM 20050217 TO 20050310;REEL/FRAME:024297/0020