US 20080191783 A1
A charge pump replica bias detector is disclosed which provides a charge pump with a greater working output voltage range or larger output compliance. A larger working range will provide a charge pump with more symmetric source and sink currents than prior designs with a reduction of the multiple frequency sideband levels that occur in a voltage controlled oscillator of a phase-locked loop synthesizer. Further improvements are the prevention of disturbances of the loop filter voltage level due to unwanted leakage currents in a charge pump that are dependent on the value of loop filter voltage. Finally, by providing improved output voltage compliance and limiting loop filter voltage disturbances there are improvements in the reduction in reference frequency feed-through, charge sharing and noise transient coupling and phase noise in the phase-locked loop. Possible applications include but are not limited to charge pump phase-locked loop designs for single chip CMOS multi-band and multi-standard radio frequency transceiver integrated circuits.
1. A replica bias clamp detector that maximizes a charge pump's output voltage compliance by monitoring and limiting the leakage current in a charge pump circuit comprising:
a voltage buffer follower responsive to a charge pump circuit output voltage level and providing a voltage output and current output;
a voltage comparator whose output signal limits a circuit's leakage current by responding to an input voltage sensing level;
a constant discharging current source to establish a fixed dc input voltage level for a comparator in the absence of charge pump leakage;
an inverter circuit whose output is responsive to a sensing input voltage;
a replica pull-up current source of an existing charge pump circuit responsive to a charge pump output and providing a charging leakage current path; and
a transmission switch responsive to the bi-directional flow of a current;
2. The replica bias clamp detector of
a second voltage comparator whose output signal limits a circuit's leakage current by responding to a second input voltage sensing level;
a constant charging current source to establish a second fixed dc input voltage level for a second comparator in the absence of charge pump leakage;
a second inverter circuit whose output is responsive to a second sensing input voltage;
a replica pull-down current source of an existing charge pump circuit responsive to a charge pump output and providing a discharge leakage current path; and
a second transmission switch responsive to the bi-directional flow of a current.
3. The replica bias clamp detector
a complimentary transmission gate coupled to the replica pull-up current source and a leakage detection comparator input and constant current source bias supply coupled between the transmission gate and supply.
4. The replica bias clamp detector
a second complimentary transmission gate coupled to the replica pull-down current source and a second leakage detection comparator input and second constant current source bias supply coupled between the second transmission gate and ground.
5. The comparator of
6. A second comparator of
7. A method of monitoring and limiting a charge pump's reverse leakage current that maximizes the charge pump's output voltage compliance using a replica bias clamp detector comprising:
a voltage follower buffer responsive to a charge pump circuit output voltage level and providing an output voltage and output current;
a replica pull-up current source that provides a reverse leakage current responsive to a voltage follower buffer output voltage level;
a complimentary transmission gate switch coupled to the pull-up current source and a leakage detection comparator input and a pull-down constant current source bias supply coupled between the complementary transmission gate and ground;
a constant discharging current source to establish a fixed dc input voltage sensing level at the input of a comparator in the absence of charge pump leakage; and
a voltage comparator responsive to an input voltage sensing level that controls transmission switch closure in a given charge pump to limit leakage current.
8. The method of
a replica pull-down current source that provides a reverse leakage current responsive to a voltage follower buffer output voltage and current levels;
a second complimentary transmission gate switch coupled to the pull-down current source and a second leakage detection comparator input and a pull-up constant current source bias supply coupled between the complementary transmission gate and ground;
a constant charging current source to establish a fixed dc input voltage sensing level at the input of a second comparator in the absence of charge pump leakage coupled between the supply; and
a second voltage comparator responsive to an input voltage sensing level that controls a second transmission switch closure in a given charge pump to limit leakage current.
9. The method of
an accurate measure of reverse leakage current in an existing charge pump circuit.
10. The method of
an accurate measure of reverse leakage current in existing charge pump circuit to a transmission switch coupled to the pull-up current source and a second leakage detection comparator input and a pull-down constant current source bias supply coupled between the complementary transmission gate and ground.
11. The method of
an accurate measure of reverse leakage current in an existing charge pump circuit.
12. The method of
an accurate measure of reverse leakage current in existing charge pump circuit to a second transmission switch coupled to the pull-down current source and a second leakage detection comparator input and a pull-up constant current source bias supply coupled between the complementary transmission gate and ground.
THIS APPLICATION IS BASED ON THE PROVISIONAL APPLICATION No. 60/487,614 FILED ON Jul. 17, 2003 and application Ser. No. 10/809,033 FILED ON Jul. 13, 2004
1. Technical Field of Invention
The present invention relates to a replica bias detector and circuit design used in a high efficiency symmetric CMOS charge pump architecture that can be used in phase-locked loop (PLL) frequency synthesizers. The PLL application examples include but are not limited to radio frequency receivers and transmitters for all wireless communication standards including cellular 2.5G/3G/4G wireless communications, optical fiber communications, network communications and storage systems.
2. Background of the Invention and Discussion of Prior Art
The growing demand for wireless communications has motivated attempts to design radios that permit the integration of more components onto a single chip. The recent advances in CMOS semiconductor processing allow the integration of the radio receiver and transmitter into a single chip radio frequency (RF) transceiver to reduce cost, size and power consumption.
Phase-locked loop (PLL) frequency synthesizer, one of the most important and challenging building blocks of the RF transceiver, is most suitable for low cost CMOS integration of wireless communication integrated circuits. PLL's are used but not limited in wireless receivers and transmitters in part for frequency synthesis where a synthesized local oscillator (LO) frequency is needed to mix down the Receive Signal Carrier such that the modulated signal is down-converted and the resulting base-band signal can be processed. Since the receive signal can operate in different bands or at discrete frequencies as part of the data transmission standard, an agile PLL frequency synthesizer is needed in order to track the receiver frequency by adjusting the LO frequency. A charge pump PLL is comprised of a reference oscillator (usually crystal based), a phase-frequency detector (PFD), charge pump (either voltage or current mode), a loop filter, a voltage-controlled oscillator (VCO), and a programmable feedback frequency divider. Each of the PLL building elements represents architecture and circuit design challenges. The generation of sideband levels in a PLL is a major concern that usually drives a charge pump's design and loop filtering requirements. In the most stringent GSM receiver area, the channel spacing (200 kHz) is considerably narrower than other wireless communication standards. When using an integer M/N PLL in a frequency synthesizer, the input reference frequency must be of the same order of magnitude relative to the channel spacing frequency specification. The PLL is able to synthesize frequencies with frequency steps equal to an integer multiple of the input reference frequencies. The maximum loop filter bandwidth is limited by the update rate of the PFD, which is the sample rate of the loop. As a rule of thumb, loop filter bandwidth should be much less than one tenth ( 1/10) of the PFD update rate to avoid instability of the PLL. If the sample rate of the input reference frequency and the PLL loop bandwidth becomes relatively close, then discrete time techniques may be needed or added to stabilize and predict PLL transient and steady state performance to avoid signal degradation. With the stringent loop filter bandwidth and reference frequency feed through filtering requirements, the charge pump PLL is a most suitable solution with the charge pump itself drawing considerable interest and study. The charge pump design works in conjunction with the PFD to improve the PLL performance.
Charge pumps as well as PLL frequency synthesizers are used in many computer, consumer and communication applications. Charge pumps can operate in either current or voltage mode and are implemented in different ways with fully differential or single-ended signal designs. Within these two classifications, there are multiple design options with their own inherent benefits and flaws.
The simplest charge pump design is the single-ended signal design where the charge pump is controlled by full swing digital signals to open a current source switch for a sourcing or sinking operation. In addition, the digital signal control will be used to quickly turn off the current source switch in the high impedance or tri-state mode. Rapid turn-on and turn-off times as well as the relative ease of matching the timing of the source and sink controlling signals are the benefits of this approach. However, relatively large transients can be induced across parasitic junction capacitance's that inject unwanted spurious noise. Furthermore, full swing designs always suffer from transient currents being induced through the power supply and ground return paths as well as introducing low efficiency in the charge pump because of asymmetrical current sourcing and current sinking behavior.
Differential signal charge pump designs using constant current mode operation have also been proposed for the charge pump to overcome the shortcomings of the single-ended design. The differential signal design approach has the benefits of high common-mode rejection to power supply noise and providing symmetrical pump currents. The differential approach while looking favorable in many areas has its own limitations such as constant power loss and charge injection from the charge pump into the loop filter load. In certain charge pump architectures, relatively small sized differential devices are used to steer the currents in order to reduce parasitic capacitance, charge injection and charge sharing effects. However, undesirably larger driving signals are still needed to completely steer current across the small sized differential pair devices. In this situation, larger driving signals again lead to the above mentioned effects of transients induced across parasitic junction capacitance's that inject unwanted spurious noise contributing to increased reference frequency feed-through in the PLL.
Due to the fact that the VCO is typically controlled by a node voltage, any reference frequency feed-through effects from the phase detector/charge pump design can modulate this voltage thereby creating modulation sidebands at the VCO RF frequency. Shown below is a mathematical description of this modulation process where modulation tones are shown to be linear in power level for small modulation indexes.
g(t)—modulation function (sinusoid)
The final expression shows that a carrier modulated by a single sinusoid produces sets of sidebands offset from the carrier by every possible multiple of the modulating frequency. The Bessel coefficients (Jn) are a function of the modulation index. If mp is small, the higher frequency sideband terms are not significant. Thus, for small modulation index only the first-order sidebands are significant. The resulting frequency spectrum will resemble a carrier undergoing amplitude modulation.
New charge pump designs  are being proposed to improve the PLL performance by adding cascoded devices for faster turn-on and turn-off and for reducing charge sharing problems of operating the high and low side switch together. However, this type of design suffers from larger internal dynamic voltage swings that increase the reference frequency feed through from the switching elements to the filter load.
Accordingly, it is a primary object of the present invention to provide a new charge pump design for high performance CMOS Frequency Synthesizers. The application is intended for the very stringent design specifications of high integration RF receivers and/or transmitters requiring low cost, small size and low power. In a common architecture where a charge pump drives a passive filter load, the resulting voltage used to control a voltage-controlled oscillator (VCO) translates directly to the AC performance of the VCO and the overall PLL control loop system. Static phase detector offset, reference frequency feed-through, and high sideband levels are direct results of non-idealities in the charge pump design. Asymmetry in the charge pump drive such as non-ideal current transitions driving a passive loop filter contribute to transient spurs on the VCO control voltage node resulting in unwanted frequency side band spectra. These errors and effects due to the charge pump current switching inefficiencies' are greatly magnified in a frequency synthesizer architecture that uses a Sigma-Delta modulator (SDM). Reference spurs and other frequency spectra must be controlled in SDM designs for PLL implementations. Accurate charge pumps are required for GSM receiver synthesizers to meet the most rigid phase noise and frequency sideband specifications in wireless communications.
The following lists the advantages of the invention compared to prior art charge pumps.
The present invention achieves the above objects and advantages by providing a new method for implementing a charge pump with double cascoded drivers, a reference signal generator and a replica bias clamp detection circuit. The following lists the new design features of the charge pump for this invention.
When higher circuit output voltages are needed, the optimum bias voltage for complete output current turn-off diverges from a common reference bias voltage, Vbias, as shown in