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Publication numberUS20080192877 A1
Publication typeApplication
Application numberUS 12/029,456
Publication dateAug 14, 2008
Filing dateFeb 11, 2008
Priority dateFeb 12, 2007
Also published asUS7983375, US20080192876, US20120244824
Publication number029456, 12029456, US 2008/0192877 A1, US 2008/192877 A1, US 20080192877 A1, US 20080192877A1, US 2008192877 A1, US 2008192877A1, US-A1-20080192877, US-A1-2008192877, US2008/0192877A1, US2008/192877A1, US20080192877 A1, US20080192877A1, US2008192877 A1, US2008192877A1
InventorsOren E. Eliezer, Manouchehr Entezari, Robert B. Staszewski, Sumeer Bhatara
Original AssigneeTexas Instruments Incorporated
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Phase alignment mechanism for minimizing the impact of integer-channel interference in a phase locked loop
US 20080192877 A1
Abstract
A novel and useful apparatus for and method of minimizing the impact of interference on the phase error performance in a phase locked loop (PLL) at integer channels by adjustment of the phase of the interfering signal such that its impact on the reference signal is minimized. Phase control is achieved by use of the digital architecture of the ADPLL and its insensitivity to an arbitrary phase bias introduced between its digitally represented output and reference phase signals. The optimal phase relationship for each integer channel is determined through a calibration procedure in which the phase is swept and the optimal phase is recorded. Before the transmission of a payload on an integer channel, the phase relationship between the output RF signal and the input reference signal is adjusted to the value found to be optimal for that frequency, based on the values previously recorded during the calibration procedure.
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Claims(25)
1. A method of minimizing the impact of interference to a frequency reference from a radio frequency (RF) signal, said method comprising steps of:
determining a desired phase relationship between said frequency reference input and said RF signal; and
adjusting the phase of said RF signal in accordance with said desired phase relationship.
2. The method according to claim 1, wherein said step of adjusting substantially satisfies said desired phase relationship.
3. The method according to claim 1, wherein said interference impact comprises excessive jitter induced onto said input reference signal resulting in corresponding distortion suffered at the output of the frequency synthesizer.
4. The method according to claim 1, wherein said RF signal comprises a carrier signal of a wireless transmitter employing digital modulation.
5. The method according to claim 4, wherein said RF signal comprises a harmonic of said carrier signal.
6. The method according to claim 1, wherein said step of determining comprises:
sweeping the phase relationship between said RF and frequency reference clock signals with a phase step;
assessing PLL performance by evaluation of said phase error samples; and
determining an optimum phase relationship and storing its location in a calibration table as a desired phase.
7. The method according to claim 1, further comprising the step of measuring the phase relationship between said frequency reference input and said RF signal, wherein said phase is adjusted in accordance with said phase relationship measurements and said predetermined desired phase relationship.
8. The method according to claim 1, wherein said step of adjusting comprises the step of temporarily changing the frequency of said RF signal for a predetermined time interval thereby achieving a phase step to substantially cover the phase distance between a measured phase relationship and said desired phase relationship.
9. A phase locked loop (PLL), comprising:
a frequency reference input for receiving a reference clock;
a controllable oscillator for generating a radio frequency (RF) clock;
a phase detector operational on said reference clock, said phase detector generating phase error samples in accordance therewith; and
a phase adjustor coupled to said controllable oscillator and said phase detector, said phase adjustor operative to receive said phase error samples and adjust the phase of said RF clock such that the impact of interference of said RF clock onto said reference clock is minimized.
10. The PLL according to claim 9, wherein said phase adjustor is operative to adjust the phase of said RF clock by temporarily changing the frequency of said controllable oscillator for a predetermined time interval.
11. The PLL according to claim 9, further comprising a slicer operative to receive said reference clock and generate a digitized version thereof.
12. The PLL according to claim 9, wherein said controllable oscillator is operative to generate said RF clock having a frequency in accordance with the frequency of said reference clock and the value of a frequency command word (FCW) input.
13. The PLL according to claim 12, wherein said phase adjustor is operative to adjust the phase of said RF clock by temporarily changing the value of said FCW for a predetermined time interval.
14. The PLL according to claim 9, wherein the spectral content of induced jitter associated with said phase adjustment is shifted substantially outside a particular frequency band of interest, thereby minimizing its impact on a PLL output signal.
15. The PLL according to claim 9, wherein said phase adjustor comprises:
means for sweeping the phase relationship between said RF and frequency reference clock signals with a phase step;
means for assessing PLL performance by evaluation of said phase error samples; and
means for determining an optimum phase relationship and storing its location in a calibration table as a desired phase.
16. The PLL according to claim 9, further comprising means for frequency modulation, wherein said RF clock interference causes modulation distortion.
17. The PLL according to claim 9, wherein said phase adjustor is operative to adjust the phase of said RF clock in accordance with said phase error samples.
18. The PLL according to claim 9, further coupled to a receiver, said receiver operative to downconvert said RF signal, and wherein said phase adjustor is operative to adjust the
phase of said RF clock in accordance with measurements based on said down-converted RF signal.
19. A single chip radio, comprising:
a phase locked loop (PLL) comprising:
a frequency reference input for receiving a reference clock;
a controllable oscillator for generating a radio frequency (RF) clock;
a phase detector operational on said reference clock, said phase detector generating phase error samples in accordance therewith;
a phase adjustor coupled to said controllable oscillator and said phase detector, said phase adjustor operative to receive said phase error samples and adjust the phase of said RF clock such that the impact of interference of said RF clock onto said reference clock is minimized;
a transmitter coupled to said phase locked loop;
a receiver coupled to said phase locked loop; and
a baseband processor coupled to said transmitter and said receiver.
20. The radio according to claim 19, wherein said phase adjustor is operative to adjust the phase of said RF clock by temporarily changing the frequency of said controllable oscillator for a predetermined time interval.
21. The PLL according to claim 19, wherein said controllable oscillator is operative to generate said RF clock having a frequency in accordance with the frequency of said reference clock and the value of a frequency command word (FCW) input.
22. The PLL according to claim 21, wherein said phase adjustor is operative to adjust the phase of said RF clock by temporarily changing the value of said FCW for a predetermined time interval.
23. The PLL according to claim 19, wherein the spectral content of induced jitter associated with said phase adjustment is shifted substantially outside a particular frequency band of interest, thereby minimizing its impact on a PLL output signal.
24. The PLL according to claim 23, wherein said frequency band of interest is substantially equal to the bandwidth of said PLL.
25. The PLL according to claim 19, wherein said receiver is operative to downconvert said RF signal, and wherein said phase adjustor is operative to adjust the phase of said RF clock in accordance with measurements based on said down-converted RF signal.
Description
REFERENCE TO PRIORITY APPLICATION

This application claims priority to U.S. Provisional Application Ser. No. 60/889,334, filed Feb. 12, 2007, entitled “Dithering of Frequency Reference Through Bond Wires”, incorporated herein by reference in its entirety.

FIELD OF THE INVENTION

The present invention relates to the field of data communications and more particularly relates to an apparatus for and method of phase alignment for minimizing the impact of integer-channel interference in a phase locked loop (PLL).

BACKGROUND OF THE INVENTION

A current trend in modern radio design is the attempt to continually increase the level of integration. The integration of wireless transceivers within digital Systems on Chips (SoCs), driven by cost reduction demands and the advances in technology, creates various challenges related with the coexistence of the various functions within the SoC. The many analog and digital functions, which operate in proximity and share the same die, potentially interfere with each other to the extent that their performance may be intolerably impaired. Various types and mechanisms for interference may exist resulting in different consequences in terms of the functionality or performance of an interfered circuit. The ability to address these interference mechanisms and mitigate their effects is a key factor in meeting the performance and cost targets of present and future integrated radio solutions.

With the increase in the number of functions in a mobile handset that are integrated into single die System-on-Chip (SoC) solutions, several interference mechanisms are created. It is often impossible (due to lack of prior knowledge, lack of full simulation capabilities or not being able to solve all the system constraints) to prevent certain aggressors from generating excessive levels of interference or to protect sensitive victims from such interference, thus creating a need for new techniques to effectively mitigate the impact of interference and ensure compliance of the transceiver with target radio specifications.

It should be noted that the drive for cost reduction in the wireless commercial market creates coexistence challenges not only as a direct result of the higher scale of integration, often requiring more than one radio to be incorporated into a single SoC, but also as a result of the demand to minimize external component count. In particular, decoupling capacitors, liberal use of copper layers in a PCB, and SAW filters that were commonly used are gradually being eliminated in current designs. This increases the potential for various mechanisms of interference, resulting in phenomena such as spurious emissions and incompliant levels of noise at outputs of transmitters. Addressing these design challenges requires understanding and optimization in both system and circuitry design considerations and constraints, and often poses a multi-dimensional optimization problem, where design complexity and area may be traded off with current consumption and/or other design aspects of interest.

Potential victim circuits may be classified into numerous categories. Five common examples in wireless SoCs include (1) sensitive RF/analog circuits (typically designed to process low-level signals) which may suffer desensitization by the interferer (e.g., the front end of a receiver); (2) RF oscillators whose performance may be impaired in the presence of an aggressing signal causing parasitic AM, PM or FM and/or frequency pulling/pushing; (3) RF/analog amplifiers, where parasitic AM may be induced (e.g., as a result of a noisy supply); (4) frequency converters and mixing circuits of nonlinear nature, which would frequency-convert aggressing signals (from the supply or signal terminals) to frequencies where they could cause incompliance with limits set forth in performance and/or regulatory specifications; and (5) digital circuits sensitive to jitter (e.g., reference clock circuits for RF synthesizers), which could suffer from additive interference on signal or supply lines (the additive noise translates into jitter as the signal passes through slicing to become a clock signal).

Potential aggressor circuits may be classified into two categories: (1) RF/analog circuits that produce strong signals that might be aggressors of specific victim circuits; and (2) digital circuits whose activity (i.e. data, clock and power supply signals) may create aggressing signals. Proper system design would include careful analysis of both types to determine the possibility of an interference mechanism stemming from either one or both of the two above.

The interference medium (i.e. coupling paths) is the physical channel through which an aggressing signal reaches a victim circuit. Such a channel may be a shared component or routing, and may also be a parasitic coupling mechanism that was not an intentional part of the circuitry. Examples of common coupling paths that could carry interference from the aggressor to the victim circuit include: (1) silicon substrate based coupling paths; (2) mutual inductance coupling paths between adjacent routs, inductors, bond wires, etc.; (3) electromagnetic paths (e.g., antenna to antenna between Bluetooth and cellular); (4) shared supply lines (e.g., static and dynamic I•R drop); (5) capacitive coupling within the SoC; and (6) external coupling paths that are related with the SoC pinout and package (e.g., PCB paths).

Ideally, the design approach minimizes the creation of an interference medium that could allow a potential aggressor to interfere with a potential victim. Once potential victim circuits and corresponding aggressing signals are identified, the possibility of the latter reaching the former is minimized. It is, however, often difficult to quantify the extent at which a particular medium would carry an aggressing signal into a victim circuit, as these are typically of parasitic nature and hence require additional modeling effort. In addition, the system tradeoffs could be so constrained that it is often not possible to minimize the coupling without a significant cost increase.

For example, one problem associated with the increase in integration of multiple transceivers in a single die is the increase in the size of the die area containing multiple potential aggressors and victims, a potential problem that is exacerbated as more and more functions are integrated into single chip radio designs. An example is modern SoCs for cellular phones, which incorporate other radios in addition to the basic cellular radio, including Bluetooth, GPS, FM, etc. As more and more functions are added, interference between the various radios, operating at different frequencies, is becoming more and more of a problem. As physical distances decrease between radios and IC pins get closer to each other, frequency planning and interference avoidance are becoming more difficult on system on chip (SoC) designs.

For example, the physical distance between the pins for the external crystal, which provides the SoC with an accurate frequency reference, and the transmit RF output is becoming smaller and thus more susceptible to interference caused by the RF output signal being coupled into the reference frequency input. This contaminated signal then passes through a slicer, to produce a square clock signal from it, but this nonlinear circuit also creates harmonics and intermodulation. When the transmitter is operating at a frequency that is a harmonic of the crystal frequency (i.e. integer-N ratio of output RF signal to reference signal), subharmonic mixing of the reference frequency signal and RF output signal occurs in the slicer. A portion of the mixing products are close to DC, which is likely to be within the bandwidth of the PLL, thus degrading its performance and impacting the quality of the RF output signal. The RF output signal coupled back to the input of the Digitally Controlled Xtal Oscillator (DCXO) manifests itself as jitter in the reference frequency, i.e. modulation of the timing of the zero crossings of the frequency reference signal which, for integer ratios of RF output and reference frequency, is within the loop bandwidth, resulting in degraded phase error at the transmitter's output.

The existing implementation of the Digital Radio Processor (DRP) based transceiver the present invention targets could not accommodate conventional suppression techniques, nor could frequency domain or time-domain avoidance techniques be applied, as the victim and aggressor circuits were required to operate simultaneously and continuously, with specific frequency relationships dictated by the operation of the transmitter.

A diagram illustrating a first example prior art single chip polar transmitter incorporating an all digital phase locked loop (ADPLL), as well as potential parasitic coupling paths intended to be addressed by the invention is shown in FIG. 1. The transmitter, generally referenced 10, comprises an ADPLL circuit 16, pulse shaper 12, amplitude modulation (AM) circuit 14, digital to RF amplitude converter (DRAC) 18 (also referred to as a Digitally Controlled Power Amplifier or DPA, which consists of a Pre Power Amplifier PPA and Sigma-Delta Amplitude Modulator SAM), digitally controlled crystal oscillator (DCXO) 20 and slicer 25. The ADPLL 16 comprises frequency command word (FCW) adder 11, reference phase accumulator 15, time to digital converter (TDC) 13, adder 17, loop filter 21, adder 23, DCO Gain Multiplier 9, and digitally controlled oscillator (DCO) 27.

The radio implements a direct FM or polar transmitter whereby the ADPLL generates an output frequency in accordance with a frequency command word (FCW) input. The CKV clock signal output of the ADPLL is amplitude modulated in accordance with an amplitude control word (ACW) generated by the AM circuit 14.

Depending on the particular implementation of the radio, a potential problem that may occur is excessive RMS phase error, or phase/frequency modulation distortion in general, for “integer-N channels” of transmission. The integer-N channels are those for which the ratio between the carrier frequency produced by the ADPLL is an integer multiple of the input reference frequency FREF. In a highly integrated multi-band cellular radio, with its reference clock generating Digitally-Controlled Crystal Oscillator (DCXO) also being integrated in the same die, a potentially significant performance degrading phenomenon is the coupling of the RF transmit output signal through the crystal pins of the DCXO.

Thus, the RMS phase error problem is due to the RF output or internal RF (e.g., digital RF) signal coupling back into the DCXO that provides the frequency reference signal for the local oscillator based on the ADPLL. The much higher frequency RF output signal that is generated is coupled into the much lower frequency FREF input, where a slicer exists to convert the oscillations into a two-level clock signal. The slicer performs a non-linear operation which allows the additive interference to translate into additive phase (or jitter) on the clock produced by this circuit. It is noted that this problem can arise in any type of PLL or frequency synthesizer circuit, where the output RF signal has the opportunity of coupling into the FREF circuitry, as typically is the case in a system-on-chip (SoC) environment.

The coupling mechanism is modeled in FIG. 1 as a modulus N block 26 (where N=CKV/FREF) coupled to a gain block 24. This interference signal is coupled to the FREF signal via virtual adder 22 before it enters the slicer 25. Thus, the frequency reference signal output of the slicer contains an interference signal whose frequency content depends on the frequency distance between the aggressing signal at CKV and the closest harmonic of FREF to it. Thus, the ADPLL output signal, and/or derived clock signals, and/or the RF output signal, are effectively coupled (various paths are indicated by dotted lines 28 and 29) to the frequency reference input. This coupling creates subharmonic mixing in the slicer (i.e. the buffer circuit following the DCXO core) through its nonlinear characteristics. The in-band spurs created by the interfering modulated TX signal through this mixing phenomenon pass through the ADPLL, being within the loop bandwidth, and degrade the phase error performance of the transmitter.

The RF interference at the DCXO is detrimental to the performance of the radio at integer-N channels because it gets downconverted to around zero (due to being located at around an integer multiple of the frequency reference), where it creates slow jitter on the frequency reference output of the slicer, via the AM/PM occurring in the slicer. The slow jitter passes through the low-pass frequency response of the PLL and reaches the output, thereby distorting the modulation (e.g., degrading the phase-trajectory error in GSM).

In highly integrated small silicon area radios, such as multi-band cellular radios with integrated RF and digital baseband (DBB), with very short separation between the RF and FREF bond pads, bond wires, balls and pins, this problem is practically unavoidable or is so much constrained that satisfying it would create other issues.

A block diagram illustrating an example prior art conventional single chip radio transceiver incorporating an on-chip DCXO buffer and showing a potential parasitic coupling path addressed by the present invention is shown in FIG. 2. Note that for clarity, only the transmitter and related phase locked loops portions of the radio are shown. The circuit shown illustrates the source of the interference phenomena in a generic transmitter that utilizes an offset-PLL up-conversion modulation loop, widely used in GSM transceivers.

The transmitter part of the radio, generally referenced 130, comprises a DCXO 158 coupled to a crystal 154, slicer 160, IF PLL 162, RF PLL 164, offset mixer 148, low pass filter (LPF) 152, 90 degree phase shift 166, I mixer 132, Q mixer 134, summer 136, phase/frequency detector (PFD) 138, low pass loop filter 140, voltage controlled oscillator (VCO) 142 and pre-power amplifier (PPA) 144.

Consider the I/Q based transmitter a part of an integrated multi-band cellular radio with an on-chip DCXO coupled to the external crystal 154 at pin 156. The local oscillator (LO) signal or transmit RF output signal at pin 146 is coupled through the crystal pins back to the input of the DCXO, as indicated by dotted line 150. The coupling path may be via on-chip pathways, off-chip pathways (i.e. bond wires, pins, PCB wiring, etc.) or any combination thereof.

As in the radio of FIG. 1, this coupling creates sub-harmonic mixing in the slicer (i.e. the DCXO buffer) through the nonlinear devices making up the slicer. This results in in-band frequency spurs contaminated with modulated TX RF output signal which pass though the PLL resulting in degraded TX phase error performance.

Aside from the interference problem described above, an additional problem in an ADPLL based transmitter, such as the one shown in FIG. 1, arises due to the finite resolution of the TDC (approximately 20 picoseconds, i.e. an inverter delay) which creates dead-beat effects at certain channels (i.e. integer-N and neighboring frequencies). This also potentially degrades the modulation quality of the transmitter at integer-N channels, i.e. where the value CKV/FREF is an integer.

There have been prior art attempts to solve the above described problems. One such solution is described in U.S. application Ser. No. 11/853,182, filed Sep. 11, 2007, entitled “Adaptive Spectral Noise Shaping To Improve Time To Digital Converter Quantization Resolution Using Dithering,” incorporated herein by reference in its entirety. In this solution, the circuitry of the TDC was modified to perform a reference frequency (FREF) clock delay shift through digital control of a capacitive load. A disadvantage of this approach, however, is that it created excessive transition times (e.g., more than 300 picoseconds), which created increased sensitivity to noise pickup by tying the delay generation through the degradation in the transition time. It is advantageous to have fast transition edges in order to minimize the duration in the metastable region between the legal logic levels to minimize noise pick-up. Additionally, this technique is only effective in addressing the dead-beat problem of integer channels, whereas the interference problem addressed by the present invention is not affected by it. The low-frequency jitter created by the interference, which may be regarded as a signal in the phase domain in the PLL, would be added onto the dithering signal that addresses the dead-beat problem, such that the effect of this low jitter remains unaffected.

Another prior art solution is described in U.S. application Ser. No. 11/832,292, filed Aug. 1, 2007, entitled “Minimization Of RMS Phase Error In A Phase Locked Loop By Dithering Of A Frequency Reference,” incorporated herein by reference in its entirety. In this solution, magnetic coupling through the chip bond wires is used to introduce intentional dithering to the DCXO input. This approach, however, is not well controllable in both the amplitude and frequency location. It represents a more “brute force” approach which radiates the dithering energy into other circuits which is likely to cause one or more other unintended consequences. Another derived solution in that application is through the use of more controllable direct injection of a dithering signal into the reference signal input (rather than relying on magnetic coupling of it). In both cases, the dithering is effective in addressing the interference problem addressed by the present invention. The drawbacks associated with this prior art are related with the implementation of this dithering and the possible adverse impact that it may have on other users of the clock signal that is being used for the reference in the ADPLL. For example, other processors or radios within the same platform (e.g., mobile phone) may need to operate off of the same crystal reference clock. It should be noted that the addition of a high-frequency dithering signal in this application is effective in the mitigation of the impact of the interference since it is done prior to the slicing operation. Consequently, it is not simple addition of the slow jitter induced by the RF with the high-frequency deliberate dither. Instead, it may be considered as an operation of mixing of the two within the nonlinearities of the slicer, effectively resulting in the transferring of jitter energy into higher frequencies, where it is less harmful and able to be suppressed by the phase-domain low-pass filtering action of the ADPLL.

SUMMARY OF THE INVENTION

The present invention is a novel and useful apparatus for and method of minimizing the jitter induced onto the input reference signal of a phase locked loop (PLL) by an RF interfering signal that is located around an integer multiple of that reference frequency. The impact of such interference on the output of the PLL may manifest itself in the form of excessive phase error or distortion, which a receiver based on it would often not tolerate due to degradation in reception quality that this could result in, and which a transmitter would not tolerate due to the possible violation of the transmitter's spectral mask and/or its modulation quality requirements (e.g., peak phase error and RMS phase error). The mechanism of the present invention is based on alignment (or adjustment) of the phase of the interfering RF signal (or signals) with respect to that of the reference signal, such that the interference impact is minimized.

The mechanism of the invention mitigates the impact of the aggressing signal within the victim circuitry by active means that ensure that the impact of the interference is tolerable. This is contrary to passive interference mitigation techniques wherein the impact of the interference is mitigated through the reduction in the power of the interfering aggressor, or through shielding or filtering provided on the victim side, where the interference is experienced. A common example of active interference mitigation is the active cancellation or suppression of interference in receiver front-end circuitry based on adaptation to the interference. In the mechanism of the present invention, the interference is mitigated actively by measuring the phase relationship between the aggressor and victim signals and actively and instantly shifting it to an optimal phase relationship, where the resultant performance degradation is minimal.

In particular, the mechanism addresses the phenomenon of DCXO jitter caused by a phase modulated GSM RF signal (or the second harmonic of it) transmitted on an integer channel (N×FREF), such that the impact on the victimized reference frequency signal is tolerable. The interference impact is phase-dependent because the phase adjustment controls both the power of the resultant jitter signal and its spectral content, potentially shifting it to higher frequencies, where the low-pass filtering in the phase domain within the ADPLL can offer better suppression.

Control over the phase is achieved by use of the digital architecture of the ADPLL and particularly its insensitivity to a phase bias introduced between its digitally represented output and reference phase signals.

Measurements demonstrating the technique, described in more detail infra, were provided for a 90 nm DRP based GSM SoC manufactured by Texas Instruments Incorporated, Dallas, Tex., USA. The implementation was based on existing digital hardware hooks and on an algorithm running within the processor of the DRP, thereby not necessitating any hardware modifications. The performance improvement offered by the technique, often in the range of 1° rms, was shown to be crucial for compliance with the GSM specifications for RMS phase error.

Note that the phase alignment (or avoidance) mechanism of the invention is generally applicable wherever an aggressing signal is frequency synchronous with the victim signal to which it interferes.

It is appreciated that although the presented problem and present invention solution are presented in the context of a Digital Radio Processor (DRP™) based transceiver, the same interference mechanism can be experienced and the present invention solution applicable in any SoC where the reference clock generation is integrated on-chip or may be interfered with by the RF signal operating at an integer multiple (i.e. harmonic) of it.

Further, the invention is applicable to single chip radios that integrate the RF circuitry with the digital base band (DBB) circuitry on the same die or on close proximity thereto so as to exhibit interference from the transmit RF output signal and/or clock signals derived from it coupling back into the frequency reference input. In a single chip radio, the reference frequency circuit, with its associated bond pads, bond wires, etc., may be very close to the RF output buffers and their associated circuitry, bond pads, and wires, thus allowing for such coupling. The invention, however, is also applicable in systems which are not necessarily integrated on a single die, which may still suffer such interference due to coupling through parasitic paths that may exist between the high-frequency aggressor and the victim circuitry generating the reference frequency for the PLL.

The advantage of the interference mitigation solution offered by the invention is that it does not require filtering, shielding, or any other conventional means for interference mitigation, as the method of the present invention relies primarily on software to adjust the phase of the aggressor such that its interference impact is minimized.

Note that some aspects of the invention described herein may be constructed as software objects that are executed in embedded devices as firmware, software objects that are executed as part of a software application on either an embedded or non-embedded computer system such as a digital signal processor (DSP), microcomputer, minicomputer, microprocessor, etc. running a real-time operating system such as WinCE, Symbian, OSE, Embedded LINUX, etc. or non-real time operating system such as Windows, UNIX, LINUX, etc., or as soft core realized HDL circuits embodied in an Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA), or as functionally equivalent discrete hardware components.

There is thus provided in accordance with the invention, a method of minimizing the impact of interference to a frequency reference from a radio frequency (RF) signal, the method comprising steps of determining a desired phase relationship between the frequency reference input and the RF signal and adjusting the phase of the RF signal in accordance with the desired phase relationship.

There is also provided in accordance with the invention, a phase locked loop (PLL) comprising a frequency reference input for receiving a reference clock, a controllable oscillator for generating a radio frequency (RF) clock, a phase detector operational on the reference clock, the phase detector generating phase error samples in accordance therewith and a phase adjustor coupled to the controllable oscillator and the phase detector, the phase adjustor operative to receive the phase error samples and adjust the phase of the RF clock such that the impact of interference of the RF clock onto the reference clock is minimized.

There is further provided in accordance with the invention, a single chip radio comprising a phase locked loop (PLL) comprising a frequency reference input for receiving a reference clock, a controllable oscillator for generating a radio frequency (RF) clock, a phase detector operational on the reference clock, the phase detector generating phase error samples in accordance therewith, a phase adjustor coupled to the controllable oscillator and the phase detector, the phase adjustor operative to receive the phase error samples and adjust the phase of the RF clock such that the impact of interference of the RF clock onto the reference clock is minimized, a transmitter coupled to the phase locked loop, a receiver coupled to the phase locked loop and a baseband processor coupled to the transmitter and the receiver.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is herein described, by way of example only, with reference to the accompanying drawings, wherein:

FIG. 1 is a diagram illustrating a first example prior art single chip polar transceiver radio showing a transmitter incorporating an all digital phase locked loop (ADPLL) based transmitter circuits, as well as potential parasitic coupling paths intended to be addressed by the invention;

FIG. 2 is a block diagram illustrating a second example prior art single chip radio transceiver incorporating an on-chip DCXO buffer and showing the potential parasitic coupling paths addressed by the present invention;

FIG. 3 is a block diagram illustrating an example single chip radio incorporating the phase alignment mechanism of the present invention shown as a software routine within the processor serving as the transceiver controller;

FIG. 4 is a simplified block diagram illustrating an example mobile communication device incorporating the phase alignment mechanism of the present invention within multiple radio transceivers;

FIG. 5 is a block diagram illustrating an example ADPLL incorporating the phase alignment mechanism of the present invention;

FIG. 6 is a simplified block diagram illustrating the relevant functions of the transmitter and the general interference mechanism addressed by the present invention;

FIG. 7 is a graph illustrating the rms phase error performance of a GSM transmitter across frequency and exhibiting a violation at the integer channel 1768 MHz;

FIG. 8 is an equivalent block of the general interference mechanism model;

FIG. 9 is a graph illustrating the victim DCXO oscillations, the interfering RF aggressor and the victim's sensitivity function represented as sampling impulses;

FIG. 10 is a vector diagram showing four different combinations for two interference sources, and their corresponding vector sums resulting from all four possible phases that the second aggressor may have with respect to the first;

FIG. 11 is a spectral diagram illustrating the down-sampling or aliasing to zero of high frequency interference occurring within the low frequency fREF circuitry;

FIG. 12 is a graph illustrating the typical phase trajectory waveform for GMSK modulated random data and the corresponding frequency deviation signal (its time derivative);

FIG. 13 is a graph illustrating the simulated and measured results for phase error performance vs. ftx-to-fref phase relationship in the presence of interference;

FIG. 14 is a graph illustrating the simulated spectrum of the down-converted interference b(t), corresponding to jitter, for best and worst case phase relationships;

FIG. 15 is a graph illustrating measured results for maximum and average rms PTE for the 5 high band integer channels with and without the phase alignment mechanism of the invention;

FIG. 16 is a graph illustrating the measured RMS PE versus the ftx-to-fref phase relationship in the presence of interference;

FIG. 17 is a graph illustrating the simulated phase error performance versus the phase relationship between the second harmonic interferer and the reference signal;

FIG. 18 is a flow diagram illustrating the phase error minimization method of the present invention; and

FIG. 19 is a flow diagram illustrating the phase shift calculation method of the present invention.

DETAILED DESCRIPTION OF THE INVENTION Notation Used Throughout

The following notation is used throughout this document.

Term Definition
AC Alternating Current
ACW Amplitude Control Word
ADC Analog to Digital Converter
ADPLL All Digital Phase Locked Loop
AM Amplitude Modulation
ASIC Application Specific Integrated Circuit
AVI Audio Video Interface
BIST Built-In Self Test
BMP Windows Bitmap
CMOS Complementary Metal Oxide Semiconductor
CPU Central Processing Unit
DBB Digital Baseband
DC Direct Current
DCO Digitally Controlled Oscillator
DCXO Digitally Controlled Crystal Oscillator
DPA Digitally Controlled Power Amplifier
DRAC Digital to RF Amplitude Conversion
DRP Digital RF Processor or Digital Radio Processor
DSL Digital Subscriber Line
DSP Digital Signal Processor
EDGE Enhanced Data Rates for GSM Evolution
EDR Enhanced Data Rate
EPROM Erasable Programmable Read Only Memory
FCW Frequency Command Word
FIB Focused Ion Beam
FM Frequency Modulation
FPGA Field Programmable Gate Array
GMSK Gaussian Minimum Shift Keying
GPS Global Positioning System
GSM Global System for Mobile communications
HB High Band
HDL Hardware Description Language
IEEE Institute of Electrical and Electronics Engineers
IIR Infinite Impulse Response
JPG Joint Photographic Experts Group
LAN Local Area Network
LB Low Band
LDO Low Drop Out
LO Local Oscillator
MBOA Multiband OFDM Alliance
MIM Metal Insulator Metal
MOS Metal Oxide Semiconductor
MP3 MPEG-1 Audio Layer 3
MPG Moving Picture Experts Group
OTW Oscillator Tuning Word
PA Power Amplifier
PC Personal Computer
PCB Printed Circuit Board
PDA Personal Digital Assistant
PHE Phase Error
PLL Phase Locked Loop
PM Phase Modulation
PPA Pre-Power Amplifier
RAM Random Access Memory
RAT Radio Access Technology
RF Radio Frequency
RFBIST RF Built-In Self Test
RMS Root Mean Squared
ROM Read Only Memory
SAM Sigma-Delta Amplitude Modulation
SAW Surface Acoustic Wave
SIM Subscriber Identity Module
SoC System on Chip
SRAM Static Read Only Memory
TDC Time to Digital Converter
TV Television
USB Universal Serial Bus
UWB Ultra Wideband
VCO Voltage Controlled Oscillator
WCDMA Wideband Code Division Multiple Access
WiFi Wireless Fidelity
WiMAX Worldwide Interoperability for Microwave Access
WiMedia Radio platform for UWB
WLAN Wireless Local Area Network
WMA Windows Media Audio
WMV Windows Media Video
WPAN Wireless Personal Area Network

DETAILED DESCRIPTION OF THE INVENTION

The present invention is a novel and useful apparatus for and method of minimizing the jitter induced onto the input reference signal of a phase locked loop (PLL) by an RF interfering signal that is located around an integer multiple of that reference frequency. The impact of such interference on the output of the PLL may manifest itself in the form of excessive phase error or distortion, which a receiver based on it would often not tolerate due to degradation in reception quality that this could result in, and which a transmitter would not tolerate due to the possible violation of the transmitter's spectral mask and/or its modulation quality requirements (e.g., peak phase error and RMS phase error). The mechanism of the present invention is based on alignment (or adjustment) of the phase of the interfering RF signal (or signals) with respect to that of the reference signal, such that the interference impact is minimized.

Note that the phase alignment (or avoidance) mechanism of the present invention is generally applicable wherever an aggressing signal is frequency synchronous with the victim signal to which it interferes. It is appreciated that although the presented problem and present invention solution are presented in the context of a Digital Radio Processor (DRP™) based transceiver, the same interference mechanism can be experienced and the present invention solution applicable in any SoC or system where the reference clock generation is integrated on-chip or may suffer from such interference through coupling paths that are not on-chip.

Further, the invention is particularly applicable to single chip radios that integrate the RF circuitry with the digital base band (DBB) circuitry on the same die or in close proximity thereto so as to exhibit interference from the transmit RF output signal coupling back into the frequency reference input. In a single chip radio, the reference frequency circuit area with its associated bond pads, bond wires, etc. may be very close to the VCO and RF output buffers and their associated bond pads and wires.

Although the phase alignment mechanism is applicable to numerous wireless communication standards and can be incorporated in numerous types of wireless or wired communication devices such a multimedia player, mobile station, user equipment, cellular phone, PDA, DSL modem, WPAN device, etc., it is described in the context of a digital RF processor (DRP) based GSM transmitter. It is appreciated, however, that the invention is not limited to use with any particular communication standard and may be used in optical, wired and wireless applications. Further, the invention is not limited to use with a specific modulation scheme but may be applicable to many digital modulation schemes where there is a need to mitigate the interference effects of the coupling of the transmit RF output signal back into the frequency reference input.

Note that throughout this document, the term communications device is defined as any apparatus or mechanism adapted to transmit, receive or transmit and receive data through a medium. The term communications transceiver or communications device is defined as any apparatus or mechanism adapted to transmit and receive data through a medium. The communications device or communications transceiver may be adapted to communicate over any suitable medium, including wireless or wired media. Examples of wireless media include RF, infrared, optical, microwave, UWB, Bluetooth, WiMAX, WiMedia, WiFi, or any other broadband medium, etc. Examples of wired media include twisted pair, coaxial, optical fiber, any wired interface (e.g., USB, Firewire, Ethernet, etc.). The term Ethernet network is defined as a network compatible with any of the IEEE 802.3 Ethernet standards, including but not limited to 10Base-T, 100Base-T or 1000Base-T over shielded or unshielded twisted pair wiring. The terms communications channel, link and cable are used interchangeably. The notation DRP is intended to denote either a Digital RF Processor or Digital Radio Processor. References to a Digital RF Processor infer a reference to a Digital Radio Processor and vice versa. The term frequency reference input is intended to denote a signal that provides a waveform of a reference frequency, such as the crystal based input signal of frequency synthesizer, and in the context of this invention, it is typically a clock signal having logic levels.

The term interference mechanism is a phenomenon resulting in an interference consequence, involving at least one aggressor and a victim coupled through at least one coupling path. The aggressor is the source of interference in an interference mechanism. The aggressing signal is the signal creating the interference effect, resulting in an interference consequence. Note that there may be more than one aggressing signal involved in a particular interference mechanism. The aggressing circuit is the active circuitry from which the interference originates. The coupling path or medium is the means by which the aggressing signal arrives from the aggressing circuit into the victim circuit. The victim circuit is the circuit in which the interference is suffered. The victim signal is a signal that is corrupted/interfered as a result of the aggressing signal. The victim signal may represent information in analog or digital form, or may be a power signal whose purpose is to deliver energy to the victim circuit. The victim is a general term for a circuit or a signal that is interfered by the aggressor. Coexistence performance is defined as the performance of the victim, or the system whose operation relies on it, in the presence of the active aggressor.

The term multimedia player or device is defined as any apparatus having a display screen and user input means that is capable of playing audio (e.g., MP3, WMA, etc.), video (AVI, MPG, WMV, etc.) and/or pictures (JPG, BMP, etc.). The user input means is typically formed of one or more manually operated switches, buttons, wheels or other user input means. Examples of multimedia devices include pocket sized personal digital assistants (PDAs), personal media player/recorders, cellular telephones, handheld devices, and the like.

Some portions of the detailed descriptions which follow are presented in terms of procedures, logic blocks, processing, steps, and other symbolic representations of operations on data bits within a computer memory. These descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. A procedure, logic block, process, etc., is generally conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps require physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared and otherwise manipulated in a computer system. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, bytes, words, values, elements, symbols, characters, terms, numbers, or the like.

It should be born in mind that all of the above and similar terms are to be associated with the appropriate physical quantities they represent and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present invention, discussions utilizing terms such as ‘processing,’ ‘computing,’ ‘calculating,’ ‘determining,’ ‘displaying’ or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

The invention can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment containing a combination of hardware and software elements. In one embodiment, a portion of the mechanism of the invention is implemented in software, which includes but is not limited to firmware, resident software, object code, assembly code, microcode, etc.

Furthermore, the invention can take the form of a computer program product accessible from a computer-usable or computer-readable medium providing program code for use by or in connection with a computer or any instruction execution system. For the purposes of this description, a computer-usable or computer readable medium is any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device, e.g., floppy disks, removable hard drives, computer files comprising source code or object code, flash semiconductor memory (USB flash drives, etc.), ROM, EPROM, or other semiconductor memory devices.

Single Chip Radio

A block diagram illustrating an example single chip radio incorporating the phase alignment mechanism of the present invention, shown as a software routine within the processor serving as the transceiver controller, is shown in FIG. 3. For illustration purposes only, the transmitter, as shown, is adapted for the GSM/EDGE cellular standards. It is appreciated, however, that one skilled in the communication arts can adapt the transmitter illustrated herein to other modulations and communication standards as well without departing from the spirit and scope of the present invention.

The radio circuit, generally referenced 30, comprises a single chip radio integrated circuit (IC) 31 coupled to a crystal 38, front end module (FEM) 46, antenna 44 and battery management circuit 32 connected to a battery 68. The radio chip 31 comprises a script processor 60, digital baseband (DBB) processor 61, memory 62 (e.g., static RAM), TX block 42, RX block 58, digitally controlled crystal oscillator (DCXO) 50, slicer 51, power management unit 34 and RF built-in self test (BIST) 36. The TX block comprises high speed and low speed digital logic block 40 including ΣΔ modulators 52, 53, digitally controlled oscillator (DCO) 56, TDC 59 and digitally controlled power amplifier (DPA) or pre-power amplifier (PPA) 48. The ADPLL and transmitter generate various radio frequency signals. The RX block comprises a low noise transconductance amplifier 63, current sampler 64, discrete time processing block 65, analog to digital converter (ADC) 66 and digital logic block 67 for the digital processing of the recovered signal in the receiver.

In accordance with the invention, the radio comprises a phase alignment function 33 operative to adjust and control the phase of the interference so that the impact of the interference is least harmful. It is noted that the phase alignment mechanism is applicable to numerous other types of PLL or frequency synthesizer, especially those with high integration wherein the frequency reference DCXO buffer is in close physical proximity to the RF output signal or to circuits operating at high clock rates derived from that PLL/synthesizer.

The structure presented herein has been used to develop three generations of a Digital RF Processor (DRP) for single-chip Bluetooth, GSM and GSM/EDGE radios realized in 130 nm, 90 nm and 65 nm digital CMOS process technologies, respectively. The common architecture is highlighted in FIG. 3 with features added specific to the cellular radio, such as the DCXO. The all digital phase locked loop (ADPLL) based transmitter employs a polar architecture with all digital phase/frequency and amplitude modulation paths. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques.

A key component is the digitally controlled oscillator (DCO) 56, which avoids any analog tuning controls. A digitally-controlled crystal oscillator (DCXO) generates a high-quality base-station-synchronized frequency reference such that the transmitted carrier frequencies and the received symbol rates are accurate to within 0.1 ppm. Digital logic built around the DCO realizes an all-digital PLL (ADPLL) that is used as a local oscillator for both the transmitter and the receiver. The polar transmitter architecture utilizes the wideband direct frequency modulation capability of the ADPLL and a digitally controlled power amplifier (DPA) 48 for the amplitude modulation. The DPA operates in near-class-E mode and uses an array of nMOS transistor switches to regulate the RF amplitude and acts as a digital-to-RF amplitude converter (DRAC). It is followed by a matching network and an external front-end module 46, which comprises a power amplifier (PA), a transmit/receive switch for the common antenna 44 and RX surface acoustic wave (SAW) filters. Fine amplitude resolution is achieved through high-speed ΣΔ dithering of the DPA nMOS transistors.

The receiver 58 employs a discrete-time architecture in which the RF signal is directly sampled at the Nyquist rate of the RF carrier and processed using analog and digital signal processing techniques. The transceiver is integrated with a script processor 60, dedicated digital base band processor 61 (i.e. ARM family processor or DSP) and SRAM memory 62. The script processor handles various TX and RX calibration, compensation, sequencing and lower-rate data path tasks and encapsulates the transceiver complexity in order to present a much simpler software programming model. In addition, in accordance with the invention, the script processor is also operative to execute the phase alignment mechanism as a software task.

The frequency reference (FREF) is generated on-chip by a 26 MHz (could be 38.4 MHz or other) digitally controlled crystal oscillator (DCXO) 50 coupled to slicer 51. An integrated power management (PM) system is connected to an external battery management circuit 32 that conditions and stabilizes the supply voltage. The PM comprises multiple low drop out (LDO) regulators that provide internal supply voltages and also isolate supply noise between circuits. The RF built-in self-test (RFBIST) 36 performs autonomous phase noise and modulation distortion testing, and various loopback configurations for transmitter and receiver tests. The transceiver is integrated with the digital baseband and SRAM in a complete system-on-chip (SoC) solution. Almost all the clock signals on this SoC are derived from and are synchronous to the RF oscillator clock. This helps to reduce susceptibility to the noise generated through clocking of the massive digital logic. In the context of the present invention, this also allows for the adjustment of the phase of these clock signals with respect to that of the DCXO, when the RF oscillator is tuned to an integer multiple of the DCXO clock frequency. This capability is what enables the minimization of the impact of the jitter induced by these higher frequency aggressors onto the clock signal produced by the slicer following the DCXO.

The transmitter comprises a polar architecture in which the amplitude and phase/frequency modulations are implemented in separate paths. Transmitted symbols generated in the digital baseband (DBB) processor are first pulse-shape-filtered in the Cartesian coordinate system. The filtered in-phase (I) and quadrature (Q) samples are then converted through a CORDIC algorithm into amplitude and phase samples of the polar coordinate system. The phase is then differentiated to obtain frequency deviation. The polar signals are subsequently conditioned through signal processing to sufficiently increase the sampling rate in order to reduce the quantization noise density and lessen the effects of the modulating spectrum replicas.

A more detailed description of the operation of the ADPLL can be found in U.S. Patent Publication No. 2006/0033582A1, published Feb. 16, 2006, to Staszewski et al., entitled “Gain Calibration of a Digital Controlled Oscillator,” U.S. Patent Publication No. 2006/0038710A1, published Feb. 23, 2006, to Staszewski et al., entitled “Hybrid Polar/Cartesian Digital Modulator” and U.S. Pat. No. 6,809,598, to Staszewski et al., entitled “Hybrid Of Predictive And Closed-Loop Phase-Domain Digital PLL Architecture,” all of which are incorporated herein by reference in their entirety.

Mobile Device Incorporating the Variable Delay Slicer Mechanism

A simplified block diagram illustrating an example mobile communication device incorporating the phase alignment mechanism of the present invention within multiple radio transceivers is shown in FIG. 4. Note that the mobile device may comprise any suitable wired or wireless device such as multimedia player, mobile communication device, cellular phone, smartphone, PDA, Bluetooth device, etc. For illustration purposes only, the device is shown as a mobile device, such as a cellular phone. Note that this example is not intended to limit the scope of the invention as the phase alignment mechanism of the present invention can be implemented in a wide variety of communication devices.

The mobile device, generally referenced 70, comprises a baseband processor or CPU 71 having analog and digital portions. The mobile device may comprise a plurality of RF transceivers 94 and associated antennas 98. RF transceivers for the basic cellular link and any number of other wireless standards and Radio Access Technologies (RATs) may be included. Examples include, but are not limited to, Global System for Mobile Communication (GSM)/GPRS/EDGE 3G; CDMA; WiMAX for providing WiMAX wireless connectivity when within the range of a WiMAX wireless network; Bluetooth for providing Bluetooth wireless connectivity when within the range of a Bluetooth wireless network; WLAN for providing wireless connectivity when in a hot spot or within the range of an ad hoc, infrastructure or mesh based wireless LAN network; near field communications; UWB; etc. One or more of the RF transceivers may comprise additional antennas to provide antenna diversity which yields improved radio performance. The mobile device may also comprise internal RAM and ROM memory 110, Flash memory 112 and external memory 114.

Several user-interface devices include microphone(s) 84, speaker(s) 82 and associated audio codec 80 or other multimedia codecs 75, a keypad for entering dialing digits 86 and for other controls and inputs, vibrator 88 for alerting a user, camera and related circuitry 100, a TV tuner 102 and associated antenna 104, display(s) 106 and associated display controller 108 and GPS receiver 90 and associated antenna 92. A USB or other interface connection 78 (e.g., SPI, SDIO, PCI, etc.) provides a serial link to a user's PC or other device. An FM transceiver 72 and antenna 74 provide the user the ability to listen to FM broadcasts as well as the ability to transmit audio over an unused FM station at low power, such as for playback over a car or home stereo system having an FM receiver. SIM card 116 provides the interface to a user's SIM card for storing user data such as address book entries, user identification, etc.

The RF transceivers 94 also comprise the phase alignment mechanism 125 of the present invention. Alternatively (or in addition to), the phase alignment mechanism may be implemented as a task 128 executed by the baseband processor 71. The phase alignment blocks 125, 128 are adapted to implement the phase alignment mechanism of the present invention as described in more detail infra. In operation, the phase alignment mechanism may be implemented as hardware, software or as a combination of hardware and software. Implemented as a software task, the program code operative to implement the phase alignment mechanism of the present invention is stored in one or more memories 110, 112 or 114 or local memories within the baseband.

Portable power is provided by the battery 124 coupled to power management circuitry 122. External power is provided via USB power 118 or an AC/DC adapter 121 connected to the battery management circuitry 122, which is operative to manage the charging and discharging of the battery 124.

ADPLL Based Polar Transmitter Incorporating Phase Alignment Mechanism

A block diagram illustrating an example ADPLL incorporating the phase alignment mechanism of the present invention is shown in FIG. 5. The ADPLL presented herein is provided as an example application of the phase alignment of the present invention. It is appreciated that the phase alignment mechanism may be applied to numerous other communication circuits as well without departing from the scope of the invention.

A more detailed description of the operation of the ADPLL can be found in U.S. Patent Publication No. 2006/0033582A1, published Feb. 16, 2006, to Staszewski et al., entitled “Gain Calibration of a Digital Controlled Oscillator,” U.S. Patent Publication No. 2006/0038710A1, published Feb. 23, 2006, to Staszewski et al., entitled “Hybrid Polar/Cartesian Digital Modulator” and U.S. Pat. No. 6,809,598, to Staszewski et al., entitled “Hybrid Of Predictive And Closed-Loop Phase-Domain Digital PLL Architecture,” all of which are incorporated herein by reference in their entirety.

For illustration purposes only, the transmitter, as shown, is adapted for the GSM/EDGE cellular standards. It is appreciated, however, that one skilled in the communication arts can adapt the transmitter illustrated herein to other modulations and communication standards as well without departing from the spirit and scope of the present invention.

The transmitter, generally referenced 170, is well-suited for a deep-submicron CMOS implementation, as its implementation is extensively digital. The transmitter comprises a complex pulse shaping filter 174, adder 173, amplitude modulation (AM) block 176 and ADPLL 172. The ADPLL 172 is operative to perform complex modulation in the polar domain in addition to the generation of the local oscillator (LO) signal for the receiver, as shown in FIG. 3. All clocks in the system are derived directly from this source through digital frequency division (based on flip-flops) or through clock edge division. Note that the transmitter is constructed using digital techniques that exploit the high speed and high density of the advanced CMOS, while avoiding problems related to voltage headroom. The ADPLL circuit replaces a conventional RF synthesizer architecture, based on a voltage-controlled oscillator (VCO) and a phase/frequency detector and charge-pump combination, with a digitally controlled oscillator (DCO) 194 and a time-to-digital converter (TDC) 206. All inputs and outputs are digital and some even at multi-GHz frequency.

The core of the ADPLL is a digitally controlled oscillator (DCO) 194 adapted to generate the RF oscillator clock CKV based on the Oscillator Tuning Word (OTW) at its digital input. The oscillator core (not shown) operates at least twice the 1.6-2.0 GHz high band frequency or at least four times the 0.8-1.0 GHz low band frequency in a GSM/EDGE transceiver. The output of the DCO is then divided for precise generation of RX LO quadrature signals, and for use as the transmitter's carrier frequency. The single DCO is shared between transmitter and receiver in TDD transceivers and is used for both the high frequency bands (HB) and the low frequency bands (LB) by dividing its output frequency by the appropriate factor for each. In additional to the integer control of the DCO, several additional varactors of minimal size are dedicated for ΣΔ dithering in order to improve frequency resolution. The DCO comprises a plurality of varactor banks, which may be realized as MOS capacitor (MOSCAP) devices or Metal Insulator Metal (MIM) devices that operate in the flat regions of their C-V curves to assist digital control. The output of the DCO is input to the RF high band pre-power amplifier (PPA) 180. It is also input to the RF low band pre-power amplifier 178 after divide by two via divider 196.

The expected variable frequency fV is related to the reference frequency fR by the frequency command word (FCW).

F C W [ k ] E ( f V [ k ] ) f R ( 1 )

The FCW is time variant and is allowed to change with every cycle TR=1/fR of the frequency reference clock. With WF=24 the word length of the fractional part of FCW, the ADPLL provides fine frequency command with 1.5 Hz accuracy, according to:

Δ f res = f R 2 W F ( 2 )

The number of integer bits WI=8 has been chosen to fully cover the GSM/EDGE frequency range of fV=1,600-2,000 MHz with an arbitrary reference frequency fR≧8 MHz.

The ADPLL operates in a digitally-synchronous fixed-point phase domain as follows: The variable phase accumulator 198 determines the variable phase RV[i] by counting the number of rising clock transitions of the DCO oscillator clock CKV as expressed below.

R V [ i ] = l = 0 i 1 ( 3 )

The index i indicates the DCO edge activity. The variable phase RV[i] is sampled via sampler 200 to yield sampled FREF variable phase RV[k], where k is the index of the FREF edge activity. The sampled FREF variable phase RV[k] is fixed-point concatenated with the normalized time-to-digital converter (TDC) 206 output ε[k]. The TDC measures and quantizes the time differences between the frequency reference FREF and the DCO clock edges. The sampled differentiated (via block 204) variable phase is subtracted from the frequency command word (FCW) by the digital frequency detector 184. The frequency error fE[k] samples


f E [k]=FCW−[(R V [k]−ε[k])−(R V [k−1]−ε[k−1])]  (4)

are accumulated via the frequency error accumulator 186 to create the phase error φE[k] samples

φ E [ k ] = l = 0 k f E [ k ] ( 5 )

which are then filtered by a fourth order IIR loop filter 188 and scaled by a proportional loop attenuator α. A parallel feed with coefficient ρ adds an integrated term to create type-II loop characteristics which suppresses the DCO flicker noise.

It should be noted that since the phase error measured and quantized by the TDC undergoes a time-derivative operation in block 204, the closed loop operation may be considered to be based on frequency error detection, performed in adder 184, rather than phase detection, which is more commonly used in PLLs. Hence, although the ADPLL operates in the phase domain in its processing of the error signal after it is integrated in the accumulator 186, the loop is insensitive to an arbitrary phase difference that may exist between the output RF signal and the input signal to the ADPLL. Consequently, when the ADPLL is locked on an integer channel, and a constant phase may be observed between the output RF signal and input FREF clock, this phase may take any value in the range −180 to +180 degrees. This property is important as it allows its interference mitigation mechanism of the present invention to force a desired phase-shift in the loop without affecting its operation, while ensuring the minimization of the impact of the jitter that the RF signal induces onto the FREF signal as it interferes with it.

The IIR filter is a cascade of four single stage filters, each satisfying the following equation:


y[k]=(1−λ)·y[k−1]+λ·x[k]  (6)

wherein

x[k] is the current input;

y[k] is the current output;

k is the time index;

λ is the configurable coefficient;

The 4-pole IIR loop filter attenuates the reference and TDC quantization noise with an 80 dB/dec slope, primarily to meet the GSM/EDGE spectral mask requirements at 400 kHz offset. The filtered and scaled phase error samples are then multiplied by the DCO gain KDCO normalization factor fR/{circumflex over (K)}DCO via multiplier 192, where fR is the reference frequency and {circumflex over (K)}DCO is the DCO gain estimate, to make the loop characteristics and modulation independent from KDCO. The modulating data is injected into two points of the ADPLL for direct frequency modulation, via adders 182 and 190. A hitless gear-shifting mechanism for the dynamic loop bandwidth control serves to reduce the settling time. It changes the loop attenuator α several times during the frequency locking while adding the (α12−1)φ1 dc offset to the phase error, where indices 1 and 2 denote before and after the event, respectively. Note that φ12, since the phase is to be continuous.

The FREF input is re-sampled by the RF oscillator clock CKV via retimer block 208 which may comprise a flip flop or register clocked by the reference frequency FREF. The resulting retimed clock (CKR) is distributed and used throughout the system. This ensures that the massive digital logic is clocked after the quiet interval of the phase error detection by the TDC. Note that in the example embodiment described herein, the ADPLL is a discrete-time sampled system implemented with all digital components connected with all digital signals.

In accordance with the invention, the phase alignment block 171, implemented, for example, on the script processor as a software task, is operative to interface with one or more components in the ADPLL as described in more detail infra. The phase alignment block determines and introduces an adjustment or alignment to the phase of the interference, originating from the ADPLL output signal and its derivatives, in such a way that mitigates its impact on the operation of the ADPLL. In the example ADPLL circuit of FIG. 5, the phase alignment block generates adjustment signal FCW SHIFT that is combined via adder 173 with the DATA FCW output of the pulse shaping filter 174.

The Interference Mechanism and Phase Alignment Based Mitigation Technique

To aid in understanding the principles of operation of the present invention, a detailed description of the problem and its solution is presented below. In particular, a detailed analysis of the interference to the frequency reference clock and the means for its mitigation is presented.

The interference suffered by the reference clock (FREF) results in intolerable jitter thereon when the transmitter output frequency is centered at an integer multiple (or close thereof) of the FREF clock. In the worst case, a consequence of this interference is potentially failing to meet specifications for phase-error in bursts or packets transmitted at integer channels, resulting from the excessive FREF noise that is tracked by the ADPLL and exhibits itself on the modulated RF carrier. A mathematical model for the interference mechanism is presented as well as the mathematical analyses explaining the performance improvements that were observed through the phase alignment mechanism of the present invention.

The Interference Mechanism Addressed by the Present Invention

The interference mechanism analyzed herein is unique in that the frequency of the aggressing signal is significantly higher than that of the operation of the victim circuitry, contrary to most common interference scenarios, such as the desensitization of RF receivers by in-band harmonics of clock signals. The high frequency aggressing signals are shown to be at the second harmonic of the transmitted carrier frequency, which approaches a frequency of 4 GHz, allowing various inevitable coupling paths between the aggressing and victim circuitry, such as mutual inductance between bond-wires of the package, imperfect supply and ground routes, and substrate paths. The high-frequency signal causes interference to the reference clock circuitry whenever it is tuned to an integer multiple of it. In such cases, the RF interference is down-sampled to zero in the non-linear circuitry that forms the 26 MHz reference clock from the sinusoidal waveform generated by the DCXO. In the slicing operation, the downconverted modulated RF signal, acting as additive interference to the input signal of the slicer, is converted into phase-domain jitter on the output reference clock signal.

A simplified block diagram illustrating the relevant functions of the transmitter and the general interference mechanism addressed by the present invention is shown in FIG. 6. The circuit, generally referenced 290, shows two sources of aggressing signals (i.e. dotted lines 308, 309 representing RF coupling interference 1 and 2) that interfere with the reference clock. The circuit comprises DCXO 292, slicer 294, ADPLL circuit 296 including phase/frequency control block 298, DCO 300 and CKV divider 302, TX divider 304 and DPA 306.

The aggressors are derived from the frequency divider 304 from which the transmitted signal is produced (denoted ‘TX divider’), and the frequency divider 302 from which various RF-derived clock signals are produced (denoted ‘CKV divider’). The notation ‘CKV’ is for the variable-phase, i.e. phase modulated, clock signal produced by the ADPLL, which is in the range of 1.6 to 2.0 GHz. Within these high frequency functions and the circuits they drive, current consumption impulses are created, which are rich in harmonic content. As shown infra, it is the second harmonic of the CKV frequency, i.e. energy in the 3.2 to 4 GHz range, which appeared to be the dominant source of interference, apparently originating from the harmonic content of these current pulses.

A graph of the measured phase trajectory error (PTE) performance of a GSM transmitter versus the carrier frequency around one of the ‘integer N’ channels for FREF=26 MHz is shown in FIG. 7. Note the violation exhibited at fTX=68·26 MHz=1768 MHz. The performance at the integer channel is shown to be significantly worse than that of the other channels, to the extent that the 3.0-degree rms phase error limit is exceeded, requiring a solution to guarantee compliance.

Properties of the Victim Signal FREF and Related Circuitry

The reference clock FREF is a square-wave signal nominally tuned within the DCXO to 26 MHz for the example DCXO presented herein, which is a crystal resonant frequency, having rise and fall times in the order of 50 ps. Note that crystals with other resonant frequencies such as 38.4 MHz or 52 MHz may be used depending on the particular implementation. The clock signal is generated within the slicer in the DCXO block, where the sine wave output of the DCXO is converted into a square-wave clock in a hard-limiting operation. The clock signal is then passed from the VDDX supply domain to the digital circuitry in the VDD_DIG supply domain through routing that may comprise several hundred micrometers. Several possible mechanisms of interference along this signal path could potentially result in its contamination.

First, additive interference induced onto the input signal of any block processing FREF (e.g., originating from a sufficiently strong aggressor and coupled through parasitic capacitances). Such additive noise could possibly be picked up at the input to the slicer, on the several hundred micrometer line leading from the DCXO circuitry to the TDC or within the TDC circuitry itself Second, Vdd/GND interference resulting from inductive coupling through bond wires, which would modulate the supply lines and equivalently the circuit's threshold. Third, Vdd contamination and ground bounces as a result of the use of a common supply (i.e. current surges on the digital supply that are not sufficiently suppressed by decoupling capacitances).

All three of the above cases effectively constitute AM-to-PM mechanisms which convert the additive interference to jitter at the slicer's output. The block diagram of FIG. 8 is an illustration of the interference model for the FREF signal, which would be generally applicable. The model, generally referenced 220, comprises an FREF phase modulation source 222, pulse shaping block 226, multiplier 250, AM to PM block 232, ADPLL model block 248, summation blocks 238, 247 and a plurality of interference sources including TX divider/buffer 240, RX divider 242 and clock divider circuitry 244. The FREF source 222 is shown as a generator for impulses representing the ‘sampling’ instances, at which time the interference may be suffered in the form of timing jitter. It is shown as a phase-modulator, since the interfering jitter 234 at the output of the model is shown to be fed into it and determines its phase modulation characteristics. The ADPLL model 248 represents a low pass filter in the phase domain, through which a portion of the induced jitter is passed and the higher frequency content thereof is suppressed. The phase alignment mechanism of the present invention (block 246) is operative to generate an adjustment or alignment to the phase which in the model of FIG. 8, is injected into the circuit via adder 247 to compensate for the interference. Although phase adjustment of the ADPLL output 248 is illustrated in this example, an independent phase adjustment of any aggressing individual signal is also within a spirit of the invention.

AM to PM Conversion (Creation of Jitter)

The signal b(t) 230 is responsible for the parasitic phase perturbations in the FREF signal, as shown in the interference model of FIG. 8. Therefore, the low frequency content in b(t) will determine the amount of parasitic phase perturbations on the CKV signal at the output of the ADPLL, as it would survive the low-pass filtering of the ADPLL closed-loop transfer function.

The AM to PM conversion represented by 232 occurs as the additive interference b(t) creates a proportional phase-shift or zero-crossing time-shift (i.e. instantaneous jitter) within the DCXO slicer, and/or within the digital gates, around the instance the FREF signal crosses the threshold level within the victim circuitry, expressed as θ(t)=α·b(t), which is shown as the output signal of the model 234.

The various sources of RF interference 240, 242, 244 are driven by the CKV signal and therefore produce signals that are frequency-synchronized with it. The output of this model is the time domain function θ(t) representing the parasitic phase perturbations on the FREF signal, which the interference induces through the AM to PM conversion occurring within the FREF circuitry. It is these phase perturbations that cause the transmitter's output phase to deviate from the nominal modulation-phase-trajectory, thus failing the limits or targets set forth for phase distortion (depending on the particular specification).

Since the ADPLL tracks the phase of the FREF signal, a filtered and amplified form of these phase perturbations appears as additive interference in the transmitter's phase modulation, depending on the spectral properties of the signal θ(t) and the settings of the ADPLL (e.g., loop dynamics). Contrary to the loop dynamics, there is no freedom in the selection of the low-frequency amplification factor in the phase domain, as it is dictated by the ratio between the required output carrier frequency and the FREF frequency of e.g., 26, 38.4 or 52 MHz (with 26 MHz used in the example calculations infra). Amongst the channels that suffer from this phenomenon within the two high bands of a quad-band GSM transmitter, this phase amplification factor varies in the range 66 to 73, i.e. the highest integer channel has about 11% more interference gain, potentially exhibiting worse performance for the same extent of FREF jitter.

For the lowest integer channel the amplification factor is 1716 MHz/26 MHz=66 which is approximately 20 log(66) or 36.4 dB, while for the highest integer channel the amplification factor is 1898 MHz/26 MHz=73 which is approximately 37.2 dB. It is noted that there may be various additional frequency dependent factors that could result in a difference in the level of interference experienced at the channels of interest, such as the coupling factor through which the RF signal couples into the FREF circuitry.

Potential Sources of Interference (Aggressors)

The CKV clock signal, being equal in frequency to the carrier frequency in high-band, is not the only potential source of interference, since there are several derivatives of it which serve to clock high-speed circuitry, such as CKVD8 (⅛ of the frequency of CKV). It has also been observed that the choice of the Script Processor clock, derived from CKV, has an effect on the transmitter phase-error performance.

Depending on the particular integer-N channel (e.g., if the ratio is an odd or even integer), each of these derivatives of CKV could be “met” by an appropriately high harmonic of FREF that would down-convert it to zero, where it potentially creates low-frequency jitter on FREF. It is noted that in the absence of modulation (and phase noise), the CKV signal and its derivatives would, theoretically, only create a fixed phase shift in FREF, since their interference at the zero crossing instances (the sampling instances in the model of FIG. 8) would be the same at each sampling instance (equivalent to a DC shift in the FREF threshold). With modulation present, the various sources of interference, appearing at different multiples of FREF, do not represent the same interference waveform, as the different frequency deviation on each of them would create a different signal once down-converted to zero by the appropriate FREF harmonic in the sampling operation.

For example, if the CKV signal were to be modulated with all ones (i.e. a fixed carrier frequency shift of about 68 kHz), the CKVD8 clock derivative would have a frequency shift of only 68/8=8.5 kHz from the nominal value of CKVD8=FREF×N/8. Consequently, the down conversion created by the FREF×N/8 harmonic (or 9th FREF harmonic for the “super” integer channel CKV=1872 MHz) would yield a sine wave of 8.5 kHz at baseband, which would be the rate of jitter induced on the FREF signal once passed through the AM to PM conversion within the victim circuit.

Simultaneously, the FREF 72nd harmonic (for CKV=1872 MHz) would down convert the 68 kHz shift on CKV to a 68 kHz sine wave, and the 36th harmonic of FREF would down convert the 34 kHz shift on the 936 MHz CKVD2 signal to a 34 kHz sine wave frequency-modulating FREF. Note that the 936 MHz interference can originate from the low-band divider once activated, as well as from digital circuitry that may be operating at that rate (e.g., sigma-delta dithering for resolution enhancement of frequency tuning in the DCO).

The relationship between the three low-frequency products in this example would not necessarily be that of the magnitudes of the three high-frequency interferers from which they originated (i.e. CKV, CKVD2 and CKVD8), due to the nonlinear nature of the AM to PM operation, in which a stronger signal typically dominates.

A higher frequency product (i.e. 68 kHz in this example), may be the most tolerable one, as it is more effectively suppressed in the low-pass characteristics of the ADPLL relating its output phase to the FREF phase at its input.

The FREF Source

The FREF source, which is the victim of the interference in this model, is represented as a phase-modulation (PM) source 222, due to its conversion of additive interference, which may be represented as voltage/current, into phase-perturbations. A simple linear proportion factor α is assumed between the output phase and the input entity in 232 in this model, although a higher order dependency is also conceivable.

The transition intervals in the FREF signal, having short durations (e.g., 50-500 ps), may be regarded as sampling intervals, since only the interference induced during such intervals may impact the threshold crossing instance within it, thereby inducing a parasitic phase perturbation. At instances away from these transition intervals, the FREF signal would not be impacted by the interference signal, contrary to scenarios of linear addition. For this reason, in the model illustrated in FIG. 8, the waveform at the output of the 26 MHz source is a train of impulses r(t) 224, representing the sampling instances. These ideal impulses are input to a shaping filter 226, whose time-limited impulse response p(t) corresponds to the duration of the rising edge in the FREF clock. The impulse response p(t) waveform represents the AM to PM conversion gain along that rising edge, which is naturally zero before the rising edge starts and after it is over, and may be high only during a very short interval around the threshold crossing in the rising edge (i.e. the pulse duration will not necessarily be equal in duration to the rise/fall time in FREF). The shaped pulses rp(t) 228 are then fed into a multiplier 250 where they sample the interference signal v(t) 236, which may be a sum of multiple aggressors, originating from 240, 242 and 244. It should be noted that these shaped pulses do not exist as a real signal in the system, and only represent the sensitivity or gain to interference that is effectively sampled around the threshold crossing instances in the DCXO's sinusoidal signal input to the slicer, as shown by trace 254 in FIG. 9.

Since only the rising edges (or falling edges) in FREF are used to drive the ADPLL logic, the train of impulses, representing the interference opportunities, have a period of Ts= 1/26 MHz=38 ns, for FREF=26 MHz, rather than 1/52 MHz (19 ns). Therefore, only the positive or only the negative pulses in trace 254 of FIG. 9 are to be considered as the instance affecting FREF.

Frequency Domain Representation and Creation of Low Frequency Interference

The train of impulses r(t) 224 in the time domain is equivalent, according to its well-known Fourier transform, to a train of Dirac functions in the frequency domain, separated by fs=FREF=26 MHz in frequency (i.e. equal-power harmonics). The pulse shaping filter p(t) 226 may have a very narrow impulse duration (e.g., below 100 ps), which may be represented as a very wide low-pass filter in the frequency domain. A frequency-domain envelope representing this filter P(f) is to be applied, which could potentially have an effect around the frequencies of interest. For example, for a width of 250 ps, corresponding to a bandwidth in the order of 1/250 ps=4 GHz, the second harmonic of CKV≈2 GHz, could be impacted. This is of interest, since it has been shown that the second harmonic of the transmitter's carrier frequency is dominant in this interference mechanism, rather than the derivatives of CKV.

For a pulse duration well below 100 ps, we may assume Rp=R(f)·P(f)≅R(f) for f<10 GHz. The slicer for the DCXO oscillations provides ‘sampling’ of the interference at the threshold crossing points as illustrated in FIG. 9, wherein trace 252 is the victim 26 MHz DCXO oscillations, trace 250 is the RF aggressor and trace 254 is the sensitivity function (i.e. ‘sampling’ impulses). The expression in Equation 7 below provides the time-domain and frequency domain representations of the train of impulses corresponding to the sampling instances. The gain factor is not of interest, but it is important to note the rich harmonic content in R(f), which is counterintuitive given the spectrally clean FREF sinusoid.

r ( t ) = n = - δ ( t - n · T S ) Fourier R ( f ) = 2 π T S n = - δ ( f - n · f S ) ( 7 ) R p ( f ) = R ( f ) · P ( f ) = 2 π T S · P ( f ) · n = - δ ( f - n · f S ) ( 8 )

where fs=FREF=26 MHz.

The harmonic of FREF closest to the interfering signal (e.g., 2×CKV, CKV, CKVD2, CKVD8, DSP clock) serves to downconvert it to a near-zero frequency (or zero, for the integer-N channel case). This applies to the CKVD8 interference source when the integer ratio N is an integer multiple of eight, as is the case for the “super integer” channel CKV=1872 MHz, since then the CKVD8 clock frequency is at a harmonic of FREF.

The interference signal v(t) 236 in this case may be represented as follows.

v ( t ) = k = 1 L A k · Cos { 2 π m k f S t + ϕ k ( t ) } Fourier V ( f ) = k = 1 L V k ( f ) = k = 1 L A ~ k · C k ( f - m k f S ) ( 9 )

Ck(f) represents the magnitude-normalized spectrum of the modulated harmonic mk. For example, those components in the summation in Equation 9 for which mk=2×N, represent the interference sources at the carrier's second harmonic at 2×CKV (e.g., those originating from the current surges in the TX and CKV dividers).

L represents the total number of interfering components located at harmonics of FREF represented by the integers {mk} (k=1, 2 . . . L). The sums in Equation 9 accommodate the possibility mj=mk for j≠k, which would apply for independent sources of interference centered at the same FREF harmonic (e.g., from different circuits creating independent interference at a specific derivative or harmonic of CKV).

The frequency representation given in Equation 9 as a sum of spectra Vk(f) illustrates that the total interference may be represented as L byproducts of the modulated carrier which are located at various harmonics of FREF having the appropriately compressed (for mk<N) or expanded (for mk>N) frequency deviations. It is noted that an expanded or compressed form of the modulated carrier's spectrum has a completely different appearance in the frequency domain, as it is the result of the Fourier transform of a frequency-modulated signal with a different modulation factor (i.e. not a GMSK signal for mk≠N), and not as shown in FIG. 11 for simplicity sake.

As previously noted, for the values of the index k associated with the interfering components at the carrier frequency (i.e. at CKV), mk=N, where N=fcarrier/FREF. In general, however, for some 1≦k≦L, mk may be greater than N. Based on laboratory observations, the dominant interferers of interest appear to be at the second harmonic of the carrier frequency, i.e. the Mth harmonic, where M=2×N. Furthermore, as previously noted, there may be two identical values for different elements in the vector mk (i.e. mi=mj for i≠j) since two different sources of interference at a specific harmonic may exist having independent amplitudes and phases (as is the case for the interfering signals from the separate TX and RX/CKV dividers).

In the expression of Equation 9, {Ak} are the amplitudes of these modulated harmonics, and {φk(t)} are their time-variant phases. Despite the frequency synchronization between the interfering harmonics, they may arrive within the FREF circuitry at different phase shifts depending on the relative locations of the circuitry in which they are generated, and on their coupling mechanisms. Hence, the functions {φk(t)} satisfy the following relationships:

Synchronization of frequency modulation:

t ϕ n ( t ) = 2 π m n N f dev ( t ) ( 10 )

Phase independence:

ϕ n ( t ) = Φ n + 2 π m n N t 0 t f dev ( t ) t = Φ n + m n N · ϕ c ( t ) n = 1 , 2 L ( 11 )

where

  • fdev(t) is the frequency deviation experienced by the carrier as a result of the GMSK modulation of the transmitted data;
  • Φn is the initial phases for the nth phase trajectory φn(t) at an arbitrary initial instance t0, to which all the phase trajectory functions φn(t) are to be referenced;
  • φc(t) is the phase trajectory of the RF carrier whose time derivative is the carrier's instantaneous frequency deviation;

This frequency deviation signal fdev(t) follows the Gaussian filtering applied to the modulating data and reaches the nominal peak values of approximately Δfpeak=max{fdev(t)}=±68 kHz.

Since there are interference contributors within v(t) that are of frequencies other than CKV (i.e. the carrier frequency during high-band operation), the multi-frequency sum v(t) contains elements of different frequency deviation magnitudes

m n N · Δ f peak .

For the CKVD8 clock, for example, this relative magnitude is

m n N = 1 8

(e.g., for 1872 MHz, N=72, and m=9). Consequently, the product of this component resulting from its down-conversions to zero by the mth harmonic of FREF, has a different multiplying factor in its phase argument, thereby inhibiting its vector summation with the interfering components originating from the other modulated harmonics, centered at different frequencies, as explained in more detail infra.

The sampling operation, represented by multiplier 250 in the block diagram of FIG. 8, performs the following multiplication:

b ( t ) = r p ( t ) × v ( t ) Fourier ( 12 ) B ( f ) = R p ( f ) * V ( f ) = [ 2 π T S · P ( f ) · n = - δ ( f - n · f S ) ] * k = 1 L A ~ k · C k ( f - m k f s ) ( 13 )

The products of interest in the above frequency domain convolution are those resulting from the relocation of the spectra Ck(f−mk·fs) to zero, as for each mk there is a Dirac function in Rp(f) satisfying n=mk.

Specifically, for those values of the index k where mk=M, the interfering signals at the second harmonic of the carrier frequency (e.g., from the current surges feeding the TX divider and from those of the CKV circuitry driven by the RX/CKV divider) will be down converted to zero by the Mth harmonic of FREF within Rp(f). The result of interest within B(f), which is around f=0, may be represented as the sum:

B ~ ( f ) = i = 1 K A ~ i · C i ( f ) ( 14 )

where

  • K<L represents the actual number of the interfering components of interest (at the second harmonic of the carrier frequency in this case);
  • Ci(f) are the spectra for these interfering signals after their down conversion to zero;

In the time domain, the zero-centered interference product b(t) may be expressed as the sum of the time domain zero-IF down-converted signals as follows.

b ( t ) = i = 1 K A ~ i · Cos { ϕ i ( t ) + Φ i } ( 15 )

Since the φi(t) phase trajectories considered here are only those originating from the interferers at the second harmonic of the carrier frequency, for all values of the index i, φi(t) may be replaced with 2×φc(t), further simplifying the sum to the form:

b ( t ) = i = 1 M A i · Cos { 2 ϕ c ( t ) + Φ i } = A total · Cos { 0 t ω 0 ( τ ) τ + Φ 0 } ( 16 )

where

  • φc(t) represents the phase trajectory of the GSM modulated carrier;
  • M is a subset of K and represents the number of interfering sources at the second harmonic of the transmitter's carrier frequency (two in FIG. 10);
  • αi are the amplitudes of the multiple interference sources;
  • Φi are the relative phases of the multiple interference sources;
  • Since the downconversion to zero eliminates the ωc·t term from the RF signals, the expression in Equation 15 contains only the doubled phase modulation term 2·φc(t) and the phase biases Φi.

This type of trigonometric summation may be represented as a vector sum. In this case, all elements are phasors centered at f=0, having different amplitudes Ai and different phases Φi.

It is noted that:

ω o ( t ) = t 2 ϕ c ( t ) constant , mean { ω 0 ( t ) } = 0 ( 17 )

Therefore, the phasors in Equation 16 are not of constant frequency, but since they share the same time-varying phase 2φc(t), or equivalently, the same instantaneous frequency, they may be summed in vector form.

Contrarily, a down-converted product of CKVD8, having a time varying phase of ⅛φc(t), cannot be considered in this manner and added to this sum in vector form, since its instantaneous frequency deviation is divided by a factor of 8 in the divide-by-8 operation.

The sum of all K elements having identical instantaneous frequency is represented in Equation 16 as a single trigonometric function at a zero-IF frequency of instantaneous value ω0(t) having the magnitude Atotal and the phase shift Φ0.

Impact of the Phase Shift Φ0 on the Interference Effect

Interestingly, the phase shift Φ0 in the expression for the interference signal b(t) in Equation 16 is of great importance, as it determines the impact of the interfering signal.

Although it represents a fixed relative phase between the interference signal b(t) and the FREF victim, to which the interfering harmonics are frequency-synchronized, it could determine the spectral content of b(t) due to the nonlinear trigonometric function in which it appears in Equation 16. A specific known case in which it would not have an effect on the spectral content, is for ω0(t)=β, where β is a constant representing a fixed phase-slope. For this case, the expression in Equation 16 has the form of a tone centered at ω=β [rad/sec] as expressed below.


b(t)=A total·Cos {β·t+Φ 0}  (18)

For this case, the spectrum |B(f)| of the interfering signal will not be affected by the phase shift Φ0 as it is simply a Dirac function at ω=β in the frequency domain. The expression in Equation 18 would apply in the interference scenario whenever redundant data is transmitted, such as only ‘1’s or only ‘0’s, both of which result in a fixed frequency shift from the carrier. In such cases, the down converted interference results in a tone at double the 67.7 kHz frequency shift, i.e. β=2·π135.4=850.85·103 rad/sec.

The AM-to-PM conversion of this interfering tone within the FREF circuitry results in frequency modulation at the rate of 135.4 kHz, creating spurs at frequency distances that are integer multiples of this frequency around FREF. The level of these spurs, corresponding to the extent of interference, are unaffected by the phase shift Φ0 and hence such redundant modulation is not useful for the observation and investigation of the TX performance dependency upon the FREF-RF phase relationship, a dependency that is observed for random data.

It is further noted that as the FREF source undergoes the parasitic phase modulation described above, the down converting harmonic of it at 2×CKV or M×FREF may no longer be assumed to be a simple Dirac function. This is also the case for modulation with random data, for which the phase perturbations induced onto FREF would not be represented by a simple tone. This compound effect is neglected, however, in the analysis as it is weak compared to the intentional modulation present on the carrier and its harmonics. This signal-to-noise assumption becomes even more valid once the phase alignment Φ0 is properly tuned, thus minimizing the interference and maximizing the ratio between the desired and parasitic phase modulations on the carrier to achieve the optimal phase-error performance.

Vector Summation of the Interference Sources

A vector diagram showing four different combinations for two interference sources, and their corresponding vector sums resulting from all four possible phases that the second aggressor may have with respect to the first is shown in FIG. 10. This figure graphically illustrates the vector sum of the expression in Equation 15, where only two interference sources are assumed to be present, both of which share the same instantaneous frequency. The RX or CKV divider may have one of four possible orthogonal phases indicated as: vector 260 at basic phase 0 degree, vector 262 rotated −90 degrees, vector 264 rotated 180 degrees and vector 266 rotated 90 degrees, each of which may be selected to drive the TDC and the CKV based digital circuitry. Laboratory observations confirm that the magnitude of interference suffered at FREF, resulting in different levels of RMS PHE, is linked with this phase selection. This is due to two effects: (1) the vector sum with the second dominant aggressor, denoted “TX DIVIDER” in FIG. 10, varies in magnitude according to the selected phase for the RX DIVIDER vector; and (2) the phase of the vector sum may also vary with respect to the victim signal FREF, which has been shown to affect the impact of the interference.

The vector diagram in FIG. 10 illustrates how a specific phase relationship between the interferences from the RX and the TX dividers, which is dictated by the values of the phase “biases” Φi, can yield four different magnitudes for the total interference, depending on the selected phase for the RX divider. For each selected phase, the vector sum (vector 268) is not only different in magnitude but also in its phase relationship with FREF, which has been shown to affect the extent of degradation in RMS phase error (PHE) performance. The phase between the vector sum 268 and FREF, however, could be adjusted via software, allowing the minimization of the impact of this interference. This phase is denoted Φ0 in FIG. 10.

In FIG. 10, the vector sum having magnitude Atotal and phase Φ0, is shown for the case where the selected RX divider phase is 0 degrees. The lowest level of interference, and hence the preferable one, is clearly observed for the case where the −90 degree phase output of the RX divider is selected instead.

Spectral Analysis of the Parasitic Phase Perturbations θ(t)

It should be noted that due to the nonlinear nature of the trigonometric Cos function, the spectral content of b(t) may be very different from that of its phase argument function γ(t) expressed in Equation 19 below. As has been previously stressed, even the constant phase bias Φ0 within this function has an effect on the spectral content of b(t) and can shift spectral content around in the frequency axis while also affecting the total power in the signal b(t). This is in contrast to its effect within γ(t) itself, where only the DC level is affected while all other frequency content in γ(t) remains unaffected.

The phase relationships Φi of the multiple interferers (with respect to each other and FREF) determine the magnitude Atotal of the total interference b(t), as well as its phase Φ0. Both the magnitude and the phase of the interference impact transmitter performance. The amount of interference suffered is proportional to the magnitude of b(t), but is also dependent on its phase, since the spectral content is dependent on this phase, as previously explained, and when the spectrum of the interference is concentrated more within the loop bandwidth of the ADPLL, its potential impact is greater.


b(t)=Atotal·Cos {2φc(t)+Φ0 }=A total·Cos {γ(t)}  (19)

Interference Minimization (Phase Avoidance) Mechanism

In accordance with the invention, the phase dependency of the performance degradation upon the aggressing signals is exploited to minimize the interference impact through control of this phase (i.e. Φ0 in the analysis above).

Since the level of high frequency aggressing signals arriving at the victim circuitry cannot be controlled, the invention provides a means for mitigating the impact of the interference. It is noted that narrowing the bandwidth of the PLL serves to limit the amount of jitter that is amplified by the loop, appearing as close-in phase noise at the RF output. This also, however, limits the loop's ability to track-out close-in noise of the RF oscillator, resulting in degraded performance. Hence, instead of narrowing the loop bandwidth, the mechanism of the present invention mitigates the impact of the interference by minimizing the power of the downconverted interference that translates into detrimental jitter.

The slicing operation, which is responsible for the conversion of the crystal oscillator (XTAL) signal from the DCXO into a square wave reference clock for the ADPLL, may be regarded as an AM-to-PM operation, where additive interference translates into phase-distortion or jitter. The additive interference is effectively sampled by the slicing operation, since only its values around the rising edges in the fref signal impact the timing jitter experienced on these transitions, based on which the ADPLL controls its output RF signal. As is well-known from the theory of sampling, any frequency content in the sampled signal, which is placed at an integer multiple of the sampling frequency, is aliased to zero as a result of the sampling operation.

Alternatively, the sampling operation can be represented mathematically as a convolution with a train of impulses in the frequency domain, resulting in frequency translation. This is illustrated graphically in FIG. 11, where frequency domain impulses are placed at integer multiples of fref. For illustration purposes only, the fTX/fref ratio assumed in FIG. 11 was reduced to 6 from a typical value of about 70 (i.e. 1.8 GHz/26 MHz). The sampling operation is shown to alias to zero both the modulated RF signal and its second harmonic, at the 6th and 12th harmonic of fref, respectively.

It is noted that while the phase trajectory of the transmitted GMSK signal exhibits ±90° phase shifts per symbol, its second harmonic, having a doubled phase-slope, or frequency, exhibits ±180° per symbol. Both signals maintain a fixed phase relationship with the non-modulated carrier, as their phases rotate by these amounts.

Although, for simplicity sake, the spectrum of the downconverted zero-IF modulated signal in FIG. 11 appears to have the same form as that of the modulated carrier, the actual spectral content of this signal depends on the phase relationship between the non-modulated carrier and the fref harmonic that downconverts it. Since these two signals are frequency synchronous when the transmitter is tuned to an ‘integer channel’, such a phase relationship, denoted Φi in Equation 16, may be defined. Assuming that the dominant interfering signals are only at the second harmonic of the transmitter's carrier frequency, and are originating from various sources, the downconverted interference signal may be represented as the sum indicated in Equation 16.

As shown in Equation 16, the sum b(t) may also be expressed as a single frequency modulated signal with amplitude A, instantaneous angular frequency ω0(t), and phase Φ0 with respect to the fref clock. This is because all terms in the sum of b(t) share the same instantaneous frequency and thus may be added in a vector sum, as shown in Equation 17.

Although mean{ω0(t)}=0, indicating that b(t) is centered at zero, and the instantaneous angular frequency signal ω0(t) does not depend on the phase relationship between the fref clock and the RF interferers, the spectrum of b(t) would. Only for a special case where ω0(t)=constant, which would be the result for an all ones or all zeros sequence in the modulated data, b(t) would reduce to a simple tone at 135 kHz, which is the frequency deviation on the second harmonic of the GMSK modulated signal. For the general case of random data, the phase trajectory may have a waveform of the type shown in FIG. 12, for which the bias Φ0 would affect the interference power and spectrum, as the nonlinear Cosine function is applied to the sum of this bias and the phase trajectory 2·φc(t). Note that in FIG. 12, solid trace 270 represents the phase trajectory in degrees while dashed trace 272 represents the frequency deviation in kHz.

Note that the total jitter power, which translates into modulation phase error, exhibits a periodic dependency on the phase, which is similar but not identical to a sinusoidal waveform, as shown in FIG. 13. Dashed trace 273 represents the limit imposed by the wireless specification, dot-dash trace 274 represents the simulated RMS phase error and solid trace 275 represents the measured RMS phase error. The worst jitter is shown to be experienced at a phase distance of 45° from the point of minimal impact. It is noted that the phase Φ0 is 2× the phase denoted “ftx-to-fref” in FIG. 13, since it refers to the second harmonic of ftx. It can be shown that for a given phase trajectory 2·φc(t), the interference power, derived from Equation 16 by a simple squaring operation, is periodic over Φ0 with a period of 180°. This translates into a period of 90° for the ftx-to-fref phase relationship.

As can be seen in FIG. 14, in addition to the difference in total interference power, the phase shift also affects the spectrum of the resultant jitter, with the best phase, denoted ‘0 degree phase shift’ (solid trace 278), exhibiting lower spectral content at lower frequencies than dashed trace 276 representing a 45 degree phase shift, having stronger spectral content at low frequencies, where the low pass transfer function of the ADPLL cannot offer suppression.

The impact of phase shifting shown in FIG. 13 was measured using software that shifts the RF phase in steps of 3° while recording the phase trajectory error (PTE) performance. An accurate 3° phase shift was realized by applying a pulse of 833 Hz magnitude and 10 μsec duration at the frequency command input (FCW) of the ADPLL. Since the error signal of the ADPLL is calculated based on frequency comparison (i.e. time derivative of phase), which is then integrated to create a phase error, as shown in FIG. 5, the closed loop allows any phase relationship between the output and reference phases and does not attempt to cancel the deliberate phase shift that is introduced in this fashion. The desired phase shift could also be accomplished through other means such as by introducing a delay and compensating for it to prevent hits.

The measured data in FIG. 13 shows the same periodic behavior anticipated by the simulation, when the dominant source of interference was assumed to be the second harmonic of the transmitted carrier, where the frequency/phase modulation is doubled. The initial phase, denoted ‘0’, is meaningless and it is only the effect of phase changes that should be considered, as the absolute phase could not be established during the measurements.

The implementation of the phase adjustment technique of the invention includes a calibration routine that establishes the best phase setting for each of the integer channels of interest. The performance versus phase is determined based on internal analysis of the digital phase error signal of the ADPLL, while a specific data pattern was used for the modulation, similar to the use of the error signal for testing purposes, as described in U.S. Publication No. 2007/0182496, published Aug. 9, 2007, incorporated herein by reference in its entirety.

In general, the calibration routine is operative, for each of the integer channels, to sweep the phase relationship between the RF and FREF signals with a predefined phase step and to assess the performance through the evaluation of the internal PHE signal. The best result is then found and its location (i.e. phase step) is recorded in a table as the ‘desired phase’ for that integer channel, to be referenced later during a compensation mechanism.

Prior to a payload transmission on an integer channel, the carrier's initial phase is determined by reading the time to digital converter (TDC) of the ADPLL, which is then compared to the optimal phase read from the calibration table. The necessary phase correction is then computed and a corresponding frequency deviation pulse is applied to shift the phase towards the optimal phase relationship.

The results across all five integer channels of the DCS and PCS high bands, both before and after the phase adjustment technique was applied, are shown in FIG. 15, wherein trace 314 represents the average RMS phase error without the invention, trace 316 represents the average RMS phase error with the invention, trace 310 represents the maximum RMS phase error without the invention and trace 312 represents the maximum RMS phase error with the invention. The measurements of maximum RMS phase error were obtained by recording the worst RMS phase error result for a burst amongst 200 bursts. The performance improvement offered by the present invention in both the average and maximum RMS phase error is clearly evident and is also shown to be crucial, as the 3-degree limit is exceeded in its absence.

Another example of the impact of phase shifting was obtained using a software script that enables phase shifting of the CKV signal in steps of 5°. Measured transmitter RMS PE performance was recorded versus the ftx-to-fref phase relationship in the presence of interference, as shown in FIG. 16, as the phase was swept through a total of 40×5=200 degrees. It should be noted that there is no significance to the absolute value of the phase, as the actual phase relationship between the CKV and FREF is not measured. It is noted that only the relative phase shift is of interest throughout this experiment. It is further noted that a clear periodic behavior was observed, which confirms the proposed theory regarding the relationship between the interference and the CKV/FREF phase relationship.

As can be seen in FIG. 16, periodic behavior is observed for the two integer channels shown in the plot (73×26=1898 MHz (dashed trace 322) and 72×26=1872 MHz (solid trace 320)). Although the best performance that could be reached for 1898 MHz (dashed) was below 1.8 degrees RMS, for 1872 MHz (solid) the performance could not be better than 2.5 degrees. This may be due to additional interference suffered at 1872 MHz from CKVD8, which is also an integer multiple of FREF. For both integer channels in the plot, the worst performance was above 3 degrees, whereas the target specification is 3 degrees RMS. The 16-step periodicity observed corresponds to 16×5=90 degrees of phase shift for the CKV signal, or 180 degrees for the second harmonic of it.

In simulations, the slicer for generating the FREF signal was modeled using a hyperbolic tangent function to account for the finite gain of a realistic hard limiter. The simulation permitted individual adjustment of the relative interference levels from the CKV signal, its harmonics and its derivatives. The AM to PM was quantified as the phase of the frequency-synchronous additive interference was swept, and the results are given in the graph of FIG. 17, for which the level of second harmonic of CKV was made dominant. As can be seen, the RMS PE performance exhibits 90 degree periodicity, corresponding to the observation of FIG. 16.

It should be noted that signal traces 282 (short dash) and 284 (solid) correspond to the variance in the internal phase error signal of the ADPLL, denoted PHE, and therefore reflect the levels that would be measured by the calibration mechanism of the present invention as the performance for each phase step would be evaluated. Traces 280 (long dash) and 286 (dot-dash) are the corresponding peak and average phase-error signals that would actually be experienced on the RF signal at the output of the ADPLL, and are shown to closely follow traces 282 and 284, respectively. This serves to validate the capability of assessing the external performance by means of internal digital processing of the PHE signal.

Compensation Mechanism

As described supra, the reference source (FREF) for the ADPLL, which would ideally be a pure 26 MHz clock, suffers excessive jitter when the transmitter RF frequency is tuned to an integer multiple of FREF (i.e. CKV=integer×FREF) due to CKV related noise, which is coupled into the FREF circuitry, where translation of this interference into jitter occurs (AM to PM).

A compensation algorithm for minimizing the consequence of this phenomenon by reducing the magnitude of the effective interference by shifting it in phase to where its impact is minimized is presented below. Note that the algorithm was designed to consume a minimum of memory and real time resources and is implemented with these goals in mind.

It has been shown that the phase relationship between the RF and FREF signals, which the ADPLL does not force to a deterministic value, has an effect on the interference suffered by FREF, and hence on the RMS PE. The cyclic behavior of RMS PE versus the phase shift (with a cycle of 90 degrees), however, varies from one case to another (i.e. from one relocking instance to another on the same integer channel). It has been shown that when this dependency is flatter (and higher/worse in RMS PE), the RMS PE performance may be further improved by selecting the appropriate output of the RX divider (one of four possibilities) having the optimal timing relationship with respect to the output of the TX divider 304 (FIG. 6). The selected RX divider phase is used in the ADPLL feedback as well as for the CKVD clock derivation circuitry, consequently having an effect on the cumulative interference suffered in the FREF circuitry. The worst case of this cumulative interference is when the current surges or RF signals from the two separate dividers are substantially phase aligned, thereby resulting in stronger interference.

It is therefore necessary not only to tune the phase shift between the RF and FREF signals to the optimal point, but also to ensure the right relative timing between the RX and TX divider outputs, which would serve to minimize the magnitude of the vector sum.

A flow diagram illustrating the phase error minimization method of the present invention is shown in FIG. 18. The first step is to determine the timing relationship between the TX and RX divider outputs based, for example, on the observation made in the I and Q branches of the receiver (at zero IF) (step 330). Two possible values for complex bias are possible, each of which requires a different selection of RX divider output. The observed complex bias is then compared to its two possible values and the best RX divider phase defined for this RX/TX state is selected (step 332). The method then waits for the TX_start signal for TDC reading (step 334). Alternatively some other phase error signal could also be used. This is because the timing of the modulating signal, and hence the phase Φ0 of the interference b(t), is determined only after this instance. The RF/FREF phase relationship, based on TDC readings, is then determined (step 336). The phase difference between the actual phase and the desired phase is then calculated (step 338). Note that the desired phase is a predetermined value based on characterization/calibration. The required phase movement is then forced by means of a two-point modulation FCW impulse that results in arrival at the optimal RF/FREF phase shift (step 339).

The TDC based phase measurement and calculation method will now be described in more detail. The TDC's reading at a specific instance represents the relative phase between the FREF and RF signals. For a non-modulated carrier on an integer channel, this reading will remain fixed over time (or could fluctuate between values with a certain fixed average, due to DCO phase noise). The TDC's time quantization error in a single reading can be as high as 23 ps (i.e. an inverter delay), which translates to a phase error of over 15 degrees for a signal in the 1.9 GHz range. This is too coarse considering that the best and worst points, in terms of the resultant RMS PE, are only 45 degrees apart. In order to enable more accurate phase measurements, resolution enhancement is applied. The resolution enhancement is achieved by multiple readings of the TDC at specific instances (having deterministic timing with respect to the symbol clock) and averaging, in order to reduce the effect of the noisy readings and the quantization errors. Since the TX_start signal resets the counter generating the symbol clock and also triggers the phase measurement routine, the sampling instances are deterministic with respect to the symbol timing and hence also with respect to the resultant phase trajectory.

A flow diagram illustrating the phase shift calculation method of the present invention is shown in FIG. 19. In a single TDC reading, the measurement error in resolving the RF/FREF phase relationship is up to one inverter delay (˜23 ps), which for an RF frequency of 1898 MHz corresponds to:


εTDC=23 p·1898M·360=15.7 deg   (20)

This quantization error represents the distance between two consecutive boundaries defined by two adjacent inverters in the TDC. Since 1898 MHz is the highest integer channel, 15.7 deg is the worst case quantization error. In the presence of natural oscillator noise (from FREF and RF), however, there could be occasional phase perturbations that add noise to the quantization error.

In order to mitigate the effect of this and to enhance the resolution of the phase measurement, the TDC is to be read multiple times, for example every 32 FREF clock cycles (812.5 kHz), while the RF signal is modulated with all ones. The amount of phase movement within 32 FREF clock cycles:

Δϕ S = 360 · Δ f / FREF / 32 = 360 · 67.709 / 812.5 kHz = 30 deg ( 21 ) or Δϕ S = 90 / O S R 90 / 3 30 deg ( 22 )

The duration of averaging of samples includes an integer multiple of symbols, thereby ensuring that the summation of these phase measurements yields 0 in the modulo-90 arithmetic, as each symbol accounts for +90 or −90 degrees of phase modulation.

With reference to FIG. 19, the first step in the procedure for determining the phase shift with enhanced resolution and noise filtering is to enable an internal buffer to read TDC data at 812.5 kHz (i.e. decimation factor=32) (step 340). The method then waits for 15 μsec, which is sufficient for 12 samples, which spans 4 symbols or 360 degrees (step 342). The buffer is then disabled to prevent overwriting (step 344). The first two RF/FREF transition locations in each TDC sample are then defined (i.e. to define a half period of RF cycle) (step 346).

The transition locations of all samples are then summed in units of inverter delay (step 348). The sum S, which represents the averaged phase, is then stored (step 350). The total phase is then calculated as follows (step 352):

The phase within a single inverter is calculated using:


ΔΦinverter[deg]=T inv /T RF×360   (23)


ΔΦinverter[deg]=DLO PERINV×360/215   (24)

Convenient units for the calculations are defined as follows:


ΔΦinverter=213/90×ΔΦinverter =DLO PERINV   (25)

The total_phase is then given by


total_phase=S×Δφ inverter =S×DLO PERINV [normalized units]  (26)

where 1 degree=91.0222 normalized units, 90 degrees=8192 (0×2000) normalized units. Note that the target (i.e. desired) phase should be a fraction of 8192 (0×2000), due to the modulo-90 degrees.

Next, the reference (i.e. desired) phase is subtracted from the measured phase to determine necessary phase shift (step 354):


total_phase=Δφcorrection=total_phase−desired_phase(normalized)   (27)

The method then calculates modulo ±45 degrees by shifting up 19 places (i.e. clearing from the 13th bit and up) and then shifting right (signed) to yield (step 356):


temp=219×phase_shift_mod90=phase_shift (shifted left 19 places)   (28)


phase_shift_mod45=temp (shifted right 19 places—signed)   (29)

The ΔFCW pulse magnitude to be applied is then calculated (step 358). The ΔFCW pulse is applied for a duration of Tp=5 μsec.

Δ FCW = Φ correction [ deg ] / 360 / T p [ sec ] = phase_shift _mod _ 45 × 45 / 2 12 / 360 / 5 μ sec = phase_shift _mod _ 45 × 6.1 ( 30 ) Normalized Δ fcw = FCW [ Hz ] × 2 24 / 26 M = 63 / 16 × phase_shift _mod _ 45 ( 31 )

The 5 μsec FCW pulse is then applied by adding the Δfcw to the existing FCW offset (i.e. the modulation) and then reverting to the original FCW after the 5 μsec have elapsed (step 360).

It is intended that the appended claims cover all such features and advantages of the invention that fall within the spirit and scope of the present invention. As numerous modifications and changes will readily occur to those skilled in the art, it is intended that the invention not be limited to the limited number of embodiments described herein. Accordingly, it will be appreciated that all suitable variations, modifications and equivalents may be resorted to, falling within the spirit and scope of the present invention.

Referenced by
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US8081042May 19, 2009Dec 20, 2011Nokia CorporationApparatus, method and computer program
US8248106Nov 18, 2010Aug 21, 2012Applied Micro Circuits CorporationLock detection using a digital phase error message
US8476945Mar 23, 2011Jul 2, 2013International Business Machines CorporationPhase profile generator
US8749282 *Jan 2, 2013Jun 10, 2014Ganesh Ramaswamy BasawapatnaTranslational phase lock loop and synthesizer that eliminates dividers
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Classifications
U.S. Classification375/376
International ClassificationH04L7/00
Cooperative ClassificationH03L2207/50, H03L7/1806
European ClassificationH03L7/18D
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Owner name: TEXAS INSTRUMENTS INCORPORATED, TEXAS
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Effective date: 20080204