|Publication number||US20080265234 A1|
|Application number||US 11/741,781|
|Publication date||Oct 30, 2008|
|Filing date||Apr 30, 2007|
|Priority date||Apr 30, 2007|
|Also published as||US8115186, US20090294748|
|Publication number||11741781, 741781, US 2008/0265234 A1, US 2008/265234 A1, US 20080265234 A1, US 20080265234A1, US 2008265234 A1, US 2008265234A1, US-A1-20080265234, US-A1-2008265234, US2008/0265234A1, US2008/265234A1, US20080265234 A1, US20080265234A1, US2008265234 A1, US2008265234A1|
|Inventors||Matthew J. Breitwisch, Roger W. Cheek, Eric Andrew Joseph, Chung Hon Lam, Hsiang-Lan Lung, Alejandro Gabriel Schrott|
|Original Assignee||Breitwisch Matthew J, Cheek Roger W, Eric Andrew Joseph, Chung Hon Lam, Hsiang-Lan Lung, Alejandro Gabriel Schrott|
|Export Citation||BiBTeX, EndNote, RefMan|
|Referenced by (33), Classifications (15), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates generally to memory cells in integrated circuits, and, more particularly, to memory cells comprising phase change materials for use in integrated circuits.
The possibility of using phase change materials (PCMs) in nonvolatile memory cells has recently gained momentum as more is learned about these materials and their integration into integrated circuits. When incorporated in a memory cell, these materials can be toggled between higher and lower electrical resistance states by applying a pulse of electrical current (“switching current pulse”) to the memory cell. After writing to a memory cell in this way, the electrical resistance state of the given memory cell can be determined (i.e., read) by applying a low magnitude sensing voltage to the material in order to determine its electrical resistance.
Currently, binary and ternary chalcogenide alloys such as doped antimony telluride (SbTe) and germanium antimony telluride (Ge2Sb2Te5) (GST) are showing the greatest promise for use in practical PCM-based memory cells. However, the switching of a PCM-based memory cell requires that the switching current pulse produce enough heat in the PCM to cause at least some portion of the PCM to reproducibly change electrical resistance state. The required temperature may be as high 350 degrees Celsius. If the memory cell is not properly designed, the magnitude of the switching current pulse necessary to create these required temperatures can easily exceed that which can be tolerated by modern integrated circuits.
It has been recognized that the magnitude of the required switching current pulse can be reduced by forcing the current pulse to pass through an extremely narrow region of PCM. The confinement of the switching current to this narrow region results in high localized current density, and, in turn, in high localized ohmic heating. Nevertheless, it remains challenging to reliably and reproducibly form constricted regions of PCM with suitably narrow dimensions. Frequently, for example, such processing requires the formation of features that are smaller than those that can be formed using conventional photolithographic techniques. There remains, as a result, a need for methods of reliably and reproducibly forming constricted regions of PCM in PCM-based memory cells.
Embodiments of the present invention address the above-identified need by providing methods for reliably and reproducibly forming PCM-based memory cells with constricted PCM regions.
In accordance with an aspect of the invention, a memory cell is fabricated by forming a dielectric layer and patterning a hole in the dielectric layer. Patterning the hole is accomplished at least in part by contacting the dielectric layer with a catalytic material in the presence of a reactant under conditions effective to remove those areas of the dielectric layer in contact with the catalytic material. A phase change feature is then formed in contact with the dielectric layer such that a portion of the phase change feature at least partially fills the hole in the dielectric layer. At least a portion of the patterned dielectric layer remains in the ultimate memory cell.
In one of the above-identified embodiments, a memory cell comprises a dielectric layer comprising silicon dioxide. A hole is patterned in the dielectric layer by contacting the surface of the dielectric layer with a solid platinum catalytic feature in the presence of xenon difluoride (XeF2) under temperature and pressure conditions selected to cause that region of the dielectric layer in contact with the catalytic feature to be selectively removed. The remainder of the dielectric layer remains substantially intact. Once the hole is formed in the dielectric layer, PCM is deposited on the dielectric layer such that a portion of the PCM fills the hole. When a switching current pulse is applied to the memory cell, it must pass through this narrow region of PCM. As a result, high localized current densities are created in the PCM in this portion of the memory cell.
Advantageously, the magnitude of the switching current pulse required to cause the PCM occupying the hole in the dielectric layer to make an electrical resistance state transition is substantially less than that which would be required to cause a transition in the remainder of the PCM volume. This memory cell design, therefore, utilizes high localized switching current density to reduce the required magnitude of the switching current pulse.
These and other features and advantages of the present invention will become apparent from the following detailed description which is to be read in conjunction with the accompanying figures.
This invention will be illustrated herein in conjunction with exemplary memory cells for use in integrated circuits and methods for forming such memory cells. It should be understood, however, that the invention is not limited to the particular materials, features, and processing steps shown and described herein. Modifications to the illustrative embodiments will become apparent to those skilled in the art.
Particularly with respect to processing steps, it is emphasized that the descriptions provided herein are not intended to encompass all of the processing steps which may be required to successfully form a functional integrated circuit device. Rather, certain processing steps which are conventionally used in forming integrated circuit devices, such as, for example, wet cleaning and annealing steps, are purposefully not described for economy of description. However one skilled in the art will readily recognize those processing steps omitted from these generalized descriptions. Moreover, many details of the processing steps used to fabricate such integrated circuit devices may be found in a number of publications, for example, S. Wolf and R. N. Tauber, Silicon Processing for the VLSI Era, Volume 1, Lattice Press, 1986 and S. M. Sze, VLSI Technology, Second Edition, McGraw-Hill, 1988, both of which are incorporated herein by reference.
The term “phase change material” (PCM) as used herein is intended to encompass any material displaying more than one programmable electrical resistance state for use in integrated circuits. PCMs comprise, for example, various chalcogenides and transition metal oxides and include, but are not limited to, doped or undoped GeSb, SbTe, Ge2Sb2Te5 (GST), SrTiO3, BaTiO3, (Sr,Ba)TiO3, SrZrO3, Ca2Nb2O7, (Pr,Ca)MnO3, Ta2O5, NiOx and TiOx, as well as other suitable materials.
It should also be understood that the various layers and/or regions shown in the accompanying figures are not drawn to scale, and that one or more layers and/or regions of a type commonly used in integrated circuits may not be explicitly shown in a given figure. For example, those integrated circuit features associated with what is commonly referred to as the front-end-of-line and middle-of-line are not described herein. This does not imply that the layers and/or regions not explicitly shown are omitted from the actual integrated circuit.
For ease of understanding, the design and operating characteristics of a PCM-based memory cell in accordance with an illustrative embodiment of the invention will be described first. Subsequently, methods for forming the illustrative memory cell embodiment in an integrated circuit will be addressed.
The lower electrode 110 comprises tungsten or titanium nitride while the upper electrode 1 40comprises titanium nitride. Both the lower and upper dielectric layers 120, 150 comprise silicon dioxide, and the PCM feature 130 comprises GST. Nonetheless, these material choices are merely illustrative and any other suitable materials may be used in the place of the ones described herein. One or both of the lower and upper electrodes, for example, may comprise tantalum nitride instead of titanium nitride or tungsten. Additionally or alternatively, one or both of the dielectric layers may comprise silicon nitride. One skilled in the art will recognize the various advantages and disadvantages of making such substitutions.
Referring again to
Access to the memory cell 100 is preferably controlled via two metallic lines (not explicitly shown in
Writing data to the memory cell 100 comprises placing some portion of the total volume of the PCM feature 130 (the “switchable volume”) into either a lower electrical resistance polycrystalline state or a higher electrical resistance amorphous state. Transitions between these states are accomplished by heating the PCM feature through the application of a pulse of switching current between the lower electrode 110 and the upper electrode 140. Advantageously, the placement of a portion of the PCM feature in the hole 160 in the lower dielectric layer 120 acts to force the switching current to pass through a constricted volume of PCM. When, for example, a switching current pulse is applied between the lower electrode and upper electrode, the switching current pulse first passes through the lower electrode and into the portion of the PCM feature filling the hole. Subsequently, the current travels through the remainder of the PCM feature and into the upper electrode.
The forcing of the switching current through the constricted region of the PCM feature 130 in the hole 160 in the lower dielectric layer 120 results in a high localized current density in this region of the PCM, and, in turn, in high ohmic heating. For this reason, the switchable volume of the PCM can be found in this region of the PCM feature (as indicated on
The duration of the switching current pulse is preferably between about I and about 500 nanoseconds and has a fast falling edge (e.g., less than about ten nanoseconds), although the invention is not limited to any particular duration and/or rise or fall time of the switching current pulse. The fast falling edge acts to freeze the switchable volume of the PCM feature 130 in its current electrical resistance state without allowing additional time for the bonds within the material to continue to rearrange.
Reading the state of the memory cell 100 may be accomplished by applying a sensing voltage to the memory cell, again via the lower and upper electrodes 110, 140. The ratio of the electrical resistances between the higher and lower electrical resistance states in a typical two-state PCM is between about 100:1 and 1,000:1. The sensing voltage is preferably of low enough magnitude to provide negligible ohmic heating in the PCM feature 130. Accordingly, the electrical resistance state of the PCM feature may be determined in this manner without disturbing its written electrical resistance state. Data integrity is thereby maintained while reading the data.
Step 230 in
If the lower dielectric layer 120 comprises silicon dioxide, the catalytic feature 310 preferably comprises solid platinum, although other suitable materials or combinations of materials may be utilized. The reactant, on the other hand, will preferably comprise xenon difluoride (XeF2) gas or some other suitable fluorine-containing gas. Platinum catalytically etches silicon dioxide in the presence xenon difluoride. Conditions employed to effectively remove portions of the lower dielectric layer may vary over a wide range. Nevertheless, generally, temperature is from about 350° to about 450° Celsius and total pressure is from about 0.5 to 1 pounds-per-square-inch-gauge (psig). The reactant partial pressure is typically from about 0.005 to about 0.01 psig. Time for the reaction may be between about 1 and about 20 seconds depending on the thickness of the lower dielectric layer as well as the other reaction conditions.
One skilled in the art will recognize that the proper choice of the catalytic material, reactant, and processing conditions will strongly depend on the composition of the lower dielectric layer 120. For example, depending on the material to be selectively removed, several materials or combinations of materials from Groups IVB, VB, VIB, and VIII of the Periodic Table of the Elements may be useful as catalytic features, while oxygen- and chlorine-containing molecules may be useful as reactants. The reactant may even be delivered in liquid phase. Effective combinations of catalytic materials, reactants, and processing conditions for different lower dielectric layer compositions will be known to one skilled in the art. As a result, several variations may be made to the selective removal process in step 230 in
It should be noted that the hole 160 in the lower dielectric layer 120 may be of any desired shape in a plane parallel to the dielectric layer (e.g., square, rectangular, oval, or round). The hole will typically match the shape of the catalytic feature 310. As a result, modifying the shape of the catalytic feature becomes a convenient way of tuning the power requirements of the memory cell 100 since the dimensions of the hole in the dielectric layer directly affect the switching current magnitude required to cause phase transitions in the PCM feature 130. Moreover, the use of the processing sequence just described allows the hole in the lower dielectric layer to have dimensions that are substantially smaller than those which can be formed by conventional photolithograpic techniques.
After performing the patterning of the hole 160 in the lower dielectric layer 120, the resultant film stack will appear as shown in
Once the film stack appears as shown in
The PCM-based memory cell 100 described above is part of the design for an integrated circuit chip. The chip design may be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or photolithographic masks used to fabricate chips, the designer transmits the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSI) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.
The resulting integrated circuit chips may be distributed by the fabricator in raw wafer form (i.e., as a single wafer that has multiple unpackaged chips), as a bare die, or in packaged form. In the latter case, the chip is mounted in a single chip package (e.g., plastic carrier with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (e.g., ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product (e.g., motherboard) or an end product. The end product may be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
Although illustrative embodiments of the present invention have been described herein with reference to the accompanying figures, it is to be understood that the invention is not limited to those precise embodiments. For example, the materials utilized in the illustrative embodiments and the particular sequence of processing steps used to fabricate the illustrative embodiments may be changed without departing from the scope of the appended claims. These changes and various other modifications will be evident to one skilled in the art.
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|U.S. Classification||257/2, 257/E45.001, 438/104|
|Cooperative Classification||H01L45/147, H01L45/1233, H01L45/04, H01L45/06, H01L45/146, H01L45/144, H01L45/1666, H01L45/148|
|European Classification||H01L45/04, H01L45/14C, H01L27/24|
|Apr 30, 2007||AS||Assignment|
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BREITWISCH, MATTHEW J.;CHEEK, ROGER W.;JOSEPH, ERIC ANDREW;AND OTHERS;REEL/FRAME:019225/0485;SIGNING DATES FROM 20070419 TO 20070420
Owner name: MACRONIX INTERNATIONAL CO., LTD., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LUNG, HSIANG-LAN;REEL/FRAME:019225/0489
Effective date: 20070419