US 20080277153 A1
Power supplied to an information handling system electronic component through a circuit board has component package inductance parasitic effects compensated by configuring connections to the electronic component to have increased parasitic capacitance. For instance, power and ground vias that connect a processor to power and ground planes of the circuit board are aligned to create a desired parasitic capacitance that reduces the impact of parasitic inductance relating to signal compensation, power delivery and high speed decoupling. The desired distributed capacitance is modeled by altering the radius associated with the equivalent line charge of the power via, the distance associated with the line charges between power and ground vias, and the via barrel length.
9. An information handling system comprising:
a circuit board operable to support electronic components, the circuit board having a surface plane, a power plane and a ground plane;
an electronic component socket coupled to the circuit board surface plane;
plural wirelines disposed in the circuit board and interfaced with the socket, the wirelines operable to communicate signals with the socket;
an electronic component coupled to the socket and operable to process information for communication as signals through the socket and wirelines, the electronic component operating with parasitic inductance and capacitance;
one or more power vias interfacing the socket to the power plane; and
one or more ground vias interfacing the socket to the ground plane;
wherein the power vias and ground vias are configured according to one or more factors associated with increased parasitic capacitance that offsets the effects of the parasitic inductance.
10. The information handling system of
11. The information handling system of
12. The information handling system of
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1. Field of the Invention
The present invention relates in general to the field of information handling system circuit boards, and more particularly to a system and method for capacitive coupled via structures between circuit board ground, power and circuit planes.
2. Description of the Related Art
As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
Over the past several decades, information handling systems have steadily increased their capacity to process and store information in designs having compact footprints. These improvements have been largely based on the availability of processors to handle greater numbers of computations with increased speed by fabricating increased numbers of circuits within a given size of semiconductor material. The processor designs have improved by increasing the number of cycles performed in a given time frame and decreasing the operating voltages. Improved processors allow more rapid execution of application instructions for interaction with an information handling system user as well as improved communication of information through busses that interface various components of an information handling system, such as memory, network interfaces and graphic display interfaces. Information handling system designers face a substantial challenge in interfacing the various components through a circuit board. For instance, design challenges include arranging components in a compact footprint with ease of assembly and adequate cooling. One type of circuit board-to-processor interface that has become increasingly common is the ball grid array (BGA) connector and socket. BGA sockets provide high density, high input/output count packaging with reduced pin-to-pin trace gaps by distributing the ball and grid connections between the processor and the circuit board.
One difficulty often faced in the design of information handling system circuit boards is that the speed, density and power requirements of powerful processors tend to generate undesired electromagnetic effects and interference. For instance, parasitic inductance is associated with the physical structure of integrated circuits. The parasitic inductance tends to disrupt power supply to the integrated circuit, especially at current flows having lower voltages and greater transient surges to meet the demands of powerful modern processors. Small parasitic effects have more pronounced effects on power delivery to processors, especially in transient conditions, as operating voltages decrease. Discrete component solutions are typically employed to reduce the undesired impact on power supply and delivery, such as associating capacitance with a power supply circuit board wire line to smooth, current flow during transient power demands. However, the ability of discrete component, solutions to compensate for power delivery, decoupling and processor package parasitic effects has fallen behind as processor density has increased and supply voltage decreased, especially in highly utilized areas of a circuit board such as near BGA socket connectors.
Therefore a need has arisen for a system and method which reduces power delivery, decoupling and package parasitic effects on information handling system circuit board designs.
In accordance with the present invention, a system and method are provided which substantially reduce the disadvantages and problems associated with previous methods and systems for power supply to information handling system components through a circuit board. Power, ground and signal vias connecting with the component are configured according to one or more factors to create a desired level of parasitic capacitance. The parasitic capacitance offsets the impact of parasitic inductance associated with the component on the supply of power to the component, such as impacts relating to parasitic inductance that arise during power transients.
More specifically, an information handling system circuit board has a ball grid array processor socket disposed on its surface plane to interface processor connectors with circuit board signal wirelines through socket connectors. Power is provided to the processor from a power plane through a socket connector by a power via having a barrel length extending from the power plane to the socket. Ground is provided to the processor from a ground plane through a socket connector by a ground via having a barrel length extending from the ground plane to the socket. Application of power to the processor faces the parasitic inductance that disrupts power delivery, signal compensation and high speed decoupling. The power, ground and signal vias are configured to create a desired parasitic capacitance to offset the parasitic inductance. The desired parasitic capacitance is created by consideration of one or more factors including, the radius associated with the power via equivalent line charge, the distance associated with the line charges between capacitively coupled vias and the via barrel length.
The present invention provides a number of important technical advantages. One example of an important technical advantage is that coupled via structures reduce the impact of package parasitics, such as inductance, with the presence of greater parasitic capacitance. The increased parasitic capacitance reduces or eliminates the need for discrete component solutions and provides improved signal compensation, power delivery and high speed decoupling. For instance, greater parasitic capacitance of between 0.1 pF and 0.4 pF may be generated for each capacitively coupled via structure in highly utilized areas of a circuit board design, such as BGA locals, depending upon the spatial geometry of the coupled via structure.
The present invention may be better understood, and its numerous objects, features and advantages made apparent to those skilled in the art by referencing the accompanying drawings. The use of the same reference number throughout the several figures designates a like or similar element.
Information handling system power supply to low voltage electronic components has the effect of parasitic inductance during power transients reduced by configuring power and ground vias associated with the electronic component to have a desired parasitic conductance. For purposes of this disclosure, an information handling system may include any instrumentality or aggregate of instrumentalities operable to compute, classify, process, transmit, receive, retrieve, originate, switch, store, display, manifest, detect, record, reproduce, handle, or utilize any form of information, intelligence, or data for business, scientific, control, or other purposes, For example, an information handling system may be a personal computer, a network storage device, or any other suitable device and may vary in size, shape, performance, functionality, and price. The information handling system may include random access memory (RAM), one or more processing resources such as a central processing unit (CPU) or hardware or software control logic, ROM, and/or other types of nonvolatile memory. Additional components of the information handling system may include one or more disk drives, one or more network ports for communicating with external devices as well as various input and output (I/O) devices, such as a keyboard, a mouse, and a video display. The information handling system may also include one or more buses operable to transmit communications between the various hardware components.
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Application of power to processor 14 results in package parasitic effects, such as parasitic inductance and parasitic capacitance, that have intensified impact on power delivery, high speed decoupling and signal compensation with increased processor speed, increased circuit board wiring density and reduced power voltages. In particular, parasitic inductance adversely impacts power delivery during transient conditions, especially where processors power demands increase more instantaneously with relatively low supply voltages. In contrast, parasitic capacitance tends to aid power delivery by reducing the impact of parasitic inductance during transient conditions. Inter via spatial relationships define the amount of parasitic capacitance with strong dependencies on via structure within circuit board 12. For instance, in a typical circuit board design, a range of between 0.1 pF and 0.4 pF of capacitance are available per via structure depending on the spatial via geometry. Configuring power, ground and signal vias according to factors associated with parasitic capacitance allows the integration of a desired parasitic capacitance to a power delivery solution to the effects of parasitic inductance. For instance, the radius associated with the equivalent line charge of a power via, the distance associated with the line charges between associated power and ground vias and the via barrel length are used as factors to build a model and simulation of the circuit board that calculates the parasitic capacitance, such as the Q3D and Etch Spies modeling systems. The increase and locality of the capacitive parasitics through via configuration offsets package inductance, appearing as distributed capacitance that provides local high speed decoupling at the socket contacts of an electronic component.
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Although the present invention has been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the invention as defined by the appended claims.