US 20080282216 A1
A multi-function core base cell includes a set of functional microcircuits. These microcircuits are used to design a Library of Logic Function Macros. The functional macros consisting of one or more microcircuits have a fixed and complete physical layout similar to a conventional standard cell library macro set. In addition to a core functional macro set, primary input/output buffers and commonly used single and dual port memory blocks are also defined in the library. The library includes all the ASIC synthesis, simulation, and physical design rules.
17. An ASIC device comprising:
a core base cell comprising a plurality of semiconductor components interconnected by a first, second and third metal level having insulating layers therebetween;
a first metal level masked on said core base cell, said first metal level comprising a first unique mask;
a second metal level masked through a first via level through an insulating level deposited over said first metal level, said second metal level comprising a second unique mask;
a third metal level masked through a second via level through an insulating level deposited over said second metal level, said third metal level comprising a third unique mask; and
a fourth level masked on said third level, said fourth level mask being a common mask to all ASIC devices for completing the ASIC device;
thereby completing the personalization of an ASIC device using only three unique masking levels.
18. The ASIC device of
19. The ASIC device of
20. The ASIC device of
21. The ASIC device of
22. The ASIC device of
a microcircuit chip comprising a plurality of said core base cells formed thereon;
input and output buffers positioned along a periphery of said microcircuit chip; and
memory blocks positioned along said periphery of said microcircuit chip.
23. The ASIC device of
24. A process for fabricating an ASIC device comprising:
providing a wafer that has been processed through second via level using standard silicon integrated circuit processing steps;
personalizing a third metal level by masking said third metal level which has been deposited over said second via level on said wafer using a first unique mask;
masking a third via level on said third metal level through an insulating level over said third metal level using a second unique mask;
personalizing a fourth metal level by masking said fourth metal level using a third unique mask on said third via level, whereby said third via level connects said third metal level to said fourth metal level; and
masking a fifth metal level over a common fourth via level masking step onto said fourth metal level, whereby said fifth metal level connects said third metal and fourth metal levels to an input and an output of said ASIC device;
said wafer, said third metal level, said third via level, said fourth metal level, said fourth via level and said fifth metal level forming a core base cell.
25. The process of
26. The ASIC device of
a first inverter, a second inverter, a third inverter and a fourth inverter;
a first two input NAND gate and a second two input NAND gate;
a three input NAND gate; and
a latch circuit.
27. The ASIC device of
said fourth inverter comprises a 3× inverter;
said first NAND gate comprises a two input NAND gate;
said second NAND gate comprises a two input NAND gate; and
said third NAND gate comprises a three input NAND gate.
28. The ASIC device of
29. The ASIC device of
30. The ASIC device of
31. The ASIC device of
32. The ASIC device of
33. The ASIC device of
34. The process of
35. The process of
36. The process of
This application claims priority to and is a divisional of application Ser. No. 11/147,024 filed on Jun. 7, 2005, which in turn claims priority to prior U.S. Provisional Application No. 60/578,371, entitled A Method for Designing Structured ASICS in Silicon Processes with Three Unique Masking Steps, filed Jun. 9, 2004, both applications are incorporated herein in their entirety for all purposes.
Various embodiments of the invention relate to the design and fabrication of application specific integrated circuit (ASIC) devices, and in particular, but not by way of limitation, to a method of ASIC design and fabrication with three unique masking steps per ASIC part.
A general function ASIC device consists of logic functions such as combinatorial circuits, latches and registers, memory blocks, input/output buffers, and other custom functions. In the prior art, logic functions are derived from a configurable logic block (CLB) in the same manner as these functions are configured in Field Programmable Gate Array (FPGA) devices, except interconnections are made in a semiconductor process line with reduced masking steps. One example of such a CLB is shown in
The art is therefore in need of a less complex and more flexible process to manufacture ASIC devices.
In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein in connection with one embodiment may be implemented within other embodiments without departing from the scope of the invention. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the claims are entitled. In the drawings, like numerals refer to the same or similar functionality throughout the several views.
In an embodiment, a multifunction core base cell is defined. As will be described infra, the core base cell consists of a set of functional microcircuits. These microcircuits are used to design a Library of Logic Function Macros. The functional macros consist of one or more microcircuits having a fixed and complete physical layout similar to a conventional standard cell library macro set. In addition to the core functional macro set, primary input/output buffers and commonly used single and dual port memory blocks are also defined in the library. The library includes all the ASIC synthesis, simulation, and physical design rules.
An architecture of a chip image is defined. The chip has an optimum area defined for rows and columns of the core base cells, memory blocks, input and output buffers and other custom logic functions. The chip image layout with all these functions in place is known as the masterslice. This masterslice is used to design and fabricate a family of ASIC devices. All mask levels, except masks for metal level M3, metal level M4, and V3 (interconnection between metal levels M3 and M4) are common for all the ASICs designed using this masterslice. That is, as will be described infra, M3, V3, and M4 are the only unique masks per unique ASIC part. One or more of these partially preprocessed wafers through a V2 process step are used to complete the fabrication of an ASIC device. Therefore, fabrication of an ASIC device is started with masterslice wafers already pre-processed up to the deposition of M3 from stock. Actual wafer process procedure is a well known prior art and is not further described.
Flexibility of auto placement and auto routing with EDA tools in this design method is the same as that of designing ASICs with the conventional Standard Cell ASIC design systems, while the mask cost and fabrication time is greatly reduced from the conventional methodology.
Since normally less than 15 percent of the logic macro functions in an ASIC device are registers, it is more efficient for the circuit density of the chip to include only half of a DFF register in the base core cell. A register macro function then will take two base core cells. Another microcircuit in the base cell is a latch function 230—half of a DFF register. A latch function is used to implement DFF, DFFS, and other register functions. As illustrated in
All microcircuit inputs connected to the transistor gate terminals are connected to diodes formed with N+ diffusion to P_substrate. Since the P_substrate is connected to the ASIC ground, these diodes get reverse biased. These diodes prevent thin oxide of the transistors from getting damaged during the wafer process by the electrostatic charge accumulating on the thin silicon oxide terminal. This is an early solution for the problem known as Antenna Rules requirements in the design of the conventional Standard Cell ASICs.
The physical layout of the microcircuits at the transistor level, and the interconnections of the transistors to form the microcircuit functions, are well-known among those of skill in the art, and will not be further described.
A difference between the design of library logic function macros in embodiments of the invention and the design of the library logic functions in the prior art is that the macro functions in an embodiment of the invention have the same optimum design characteristics as those in the conventional Standard Cell libraries. Logic function macros consist of just the circuits needed to do the logic function, whereas in the prior art of structured ASIC design, logic function macros are configured from multi-purpose FPGA (Field Programmable Gate Array) types of CLBs, which result in additional decode circuits needed to direct the signal path through these CLBs.
Unused input pins of the microcircuits are connected to VDD or GND pins to bias the unused microcircuits in a steady state, a state in which no current flows through the unused transistors. Delay and power dissipation associated with each of the macros is that of the logic function used in the ASIC design and not of the configurable logic blocks (CLBs) in the prior art. For many functions, delay and power dissipation of the CLBs is several times more than that of the needed logic function. Examples of some of the library logic functions designed in this invention are given in Table 1 below.
In different embodiments, the logic function macro may be as simple as an inverter with a 1× drive (JNV—1×), or it may be a more complex logic function macro such as a DFF with Scan and Asynchronous Reset (DFFSAR—1×). In the several embodiments, most logic function macros in the library have multiple driving strengths to achieve optimum power performance characteristics at the ASIC level.
The variety of logic function macros that can be designed using the microcircuits of the core base cell far exceeds the functions that can be configured from the CLBs in the prior art. This comprehensive set of logic function macros provides performance and power dissipation characteristics comparable to the conventional Standard Cell designs.
As earlier stated, the macros' functions may be as simple as an inverter, a NAND, or a NOR, or as complex as a DFF with scan and asynchronous pre-set, a FULL Adder, or a decode DE-CODE. For some of the simple macro functions, microcircuits of equivalent logic functions are used one to one. For example, microcircuit inverter INV1 when used as an inverter macro with 1× drive becomes INV—1× in the library. At the macro level, input and output of the inverter are given global names like PA0 and P10 (See
An example of a more complex macro function is a two-way Exclusive OR function with 4× driving strength. In the library such a macro function may be referred to as XOR2 —4×. An example embodiment of an Exclusive OR Macro function configured with microcircuits is illustrated in
The design of the macro XOR2 —4×, consisting of all process levels up to metal level M3, may be saved in the Library's graphics (GDS) database under a particular cell name such as XOR2 —4×. Global input and output pin names, such as PA0, PB0, and P10, are respectively assigned in the layout of the macro. These signal pins are the only signal pins connected to other logic function macros, as described by the ASIC gate level net list. In an embodiment, the XOR2 —4× macro function is implemented in one core base cell. In other embodiments, implementation of some logic functions may take two or more base cells.
Layouts of all the library logic function macros are created and saved in the GDS database or similar database with unique cell names for each macro function. Each driving-strength of each function is also given a unique name. All these logic function designs use the same base cell up to the metal level M2 and Vias V2 (M2 to M3 Vias).
An I/O cell is defined to implement I/O buffer logic functions. Transistors to implement these functions are interconnected up to metal level M2. Functions like Receiver, Driver, Transceiver, Receiver with Pull-up, or Receiver with Pull-down can be completed with metal level M3 only, using the partially pre-wired I/O base cell. Circuits in the unused I/O buffer cells are biased to steady state. I/O cells also include Electrostatic Discharge (ESD) protection devices.
ASIC device functions consist of combinatorial logic, registers, memory blocks, special functions (e.g. phase lock loops), and I/O buffers. In the masterslice for designing a family of structured ASIC chips, area is divided between logic, memory, special functions and I/O buffers. The number and types of memory blocks are selected to meet as many applications as possible. Very often large memory functions are configured from smaller memory blocks available in the masterslice. For example, a 2Kx9 SRAM memory function can be configured from two 1Kx9 SRAM memory blocks. At the ASIC level, routing to and from memory blocks will be done at metal levels M3 and M4 only. Unused memory blocks and unused parts of memory blocks are biased to a steady state.
A chip size is selected to meet circuit density for a family of ASIC devices, in terms of logic, memory, and I/O buffers. A floorplan of a masterslice is shown in
A structured ASIC library database consists of simulation, timing, and graphics data for each logic function macro under its own unique name in the same manner as library database for conventional Standard Cell ASIC design does. Since the ASIC design library and other database created in this invention is in the same format as the database for conventional cell based ASIC design systems, physical design of the structured ASIC devices can be done in the conventional cell based ASIC design methodologies, except the routing is done only at metal levels M3 and M4.
In the foregoing detailed description of embodiments of the invention, various features are grouped together in one or more embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments of the invention require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the detailed description of embodiments of the invention, with each claim standing on its own as a separate embodiment. It is understood that the above description is intended to be illustrative, and not restrictive. It is intended to cover all alternatives, modifications and equivalents as may be included within the scope of the invention as defined in the appended claims. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. In the appended claims, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein,” respectively. Moreover, the terms “first,” “second,” and “third,” etc., are used merely as labels, and are not intended to impose numerical requirements on their objects.
The abstract is provided to comply with 37 C.F.R. 1.72(b) to allow a reader to quickly ascertain the nature and gist of the technical disclosure. The Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.