US 20080284624 A1 Abstract An unencoded m-bit data input sequence is divided into a block of n bits and a block of m−n bits. The block of n bits is divided into a first set of n+1 encoded bits, wherein at least one of P1 subblocks of the first set satisfies a G, M and I constraints. The first set of n+1 encoded bits is mapped into a second set of n+1 encoded bits wherein at least one of P2 subblocks of the second set gives rise to at least Q1 transitions after 1/(1+D
^{2}) preceding. A second set of n+1 encoded bits is divided into P3 encoded subblocks and the P3 encoded subblocks are interleaved among (m−n)/s unencoded symbols so as to form a (m+1)-bit output sequence codeword which is then stored on a data storage medium.Claims(1) 1. A method for encoding a data input sequence of m bits into an output sequence codeword of m+1 bits, where m is an integer multiple of an ECC symbol size s, the method comprising the steps of:
receiving a data stream of unencoded m-bit input sequences; dividing each m-bit input sequence into a first block of n bits and a second block of m−n unencoded bits, where n is an integer multiple of s; encoding the first block of n bits into a first set of n+1 encoded bits, wherein at least one of P1 subblocks of the first set of n+1 bits satisfies a G constraint, an M constraint and an I constraint; mapping in a one-to-one manner the first set of n+1 encoded bits into a second set of n+1 encoded bits wherein, at least one of P2 subblocks of the second set of n+1 bits gives rise to at least Q1 transitions after 1/(1+D ^{2}) preceding;dividing the second set of n+1 encoded bits into P3 encoded subblocks; interleaving the P3 encoded subblocks among (m−n)/s unencoded symbols so as to form the (m+1)-bit output sequence codeword; and storing the output sequence codeword on a data storage medium. Description The present invention relates generally to RLL encoding and, in particular, to designing a mother code having a first rate which may then be used to design additional, higher-rate codes. Runlength-limited (RLL) codes have been widely used in magnetic and optical data storage to eliminate sequences that are undesired for the processes of recording and reproducing digital data. Various classes of RLL codes are used in practice. For example, peak detection systems employing runlength-limited RLL(d,k) constrained codes such as rate-1/2 RLL(2,7) and rate-2/3 RLL(1,7) codes have been predominant in digital magnetic storage at low normalized linear densities. At moderate normalized linear densities, the introduction of partial-response maximum-likelihood (PRML) detection channels into data storage required a different type of constrained codes. This class of codes, which are known as PRML(G,I) or PRML(0,G,I) codes, facilitates timing recovery and gain control, and limits the path memory length of the sequence detector, and therefore the decoding delay, without significantly degrading detector performance. PRML(G,I) codes may also be used in conjunction with 1/(1⊕ D The first PRML(G, I) code that was implemented in a data storage device had the code rate 8/9 and satisfied the constraints G=4 and I=4. In addition, it satisfied a VFO constraint, which is also known as the M constraint, allowing discrimination of encoded data from the synchronization preamble and therefore fast start-up of the PRML receiver. The M constraint limits the maximum runlength of ones at the modulation encoder output (input of 1/(1⊕ D The RLL code used in Linear Tape Open (LTO) standards for generations 2 to 4 (hereinafter LTO 2-4) is a twins-constrained maximum-transition-run MTR(j,k,t) code that requires 1/(1⊕ D) preceding. It satisfies j, k and t constraints at the input of the 1/(1⊕ D) precoder. The k constraint limits the maximum runlength of zeros at the modulation encoder output (input of 1/(1⊕ D) precoder) to k. The j constraint limits the maximum runlength of ones at the modulation encoder output (input of 1/(1⊕ D) precoder) to j. The twins constraint t limits the maximum number of consecutive twins (pair of zeros or pair of ones) at the modulation encoder output (input of 1/(1⊕ D) precoder) to t. The G and I constraints at the input of 1/(1⊕ D Construction of rate-8/9 PRML(G, I, M) codes has previously been described. Additionally, the rate of non-concatenated PRML(G, I, M) codes that have been constructed is less than 16/17. The next generation LTO standard (LTO 5) will likely have a rate-32/33 or rate-48/49 RLL code in order to increase the format efficiency. One method for the design of such codes is the straightforward extension of the rate-16/17 LTO 2-4 code by inserting two or four more uncoded bytes to obtain a rate-32/33 or rate-48/49 code, respectively. However, this solution results in a rate-32/33 RLL code with parameters G=29, I=19, M=39 or a rate-48/49 RLL code with parameters G=45, I=27, M=55. These values are not acceptable because the constraints are too weak. Another solution would be to generate a rate-16/17 encode and decode table using a computer and use computer-aided design tools to generate Boolean-based or ROM-based logic for encoding and decoding based on the encode and decode table. However, this solution is too complex and would require more than 500,000 gates per channel to implement. Additionally, the encoding operation needs a compact representation such that it can be included into the LTO 5 standard; specifying 65,536 17-bit codewords in the LTO 5 standard is not acceptable. Therefore, there is a need for an algorithmic approach to design an RLL code that satisfies similar constraints as the LTO 2-4 RLL code does. The present invention provides a method for encoding a data input sequence of m bits into an output sequence codeword of m+1 bits, where m is an integer multiple of an ECC symbol size s. The method includes the steps of receiving a data stream of unencoded m-bit input sequences and dividing each m-bit input sequence into a first block of n bits and a second block of m−n unencoded bits, where n is an integer multiple of s. The first block of n bits is divided into a first set of n+1 encoded bits, wherein at least one of P1 subblocks of the first set of n+1 bits satisfies a G constraint, an M constraint and an I constraint. The first set of n+1 encoded bits is mapped in a one-to-one manner into a second set of n+1 encoded bits wherein at least one of P2 subblocks of the second set of n+1 bits gives rise to at least Q1 transitions after 1/(1+D In one embodiment, an encoder generates a rate-16/17 PRML(G=14, I=11, M=23) mother code from which higher rate codes may be generated. In various embodiments, such higher rate codes include a rate-32/33 PRML(G=14, I=11, M=23) code (RLL 1), a rate-48/49 PRML(G=22, I=15, M=31) code (RLL 2) and a rate-48/49 PRML(G=14, I=19, M=39) code (RLL 3). Many of the functional units described in this specification have been illustrated in the Figures as blocks, in order to more particularly emphasize their implementation independence. For example, a block may be implemented as a hardware circuit comprising custom VLSI circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components. A block may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices or the like. Blocks may also be implemented in software for execution by various types of processors. An identified block of executable code may, for instance, comprise one or more physical or logical blocks of computer instructions which may, for instance, be organized as an object, procedure, or function. Nevertheless, the executables of an identified block need not be physically located together, but may comprise disparate instructions stored in different locations which, when joined logically together, comprise the block and achieve the stated purpose for the block. Indeed, a block of executable code could be a single instruction, or many instructions, and may even be distributed over several different code segments, among different programs, and across several memory devices. Similarly, operational data may be identified and illustrated herein within blocks, and may be embodied in any suitable form and organized within any suitable type of data structure. The operational data may be collected as a single data set, or may be distributed over different locations including over different storage devices, and may exist, at least partially, merely as electronic signals on a system or network. Furthermore, the described features, structures, or characteristics of the invention may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided, such as examples of programming, software blocks, logic blocks, user selections, network transactions, database queries, database structures, hardware blocks, hardware circuits, hardware chips, etc., to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention may be practiced without one or more of the specific details, or with other methods, components, and so forth. In other instances, well-known steps, components or operations are not shown or described in detail to avoid obscuring aspects of the invention. The present invention provides an algorithmic approach to the design of higher-rate PRML(G, I, M) codes which also enforce a minimum number of transitions per codeword. A rate-16/17 PRML(G=6, I=7, M=15) mother code is provided that enforces at least four transitions per codeword. To this end the input to the encoder is partitioned into a first set of blocks which are mapped into a second set of blocks and G, I and M constraints are imposed on at least one of the second set of blocks. The encoding operation is initially performed by detecting violations and indicating in encoded data the type of violations that have occurred. Further stages of encoding by violation detection and substitution tighten the code constraints and rule out DSS and Re Sync patterns. The mother code is then used to construct higher-rate 32/33 or 48/49 PRML(G, I, M) codes by combining uncoded 8-bit bytes with the 17-bit output from the mother code. The present invention also provides a rate-32/33 PRML(G=14, I=11, M=23) code (RLL 1), a rate-48/49 PRML(G=22, I=15, M=31) code (RLL 2) and a rate-48/49 PRML(G=14, I=19, M=39) code (RLL 3). The notations x(i) and x Column vectors are often specified by the transpose of a row vector and the superscript T is used to indicate the transpose operation. Two different notations are used herein for Boolean operations. The following convention has been used to specify Boolean code constraints and to perform Boolean operations involving multiplication of a matrix and a vector: overbar stands for negation, multiplication for AND, and addition for OR. Among these three operations, negation has the highest precedence, AND (multiplication) has second highest precedence and OR (addition) has the lowest precedence. Exclusive-OR (XOR) is indicated by ⊕. Encoder and decoder hardware based on Boolean logic is specified using the MATLAB notation for Boolean operations. In particular, stands for negation, & for AND, and | for OR. Again, among these three operations, negation () has the highest precedence, followed by AND (&) and OR (|) which has the lowest precedence, i.e., the usual Boolean precedence rules apply. The next section describes the requirements upon the resulting codes in terms of prohibited output sequences, which therefore determines the requirements on the mother code. The steps in creating the mother code are described both in text and via illustration in compact matrix notation. The section is followed by a section describing a corresponding decoder for the mother code. Next are sections which include Boolean listings in MATLAB format of the requirements for the third encoding and decoding stages for the mother code. Finally, the last three sections describe the design of rate-32/33 PRML(G=14, I=11, M=23) code, rate-48/49 PRML(G=22, I=15, M=31) code and rate-48/49 PRML(G=14, I=19, M=39) code from the mother code. The storage device Construction of Rate-16/17 PRML(G=6, I=7, M=15) Mother Code with Minimum Transition Density where the superscript E refers to the encoding operation and the addition and the multiplication operations in the matrix multiplication are Boolean OR and Boolean AND operations, respectively. For a given 16-bit encoder input, only one of the components of a partitioning vector is one whereas all the other components are zero. This property is related to the fact that the input space is partitioned in a mutually exclusive manner. Finally, concatenation of encoding stages is done such that the output of the k-th encoding stage, for k=1,2 in a three-stage system, is the input of the next encoding stage, i.e., i The first encoder stage The output b may be partitioned into two blocks of size 8 bits and 9 bits which will be used to construct a rate-32/33 PRML(G, I, M) code. Similarly, the output b may be partitioned into four blocks of size 4 bits, 4 bits, 5 bits and 4 bits which will be used to construct a rate-48/49 PRML(G, I, M) code. At the end of the first encoder stage The constraints satisfied by o G Constraints: I Constraints: M Constraints: Therefore, the code obtained at the output of the first encoder stage The second encoder stage
The bold pattern within the prohibited pattern b is used to detect violations during the second stage of encoding whereas the bold pattern in the substitute pattern c or d (if the presence of channel errors and errors in the first decoder stage The constraints satisfied by o G Constraints: I Constraints: M Constraints: Therefore, the code obtained at the output of the second encoder stage Coded data y must be precoded using a 1/(1⊕ D The first set of requirements, which ensure that the first coded subblock gives rise to at least Q
where all of the additions in the above equations are integer additions and [y′ The second set of requirements, which ensure that the second coded subblock gives rise to at least Q
where all of the additions in the above equations are integer additions and [y′ The third encoder stage
The bold pattern within the prohibited pattern c is used to detect violations during the third stage of encoding whereas the bold pattern in the substitute pattern y or z (if the presence of channel errors is considered, then y, the output of the third encoder stage The constraints satisfied by o G Constraints: I Constraints: M Constraints: Minimum Transition Density Constraints: _{4} + _{5} +y _{6} +y _{7} +y _{8}=1 _{13} + _{14} +y _{15} +y _{16} +y _{17}=1The code obtained at the output of the third (and last, when k=1, 2, 3) encoding stage is a PRML(G=6, I=7, M=15) code that enforces at least Q where the superscript D refers to the decoding operation. Finally, concatenation of decoding stages is done such that the output of the k-th decoding stage, k=1, 2 (in general, k=1, . . . , K−1) is the input of the next decoding stage, i.e., i As will be shown in the section on implementing the rate-16/17 encoder and decoder, the encoder and decoder may be implemented with few two-input gates. All of the Boolean equations for encoding and decoding are the result of multiplication of a specific matrix and a partitioning column vector that are specified in the next two sections. Matrix-Vector Description of Encoding Stages for Rate-16/17 PRML(G=6, I=7, M=15) Code with Minimum Transition Density In this section, the encoding of 16 bits to 17 bits, that is the generation of codewords of the mother code, is fully described using a matrix-vector notation. A compact representation of all three encoding stages
Partitioning column vector: n
are used to express the components of the partitioning vector:
Partitioning column vector: n
Partitioning column vector: n ^{E})=u^{T}=[u_{1 }u_{2 }u_{3}]^{T }where Matrix-Vector Description of Decoding Stages For Rate-16/17 PRML(G=6, I=7, M=15) Code with Minimum Transition Density In this section, decoding 17-bits to 16-bits is described using matrix-vector notation. A compact representation of all three decoding stages
Partitioning column vector: n
Partitioning column vector: n
Partitioning column vector: n The encoding of 16-bits to 17-bits to generate the mother code in accordance with the present invention is completely described by the following MATLAB Boolean operations. Sixteen inputs bits a(1) . . . a(16) are input to a first encoder stage The following Boolean equations describe the second encoder stage b(15)&q(1)|b(7)&q(2)|q(3)|b(15)&q(4) The following Boolean equations describe the third encoder stage The following Boolean equations describe the first decoder stage The following Boolean equations describe the second decoder stage The following Boolean equations describe the third (last) decoding stage with 17-bit input e and 16-bit output f The third decoder stage e(6)&e(7)&e(8)&t5 The encoder and the decoder may be implemented with a total of 936 two-input AND and OR gates (559 two-input AND gates and 377 two-input OR gates). In one embodiment of a rate-32/33 PRML code of the present invention, m=32, n=16, s=8, Q The rate-32/33 PRML(G=14, I=11, M=23) code rules out both DSS and Re Sync and has an error propagation of 8 NRZ bits assuming 4-way C1 interleaving. In an embodiment of a rate-48/49 PRML code, m=48, n=16, s=8, Q In another embodiment of a rate-48/49 PRML code, m=48, n=16, s=8, Q It is important to note that while the present invention has been described in the context of a fully functioning data processing system, those of ordinary skill in the art will appreciate that the processes of the present invention are capable of being distributed in the form of a computer readable medium of instructions and a variety of forms and that the present invention applies regardless of the particular type of signal bearing media actually used to carry out the distribution. Examples of computer readable media include recordable-type media such as a floppy disk, a hard disk drive, a RAM, and CD-ROMs and transmission-type media. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiment was chosen and described in order to best explain the principles of the invention, the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated. Moreover, although described above with respect to methods and systems, the need in the art may also be met with a computer program product containing instructions for encoding a data input sequence of m bits into an output sequence codeword of m+1 bits or a method for deploying computing infrastructure comprising integrating computer readable code into a computing system for encoding a data input sequence of m bits into an output sequence codeword of m+1 bits. Referenced by
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