US20080289867A1 - Multi-strand substrate for ball-grid array assemblies and method - Google Patents
Multi-strand substrate for ball-grid array assemblies and method Download PDFInfo
- Publication number
- US20080289867A1 US20080289867A1 US12/131,691 US13169108A US2008289867A1 US 20080289867 A1 US20080289867 A1 US 20080289867A1 US 13169108 A US13169108 A US 13169108A US 2008289867 A1 US2008289867 A1 US 2008289867A1
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- Prior art keywords
- bga
- circuit board
- printed circuit
- array
- semiconductor die
- Prior art date
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- 238000000034 method Methods 0.000 title claims description 43
- 230000000712 assembly Effects 0.000 title abstract description 3
- 238000000429 assembly Methods 0.000 title abstract description 3
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- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 238000001465 metallisation Methods 0.000 claims description 4
- 238000011109 contamination Methods 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 238000000465 moulding Methods 0.000 claims description 2
- 239000007787 solid Substances 0.000 claims description 2
- KTXUOWUHFLBZPW-UHFFFAOYSA-N 1-chloro-3-(3-chlorophenyl)benzene Chemical compound ClC1=CC=CC(C=2C=C(Cl)C=CC=2)=C1 KTXUOWUHFLBZPW-UHFFFAOYSA-N 0.000 description 28
- 238000004519 manufacturing process Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 5
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- 229920003217 poly(methylsilsesquioxane) Polymers 0.000 description 1
- 150000003505 terpenes Chemical class 0.000 description 1
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Definitions
- This invention relates, in general, to semiconductor packages, and more particularly, to ball-grid array semiconductor packaging.
- BGA Ball-grid array
- an organic resin printed wiring board substrate having a thickness on the order of 0.35 millimeters (mm) is placed on a metal pallet or support device.
- the metal pallet provides support for the printed wiring board during the majority of assembly steps.
- the printed wiring board comprises a single BGA substrate or a single row or strand of a number of BGA substrates.
- the largest available single strand printed wiring board is a 1 ⁇ 6 printed wiring board with a maximum total length of about 200 mm.
- a semiconductor die having a multitude of bonding pads is attached to a die pad located on the top side of the BGA substrate. Wire bonds are then attached to the bonding pads and to bond posts on the top side of the BGA substrate.
- the semiconductor die and the wire bonds are encapsulated with an organic material. After encapsulation, the encapsulation material is cured at an elevated temperature. Conductive solder balls are then attached to contact pads, which are on the lower side of the BGA substrate and electrically coupled through conductive traces to the bond posts, using a solder reflow process. Each BGA package is then marked. When a single strand of multiple BGA packages is used, a singulation process such as a punch press is used to separate the multiple BGA packages into single units.
- the above assembly process has several disadvantages. Because the above process requires a metal pallet to support the thin BGA substrates during the majority of assembly steps, the process is not conducive to large scale automated assembly. As a result, manufacturers must purchase additional equipment to assemble BGA packages. This requires capital investment in equipment and additional factory space. Also, because only single substrates or a single strand of a several substrates is used, it is difficult for manufacturers to produce a large volume of BGA packages efficiently. In addition, the above process requires significant labor inputs to load and unload the metal pallets or support devices at the various process steps. This negatively impacts manufacturing cycle time and quality. Furthermore, the pallets are expensive because they require precise tolerances for use with automated equipment and they require a manufacturer to carry a large inventory to support work-in-process (WIP) throughout a manufacturing line.
- WIP work-in-process
- each BGA substrate must maintain a planarity variation of less than approximately 0.15 mm (approximately 6 mils) as measured at three points across a substrate. In other words, each BGA substrate must not be excessively warped or non-planar. Because of this strict standard and a concern over warpage, printed wiring board suppliers and BGA semiconductor manufacturers have not been motivated to expand beyond the existing 1 ⁇ 6 single strand printed wiring board.
- FIG. 1 illustrates a top view of an embodiment of a printed circuit board substrate for BGA assemblies according to the present invention
- FIG. 2 illustrates an enlarged cross-sectional side view of one BGA assembly according to FIG. 1 .
- FIG. 1 illustrates a top view of multi-strand substrate, printed circuit board, or wiring board (PCB) 11 .
- PCB 11 typically comprises an organic epoxy-glass resin based material, such as bismaleimide-triazin (BT) resin, FR-4 board, or the like.
- PCB 11 includes BGA substrates or patterned package substrates 12 arranged in N rows 14 and M columns 16 to form an N by M pattern or array.
- Each of BGA substrates 12 includes a die attach or bonding pad 13 , which typically comprises copper or gold plated copper.
- Die attach pad 13 is a solid metallization area or a patterned metallization area shaped like a cross, “Union Jack”, or other specialized geometry. To avoid overcrowding the drawing, conductive traces are not shown (conductive traces are shown in FIG. 2 ).
- PCB 11 is formed using well known printed circuit board manufacturing techniques.
- N and M are preferably at least greater than or equal to 2.
- N and M are selected such that after all assembly steps are completed, each of BGA substrates 12 exhibit a planarity variation of less than approximately 0.15 mm across each of BGA substrates 12 .
- each of BGA substrates 12 does not warp to a non-planar condition in excess of approximately 0.15 mm.
- PCB 11 has a thickness 26 (shown in FIG. 2 ) sufficient to minimize warpage or non-planarity. As stated below, thickness 26 preferably is on an order of at least 0.5 mm.
- warpage within a given unit is determined by measuring a maximum difference between a seating plane (formed by the three conductive solder balls (see FIG. 2 ) having the greatest amount of standoff from the BGA substrate) and the conductive solder ball with the least amount of stand-off from the substrate. The warpage measurement is taken after PCB 11 is separated into individual BGA units.
- PCB 11 further includes a plurality of stress-relief slots or slots 19 at various locations on PCB 11 .
- slots 19 extend through PCB 11 .
- Slots 19 are all the same size or of different sizes. Slots 19 further minimize warpage of each of BGA substrates 12 .
- PCB 11 preferably includes alignment holes 21 along one side or both sides of PCB 11 . Alignment holes 21 extend from the top surface to the lower surface of PCB 11 . Alignment holes 21 are placed according to the requirements of die attaching and wire bonding equipment to support automated assembly.
- PCB 11 preferably includes holes 22 around the perimeter of PCB 11 and hole 23 along one side of PCB 11 . Holes 22 provide for an automatic orientation feature so that a manufacturer does not insert PCB 11 into assembly equipment backwards or reversed. Hole 23 provides for an orientation feature to allow a manufacturer to robotically place PCB 11 in a jig apparatus.
- N is equal to 2 and M is equal to 6 with PCB 11 having a length 17 on an order of 187 mm and a width 18 on an order of 63 mm.
- the above specifications also are preferred for a 23 mm by 23 mm and a 25 mm by 25 mm BGA device.
- N is equal to 4 and M is equal to 12 with length 17 on an order of 200 mm and width 18 on an order of 63 mm.
- N is equal to 4 and M is equal to 12 with length 17 on an order of 212 mm and width 18 on an order of 63 mm.
- N is equal to 3 and M is equal to 9 with length 17 on an order of 187 mm and width 18 on an order of 63 mm.
- N is equal to 2 and M is equal to 9 with length 17 on an order of 187 mm and width 18 on an order of 63 mm.
- N is equal to 3 and M is equal 6 with length 17 and width 18 the same as above.
- M is equal to 4 with length 17 on an order of 187 mm and width 18 on an order of 63 mm.
- the above dimensions are preferred to take advantage of standard automatic assembly equipment requirements. This allows a manufacturer to use existing tooling and equipment. The above dimensions are easily modified to meet the requirements of different types of automated assembly equipment.
- FIG. 2 illustrates an enlarged cross-sectional view of one BGA structure, assembly, or package 25 after assembly but before singulation or separation into individual packages.
- BGA structure 25 comprises one of BGA substrates 12 within PCB 11 .
- PCB 11 with BGA substrates 12 preferably has a thickness 26 such that PCB 11 can undergo magazine-to-magazine automated assembly processes without using a metal support pallet.
- Thickness 26 also is selected to minimize planarity variation of each of BGA substrates 12 .
- thickness 26 is greater than approximately 0.5 mm.
- thickness 26 is in a range from approximately 0.5 mm to approximately 0.8 mm.
- BGA structure 25 further includes a semiconductor die 24 attached die attach pad 13 on an upper surface of each of BGA substrates 12 .
- Semiconductor die 24 has a plurality of bonding or bond pads 28 .
- Each of BGA substrates 12 has a conductive connective structure comprising bond posts 31 , upper conductive traces 32 , vias 33 , lower conductive traces 36 and contact pads 38 .
- Conductive solder balls 41 are attached to contact pads 38 .
- Conductive wires or wire bonds 43 electrically couple bond pads 28 to bond posts 31 .
- semiconductor die 24 is mounted in a “flip-chip” embodiment with bond pads 28 directly connected to bond posts directly below bond pads 28 , eliminating conductive wires 43 and die attach pad 13 .
- An encapsulating layer or encapsulant 46 covers semiconductor die 24 and wire bonds 43 to provide protection of active circuit elements from physical damage and/or corrosion.
- a typical BGA assembly process incorporating PCB 11 having BGA substrates 12 to form BGA structure 25 is described as follows.
- First PCB 11 is provided having the desired N by M pattern.
- PCB 11 is loaded onto an automated die attach machine such as an ESEC 2006 .
- This type of die attach machine is an industry standard machine that manufacturers use to attach semiconductor die to other types of semiconductor packages such as plastic dual-in-line (PDIP), small outline integrated circuit (SOIC), and QFP packages.
- the die attach machine automatically attaches one semiconductor die 24 to one of die attach pads 13 on PCB 11 .
- semiconductor die 24 is attached to one of die attach pads 13 using a die attach epoxy.
- PCB 11 is then cleaned using an automated cleaning system such as an ULVAC cleaning system available from the ULVAC Corp.
- an automated wire bonder such as a Shinkawa UTC-100 where wire bonds 43 are attached to bond pads 22 and bond posts 31 .
- wire bonding is done using a similar wirebonder configured for semi-automatic operation.
- Encapsulant 46 is applied to cover semiconductor die 24 and wire bonds 43 .
- Encapsulant 46 comprises an organic material and is applied using an over-mold process or a glob-top process.
- an over-mold process automolds from Towa, Fico, or similar suppliers are used.
- encapsulant 46 preferably comprises an organic mold compound.
- encapsulant 46 preferably comprises an anhydride epoxy organic compound.
- the material selected for encapsulant 46 has a thermal coefficients of expansion (TCE) close (within a few points or parts per million) to the TCE's of the material of PCB 11 and semiconductor die 24 .
- TCE thermal coefficients of expansion
- Such encapsulents are available from several suppliers including The Dexter Corp., of Industry, California, Ciba-Giegy Corp., Hitachi Corp., Sumitomo Corp., and Nitto-Denko Corp.
- encapsulant 46 is cured preferably using a belt furnace, vertical oven, or batch oven at a temperature that is function of the type of material used for encapsulant 46 .
- a tray or some other form of protection preferably is used to protect contact pads 38 from foreign matter contamination.
- conductive solder balls 41 are attached to contact pads 38 using a room temperature attach process.
- an automated solder reflow process is used to reflow conductive solder balls 41 .
- Automated reflow equipment such as a belt furnace.
- PCB 11 is again cleaned using automated cleaning equipment with an aqueous or terpene media to remove any corrosive flux residues from the conductive solder ball attachment process.
- Each BGA structure 22 is then marked on an automated marking machine such as an automated laser marker. Optionally, marking occurs immediately following encapsulation.
- each of BGA substrates 12 is divided into individual packages. To divide the packages, a punch-press process is used. Optionally, a routing, dicing, or snapping separation process is used.
- a multi-strand PCB containing an N by M array of BGA substrates for manufacturing BGA type semiconductor packages N and M are selected and the thickness of the PCB is such so as to enable enhanced manufacturing efficiency.
- the enhanced manufacturing efficiency comes from the ability to manufacture more BGA packages from one multi-strand PCB and from the ability to use standard automated assembly equipment. Manufacturing efficiency is enhanced while still providing BGA substrate planarity variation less than approximately 0.15 mm. Because the multi-strand PCB according to the present invention enables the use of standard automated assembly equipment, a BGA manufacturer is able to use the same types of equipment to manufacture different types of packages thus reducing capital expenditures and needed factory floor space. Also, labor costs are reduced and quality is increased because of the reduced handling requirements.
Abstract
Description
- This application is a continuation of U.S. application Ser. No. 11/676,810, filed Feb. 20, 2007, which is a continuation of U.S. application Ser. No. 10/741,065, filed Dec. 19, 2003, which is a continuation of U.S. application Ser. No. 10/255,257, filed Sep. 26, 2002, which is a continuation of U.S. application Ser. No. 08/349,281 filed Dec. 5, 1994.
- This invention relates, in general, to semiconductor packages, and more particularly, to ball-grid array semiconductor packaging.
- Ball-grid array (BGA) semiconductor packages are well known in the electronics industry. BGA packages provide denser surface mount interconnects than quad flat pack (QFP) packages. Industry consensus is that BGA packages are more cost effective than QFP packages for input/output (I/O) requirements greater than 250. However, there is a great demand for cost effective BGA solutions down to 100 I/O.
- During the assembly of a BGA package, an organic resin printed wiring board substrate having a thickness on the order of 0.35 millimeters (mm) is placed on a metal pallet or support device. The metal pallet provides support for the printed wiring board during the majority of assembly steps. The printed wiring board comprises a single BGA substrate or a single row or strand of a number of BGA substrates. The largest available single strand printed wiring board is a 1×6 printed wiring board with a maximum total length of about 200 mm. Next, a semiconductor die having a multitude of bonding pads is attached to a die pad located on the top side of the BGA substrate. Wire bonds are then attached to the bonding pads and to bond posts on the top side of the BGA substrate. Next, the semiconductor die and the wire bonds are encapsulated with an organic material. After encapsulation, the encapsulation material is cured at an elevated temperature. Conductive solder balls are then attached to contact pads, which are on the lower side of the BGA substrate and electrically coupled through conductive traces to the bond posts, using a solder reflow process. Each BGA package is then marked. When a single strand of multiple BGA packages is used, a singulation process such as a punch press is used to separate the multiple BGA packages into single units.
- The above assembly process has several disadvantages. Because the above process requires a metal pallet to support the thin BGA substrates during the majority of assembly steps, the process is not conducive to large scale automated assembly. As a result, manufacturers must purchase additional equipment to assemble BGA packages. This requires capital investment in equipment and additional factory space. Also, because only single substrates or a single strand of a several substrates is used, it is difficult for manufacturers to produce a large volume of BGA packages efficiently. In addition, the above process requires significant labor inputs to load and unload the metal pallets or support devices at the various process steps. This negatively impacts manufacturing cycle time and quality. Furthermore, the pallets are expensive because they require precise tolerances for use with automated equipment and they require a manufacturer to carry a large inventory to support work-in-process (WIP) throughout a manufacturing line.
- Industry standards require that after assembly, each BGA substrate must maintain a planarity variation of less than approximately 0.15 mm (approximately 6 mils) as measured at three points across a substrate. In other words, each BGA substrate must not be excessively warped or non-planar. Because of this strict standard and a concern over warpage, printed wiring board suppliers and BGA semiconductor manufacturers have not been motivated to expand beyond the existing 1×6 single strand printed wiring board.
- With the rapid increase in demand for BGA packages, it is readily apparent that a need exists for cost effective printed wiring board substrates that are conducive to large scale automated assembly, that support existing automated assembly equipment, and that do not warp during the assembly process.
-
FIG. 1 illustrates a top view of an embodiment of a printed circuit board substrate for BGA assemblies according to the present invention; and -
FIG. 2 illustrates an enlarged cross-sectional side view of one BGA assembly according toFIG. 1 . - The present invention can be better understood with reference to the
FIGS. 1 and 2 .FIG. 1 illustrates a top view of multi-strand substrate, printed circuit board, or wiring board (PCB) 11. PCB 11 typically comprises an organic epoxy-glass resin based material, such as bismaleimide-triazin (BT) resin, FR-4 board, or the like. PCB 11 includes BGA substrates or patternedpackage substrates 12 arranged inN rows 14 andM columns 16 to form an N by M pattern or array. Each ofBGA substrates 12 includes a die attach orbonding pad 13, which typically comprises copper or gold plated copper. Dieattach pad 13 is a solid metallization area or a patterned metallization area shaped like a cross, “Union Jack”, or other specialized geometry. To avoid overcrowding the drawing, conductive traces are not shown (conductive traces are shown inFIG. 2 ). PCB 11 is formed using well known printed circuit board manufacturing techniques. - To support efficient large scale automated assembly, N and M are preferably at least greater than or equal to 2. Depending on the final dimensions of
BGA substrates 12, N and M are selected such that after all assembly steps are completed, each ofBGA substrates 12 exhibit a planarity variation of less than approximately 0.15 mm across each ofBGA substrates 12. In other words, during assembly, each ofBGA substrates 12 does not warp to a non-planar condition in excess of approximately 0.15 mm. Also, PCB 11 has a thickness 26 (shown inFIG. 2 ) sufficient to minimize warpage or non-planarity. As stated below,thickness 26 preferably is on an order of at least 0.5 mm. According to standard industry practice, warpage within a given unit is determined by measuring a maximum difference between a seating plane (formed by the three conductive solder balls (seeFIG. 2 ) having the greatest amount of standoff from the BGA substrate) and the conductive solder ball with the least amount of stand-off from the substrate. The warpage measurement is taken afterPCB 11 is separated into individual BGA units. - Preferably, PCB 11 further includes a plurality of stress-relief slots or
slots 19 at various locations on PCB 11. Preferably,slots 19 extend through PCB 11.Slots 19 are all the same size or of different sizes.Slots 19 further minimize warpage of each ofBGA substrates 12. Also, PCB 11 preferably includesalignment holes 21 along one side or both sides of PCB 11.Alignment holes 21 extend from the top surface to the lower surface ofPCB 11.Alignment holes 21 are placed according to the requirements of die attaching and wire bonding equipment to support automated assembly. Additionally, PCB 11 preferably includesholes 22 around the perimeter ofPCB 11 andhole 23 along one side of PCB 11.Holes 22 provide for an automatic orientation feature so that a manufacturer does not insert PCB 11 into assembly equipment backwards or reversed.Hole 23 provides for an orientation feature to allow a manufacturer to robotically placePCB 11 in a jig apparatus. - In a preferred embodiment for a 27 mm by 27 mm BGA device, N is equal to 2 and M is equal to 6 with PCB 11 having a
length 17 on an order of 187 mm and awidth 18 on an order of 63 mm. The above specifications also are preferred for a 23 mm by 23 mm and a 25 mm by 25 mm BGA device. In a preferred embodiment for a 9 mm by 9 mm BGA device, N is equal to 4 and M is equal to 12 withlength 17 on an order of 200 mm andwidth 18 on an order of 63 mm. In a preferred embodiment for a 10.4 mm by 10.4 mm BGA device, N is equal to 4 and M is equal to 12 withlength 17 on an order of 212 mm andwidth 18 on an order of 63 mm. In a preferred embodiment for a 15 mm by 15 mm BGA device, N is equal to 3 and M is equal to 9 withlength 17 on an order of 187 mm andwidth 18 on an order of 63 mm. In a preferred embodiment for a 14 mm by 22 mm BGA device, N is equal to 2 and M is equal to 9 withlength 17 on an order of 187 mm andwidth 18 on an order of 63 mm. Optionally, for a 14 mm by 22 mm BGA device, N is equal to 3 and M is equal 6 withlength 17 andwidth 18 the same as above. In a preferred embodiment for a 35 mm by 35 mm BGA device, N is equal to 1 and M is equal to 4 withlength 17 on an order of 187 mm andwidth 18 on an order of 63 mm. The above dimensions are preferred to take advantage of standard automatic assembly equipment requirements. This allows a manufacturer to use existing tooling and equipment. The above dimensions are easily modified to meet the requirements of different types of automated assembly equipment. -
FIG. 2 illustrates an enlarged cross-sectional view of one BGA structure, assembly, or package 25 after assembly but before singulation or separation into individual packages. BGA structure 25 comprises one ofBGA substrates 12 withinPCB 11.PCB 11 withBGA substrates 12 preferably has athickness 26 such thatPCB 11 can undergo magazine-to-magazine automated assembly processes without using a metal support pallet. Currently available single BGA substrate PCB's and single strand BGA substrates PCB's have thicknesses on the order of 0.35 mm, which is too flimsy for reliable automated assembly unless pallets or carriers are used.Thickness 26 also is selected to minimize planarity variation of each ofBGA substrates 12. Preferably,thickness 26 is greater than approximately 0.5 mm. Preferably,thickness 26 is in a range from approximately 0.5 mm to approximately 0.8 mm. - BGA structure 25 further includes a
semiconductor die 24 attached die attachpad 13 on an upper surface of each ofBGA substrates 12. Semiconductor die 24 has a plurality of bonding orbond pads 28. Each ofBGA substrates 12 has a conductive connective structure comprising bond posts 31, upper conductive traces 32, vias 33, lower conductive traces 36 andcontact pads 38.Conductive solder balls 41 are attached to contactpads 38. Conductive wires orwire bonds 43 electricallycouple bond pads 28 to bond posts 31. Alternatively, semiconductor die 24 is mounted in a “flip-chip” embodiment withbond pads 28 directly connected to bond posts directly belowbond pads 28, eliminatingconductive wires 43 and die attachpad 13. An encapsulating layer orencapsulant 46 covers semiconductor die 24 andwire bonds 43 to provide protection of active circuit elements from physical damage and/or corrosion. - A typical BGA assembly
process incorporating PCB 11 havingBGA substrates 12 to form BGA structure 25 is described as follows.First PCB 11 is provided having the desired N by M pattern.PCB 11 is loaded onto an automated die attach machine such as an ESEC 2006. This type of die attach machine is an industry standard machine that manufacturers use to attach semiconductor die to other types of semiconductor packages such as plastic dual-in-line (PDIP), small outline integrated circuit (SOIC), and QFP packages. The die attach machine automatically attaches one semiconductor die 24 to one of die attachpads 13 onPCB 11. Preferably, semiconductor die 24 is attached to one of die attachpads 13 using a die attach epoxy. - After die attach,
PCB 11 is then cleaned using an automated cleaning system such as an ULVAC cleaning system available from the ULVAC Corp. Next,PCB 11 is placed on an automated wire bonder such as a Shinkawa UTC-100 wherewire bonds 43 are attached tobond pads 22 and bond posts 31. In conventional BGA processing, wire bonding is done using a similar wirebonder configured for semi-automatic operation. - Next, encapsulant 46 is applied to cover semiconductor die 24 and
wire bonds 43.Encapsulant 46 comprises an organic material and is applied using an over-mold process or a glob-top process. For an over-mold process, automolds from Towa, Fico, or similar suppliers are used. When an over-molding process is used,encapsulant 46 preferably comprises an organic mold compound. When a glob-top process is used,encapsulant 46 preferably comprises an anhydride epoxy organic compound. Preferably, the material selected forencapsulant 46 has a thermal coefficients of expansion (TCE) close (within a few points or parts per million) to the TCE's of the material ofPCB 11 and semiconductor die 24. This further helps to minimize warpage ofBGA substrates 12 during the remainder of the assembly process. Such encapsulents are available from several suppliers including The Dexter Corp., of Industry, California, Ciba-Giegy Corp., Hitachi Corp., Sumitomo Corp., and Nitto-Denko Corp. - Next, encapsulant 46 is cured preferably using a belt furnace, vertical oven, or batch oven at a temperature that is function of the type of material used for
encapsulant 46. For the curing process, a tray or some other form of protection preferably is used to protectcontact pads 38 from foreign matter contamination. - After encapsulation,
conductive solder balls 41 are attached to contactpads 38 using a room temperature attach process. Next, an automated solder reflow process is used to reflowconductive solder balls 41. Automated reflow equipment such as a belt furnace. After reflow,PCB 11 is again cleaned using automated cleaning equipment with an aqueous or terpene media to remove any corrosive flux residues from the conductive solder ball attachment process. EachBGA structure 22 is then marked on an automated marking machine such as an automated laser marker. Optionally, marking occurs immediately following encapsulation. Finally each ofBGA substrates 12 is divided into individual packages. To divide the packages, a punch-press process is used. Optionally, a routing, dicing, or snapping separation process is used. - By now it should appreciated that there has been provided a multi-strand PCB containing an N by M array of BGA substrates for manufacturing BGA type semiconductor packages. N and M are selected and the thickness of the PCB is such so as to enable enhanced manufacturing efficiency. The enhanced manufacturing efficiency comes from the ability to manufacture more BGA packages from one multi-strand PCB and from the ability to use standard automated assembly equipment. Manufacturing efficiency is enhanced while still providing BGA substrate planarity variation less than approximately 0.15 mm. Because the multi-strand PCB according to the present invention enables the use of standard automated assembly equipment, a BGA manufacturer is able to use the same types of equipment to manufacture different types of packages thus reducing capital expenditures and needed factory floor space. Also, labor costs are reduced and quality is increased because of the reduced handling requirements.
Claims (24)
Priority Applications (1)
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US12/131,691 US20080289867A1 (en) | 1994-12-05 | 2008-06-02 | Multi-strand substrate for ball-grid array assemblies and method |
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US08/349,281 US6465743B1 (en) | 1994-12-05 | 1994-12-05 | Multi-strand substrate for ball-grid array assemblies and method |
US10/255,257 US6710265B2 (en) | 1994-12-05 | 2002-09-26 | Multi-strand substrate for ball-grid array assemblies and method |
US10/741,065 US7199306B2 (en) | 1994-12-05 | 2003-12-19 | Multi-strand substrate for ball-grid array assemblies and method |
US11/676,810 US7397001B2 (en) | 1994-12-05 | 2007-02-20 | Multi-strand substrate for ball-grid array assemblies and method |
US12/131,691 US20080289867A1 (en) | 1994-12-05 | 2008-06-02 | Multi-strand substrate for ball-grid array assemblies and method |
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US10/255,257 Expired - Fee Related US6710265B2 (en) | 1994-12-05 | 2002-09-26 | Multi-strand substrate for ball-grid array assemblies and method |
US10/741,065 Expired - Fee Related US7199306B2 (en) | 1994-12-05 | 2003-12-19 | Multi-strand substrate for ball-grid array assemblies and method |
US11/676,810 Expired - Fee Related US7397001B2 (en) | 1994-12-05 | 2007-02-20 | Multi-strand substrate for ball-grid array assemblies and method |
US12/131,691 Abandoned US20080289867A1 (en) | 1994-12-05 | 2008-06-02 | Multi-strand substrate for ball-grid array assemblies and method |
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US10/255,257 Expired - Fee Related US6710265B2 (en) | 1994-12-05 | 2002-09-26 | Multi-strand substrate for ball-grid array assemblies and method |
US10/741,065 Expired - Fee Related US7199306B2 (en) | 1994-12-05 | 2003-12-19 | Multi-strand substrate for ball-grid array assemblies and method |
US11/676,810 Expired - Fee Related US7397001B2 (en) | 1994-12-05 | 2007-02-20 | Multi-strand substrate for ball-grid array assemblies and method |
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US6931298B1 (en) | 2001-02-27 | 2005-08-16 | Cypress Semiconductor Corporation | Integrated back-end integrated circuit manufacturing assembly |
US6901984B1 (en) | 2001-02-27 | 2005-06-07 | Cypress Semiconductor Corporation | Method and system for controlling the processing of an integrated circuit chip assembly line using a central computer system and a common communication protocol |
JP4626919B2 (en) * | 2001-03-27 | 2011-02-09 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
US20020170897A1 (en) * | 2001-05-21 | 2002-11-21 | Hall Frank L. | Methods for preparing ball grid array substrates via use of a laser |
US7276802B2 (en) * | 2002-04-15 | 2007-10-02 | Micron Technology, Inc. | Semiconductor integrated circuit package having electrically disconnected solder balls for mounting |
JP4283514B2 (en) | 2002-09-24 | 2009-06-24 | 株式会社日立製作所 | Electronic circuit equipment |
TW575931B (en) * | 2002-10-07 | 2004-02-11 | Advanced Semiconductor Eng | Bridge connection type of chip package and process thereof |
JP4079874B2 (en) * | 2003-12-25 | 2008-04-23 | 沖電気工業株式会社 | Manufacturing method of semiconductor device |
DE102004015091B4 (en) * | 2004-03-25 | 2006-05-04 | Infineon Technologies Ag | Areal wiring carrier |
US7105377B1 (en) * | 2004-04-13 | 2006-09-12 | Cypress Semiconductor Corporation | Method and system for universal packaging in conjunction with a back-end integrated circuit manufacturing process |
DE602005011017D1 (en) * | 2004-07-07 | 2008-12-24 | Promerus Llc | LENS-SENSITIVE DIELECTRIC RESIN COMPOSITIONS AND ITS USES |
US7223923B2 (en) * | 2004-10-26 | 2007-05-29 | Hannstar Display Corporation | PCB capable of releasing thermal stress |
US20090008792A1 (en) * | 2004-11-19 | 2009-01-08 | Industrial Technology Research Institute | Three-dimensional chip-stack package and active component on a substrate |
TWI256694B (en) * | 2004-11-19 | 2006-06-11 | Ind Tech Res Inst | Structure with embedded active components and manufacturing method thereof |
US7148560B2 (en) * | 2005-01-25 | 2006-12-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | IC chip package structure and underfill process |
US7656172B2 (en) | 2005-01-31 | 2010-02-02 | Cascade Microtech, Inc. | System for testing semiconductors |
JP2006278610A (en) * | 2005-03-29 | 2006-10-12 | Sanyo Electric Co Ltd | Semiconductor device and manufacturing method thereof |
US7521781B2 (en) * | 2005-04-25 | 2009-04-21 | Stats Chippac Ltd. | Integrated circuit package system with mold clamp line critical area having widened conductive traces |
KR100695065B1 (en) | 2006-03-27 | 2007-03-14 | 삼성전기주식회사 | Coupon for measuring flatness of surface of substrate and measuring method thereof |
US20070253179A1 (en) * | 2006-04-27 | 2007-11-01 | Briggs Randall D | Method and apparatus for removing surface mount device from printed circuit board |
KR100728989B1 (en) | 2006-06-30 | 2007-06-15 | 주식회사 하이닉스반도체 | Substrate for fbga package fabrication |
WO2008046188A1 (en) * | 2006-10-10 | 2008-04-24 | Tir Technology Lp | Circuit board with regional flexibility |
JP5194471B2 (en) * | 2007-02-06 | 2013-05-08 | パナソニック株式会社 | Semiconductor device |
JP5223571B2 (en) * | 2008-09-30 | 2013-06-26 | 富士通株式会社 | Semiconductor device, substrate design method, substrate design apparatus |
TWI428995B (en) * | 2008-10-20 | 2014-03-01 | United Test & Assembly Ct Lt | Shrink package on board |
US8159830B2 (en) * | 2009-04-17 | 2012-04-17 | Atmel Corporation | Surface mounting chip carrier module |
TWI430717B (en) * | 2011-07-15 | 2014-03-11 | Lite On Electronics Guangzhou | Substrate strcuture, array of semiconductor devices and semiconductor device thereof |
US9099363B1 (en) | 2014-02-12 | 2015-08-04 | Freescale Semiconductor, Inc. | Substrate with corner cut-outs and semiconductor device assembled therewith |
US20180130768A1 (en) * | 2016-11-09 | 2018-05-10 | Unisem (M) Berhad | Substrate Based Fan-Out Wafer Level Packaging |
US20190259731A1 (en) * | 2016-11-09 | 2019-08-22 | Unisem (M) Berhad | Substrate based fan-out wafer level packaging |
US10880995B2 (en) * | 2017-12-15 | 2020-12-29 | 2449049 Ontario Inc. | Printed circuit board with stress relief zones for component and solder joint protection |
CN111465312A (en) * | 2020-04-14 | 2020-07-28 | 杭州洛微科技有限公司 | Photoelectric product packaging production method based on periodic array arrangement |
US20220254763A1 (en) * | 2021-02-09 | 2022-08-11 | Innolux Corporation | Electronic device |
US20230126272A1 (en) * | 2021-10-25 | 2023-04-27 | Nanya Technology Corporation | Semiconductor device with interface structure |
Citations (87)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3413713A (en) * | 1965-06-18 | 1968-12-03 | Motorola Inc | Plastic encapsulated transistor and method of making same |
US3444441A (en) * | 1965-06-18 | 1969-05-13 | Motorola Inc | Semiconductor devices including lead and plastic housing structure suitable for automated process construction |
US3606673A (en) * | 1968-08-15 | 1971-09-21 | Texas Instruments Inc | Plastic encapsulated semiconductor devices |
US3913217A (en) * | 1972-08-09 | 1975-10-21 | Hitachi Ltd | Method of producing a semiconductor device |
US4508758A (en) * | 1982-12-27 | 1985-04-02 | At&T Technologies, Inc. | Encapsulated electronic circuit |
US4518631A (en) * | 1983-11-14 | 1985-05-21 | Dow Corning Corporation | Thixotropic curable coating compositions |
US4530152A (en) * | 1982-04-01 | 1985-07-23 | Compagnie Industrielle Des Telecommunications Cit-Alcatel | Method for encapsulating semiconductor components using temporary substrates |
US4595647A (en) * | 1985-02-01 | 1986-06-17 | Motorola, Inc. | Method for encapsulating and marking electronic devices |
JPS61222151A (en) * | 1985-03-27 | 1986-10-02 | Ibiden Co Ltd | Manufacture of printed wiring substrate for mounting semiconductor |
US4654290A (en) * | 1985-02-01 | 1987-03-31 | Motorola, Inc. | Laser markable molding compound, method of use and device therefrom |
US4674811A (en) * | 1986-07-10 | 1987-06-23 | Honeywell Inc. | Apparatus for connecting pin grid array devices to printed wiring boards |
US4703984A (en) * | 1985-10-28 | 1987-11-03 | Burroughs Corporation | Flexible access connector with miniature slotted pads |
US4734820A (en) * | 1987-04-16 | 1988-03-29 | Ncr Corporation | Cryogenic packaging scheme |
US4737395A (en) * | 1983-11-29 | 1988-04-12 | Ibiden Co. Ltd. | Printed wiring board for mounting electronic parts and process for producing the same |
US4808990A (en) * | 1983-11-11 | 1989-02-28 | Sharp Kabushiki Kaisha | Liquid crystal display assembly |
US4809990A (en) * | 1985-07-31 | 1989-03-07 | Motoren Und Turbinen Union Munchen Gmbh | Brush seals of ceramic material for thermal turbomachines |
US4821007A (en) * | 1987-02-06 | 1989-04-11 | Tektronix, Inc. | Strip line circuit component and method of manufacture |
US4866841A (en) * | 1987-09-16 | 1989-09-19 | Advanced Semiconductor Packages Ltd. | Integrated circuit chip carrier |
US4870474A (en) * | 1986-12-12 | 1989-09-26 | Texas Instruments Incorporated | Lead frame |
US4871317A (en) * | 1987-12-02 | 1989-10-03 | A. O. Smith Corporation | Surface mounted component adaptor for interconnecting of surface mounted circuit components |
US4887352A (en) * | 1986-12-31 | 1989-12-19 | Texas Instruments Incorporated | Method for making matrix lead frame |
US4890383A (en) * | 1988-01-15 | 1990-01-02 | Simens Corporate Research & Support, Inc. | Method for producing displays and modular components |
US4920074A (en) * | 1987-02-25 | 1990-04-24 | Hitachi, Ltd. | Surface mount plastic package semiconductor integrated circuit, manufacturing method thereof, as well as mounting method and mounted structure thereof |
US4930216A (en) * | 1989-03-10 | 1990-06-05 | Microelectronics And Computer Technology Corporation | Process for preparing integrated circuit dies for mounting |
US4961821A (en) * | 1989-11-22 | 1990-10-09 | Xerox Corporation | Ode through holes and butt edges without edge dicing |
US4994936A (en) * | 1990-02-12 | 1991-02-19 | Rogers Corporation | Molded integrated circuit package incorporating decoupling capacitor |
US4999700A (en) * | 1989-04-20 | 1991-03-12 | Honeywell Inc. | Package to board variable pitch tab |
US5000689A (en) * | 1989-01-30 | 1991-03-19 | Japan Aviation Electronics Industry, Ltd. | Connector for integrated circuit packages |
US5006673A (en) * | 1989-12-07 | 1991-04-09 | Motorola, Inc. | Fabrication of pad array carriers from a universal interconnect structure |
US5061657A (en) * | 1990-07-18 | 1991-10-29 | The United States Of America As Represented By The Secretary Of The Navy | Method of making integrated circuit to package electrical connections after encapsulation with an organic polymer |
US5071375A (en) * | 1990-01-22 | 1991-12-10 | Savage John Jun | Electrical contact and multiple contact assembly |
US5136366A (en) * | 1990-11-05 | 1992-08-04 | Motorola, Inc. | Overmolded semiconductor package with anchoring means |
US5148266A (en) * | 1990-09-24 | 1992-09-15 | Ist Associates, Inc. | Semiconductor chip assemblies having interposer and flexible lead |
US5148265A (en) * | 1990-09-24 | 1992-09-15 | Ist Associates, Inc. | Semiconductor chip assemblies with fan-in leads |
US5153385A (en) * | 1991-03-18 | 1992-10-06 | Motorola, Inc. | Transfer molded semiconductor package with improved adhesion |
US5164817A (en) * | 1991-08-14 | 1992-11-17 | Vlsi Technology, Inc. | Distributed clock tree scheme in semiconductor packages |
US5172214A (en) * | 1991-02-06 | 1992-12-15 | Motorola, Inc. | Leadless semiconductor device and method for making the same |
US5188984A (en) * | 1987-04-21 | 1993-02-23 | Sumitomo Electric Industries, Ltd. | Semiconductor device and production method thereof |
US5216278A (en) * | 1990-12-04 | 1993-06-01 | Motorola, Inc. | Semiconductor device having a pad array carrier package |
US5239198A (en) * | 1989-09-06 | 1993-08-24 | Motorola, Inc. | Overmolded semiconductor device having solder ball and edge lead connective structure |
US5248903A (en) * | 1992-09-18 | 1993-09-28 | Lsi Logic Corporation | Composite bond pads for semiconductor devices |
US5251107A (en) * | 1990-11-28 | 1993-10-05 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor package |
US5261962A (en) * | 1991-06-05 | 1993-11-16 | Mitsubishi Jukogyo Kabushiki Kaisha | Plasma-chemical vapor-phase epitaxy system comprising a planar antenna |
US5280193A (en) * | 1992-05-04 | 1994-01-18 | Lin Paul T | Repairable semiconductor multi-package module having individualized package bodies on a PC board substrate |
US5316965A (en) * | 1993-07-29 | 1994-05-31 | Digital Equipment Corporation | Method of decreasing the field oxide etch rate in isolation technology |
US5334857A (en) * | 1992-04-06 | 1994-08-02 | Motorola, Inc. | Semiconductor device with test-only contacts and method for making the same |
US5336931A (en) * | 1993-09-03 | 1994-08-09 | Motorola, Inc. | Anchoring method for flow formed integrated circuit covers |
US5338972A (en) * | 1992-08-10 | 1994-08-16 | Rohm Co., Ltd. | Lead frame with deformable buffer portions |
US5341039A (en) * | 1991-04-19 | 1994-08-23 | Mitsubishi Denki Kabushiki Kaisha | High frequency integrated circuit device including a circuit for decreasing reflected signals in wiring formed on a semiconductor substrate |
US5346118A (en) * | 1993-09-28 | 1994-09-13 | At&T Bell Laboratories | Surface mount solder assembly of leadless integrated circuit packages to substrates |
US5355283A (en) * | 1993-04-14 | 1994-10-11 | Amkor Electronics, Inc. | Ball grid array with via interconnection |
US5371404A (en) * | 1993-02-04 | 1994-12-06 | Motorola, Inc. | Thermally conductive integrated circuit package with radio frequency shielding |
US5433822A (en) * | 1991-04-26 | 1995-07-18 | Citizen Watch Co., Ltd. | Method of manufacturing semiconductor device with copper core bumps |
US5436203A (en) * | 1994-07-05 | 1995-07-25 | Motorola, Inc. | Shielded liquid encapsulated semiconductor device and method for making the same |
US5435482A (en) * | 1994-02-04 | 1995-07-25 | Lsi Logic Corporation | Integrated circuit having a coplanar solder ball contact array |
US5446625A (en) * | 1993-11-10 | 1995-08-29 | Motorola, Inc. | Chip carrier having copper pattern plated with gold on one surface and devoid of gold on another surface |
US5450283A (en) * | 1992-11-03 | 1995-09-12 | Motorola, Inc. | Thermally enhanced semiconductor device having exposed backside and method for making the same |
US5462636A (en) * | 1993-12-28 | 1995-10-31 | International Business Machines Corporation | Method for chemically scribing wafers |
US5467252A (en) * | 1993-10-18 | 1995-11-14 | Motorola, Inc. | Method for plating using nested plating buses and semiconductor device having the same |
US5467253A (en) * | 1994-06-30 | 1995-11-14 | Motorola, Inc. | Semiconductor chip package and method of forming |
US5468999A (en) * | 1994-05-26 | 1995-11-21 | Motorola, Inc. | Liquid encapsulated ball grid array semiconductor device with fine pitch wire bonding |
US5471368A (en) * | 1993-11-16 | 1995-11-28 | International Business Machines Corporation | Module having vertical peripheral edge connection |
US5491111A (en) * | 1994-10-26 | 1996-02-13 | Tai; George | Method of making a semiconductor diode |
US5497033A (en) * | 1993-02-08 | 1996-03-05 | Martin Marietta Corporation | Embedded substrate for integrated circuit modules |
US5525834A (en) * | 1994-10-17 | 1996-06-11 | W. L. Gore & Associates, Inc. | Integrated circuit package |
US5535101A (en) * | 1992-11-03 | 1996-07-09 | Motorola, Inc. | Leadless integrated circuit package |
US5541450A (en) * | 1994-11-02 | 1996-07-30 | Motorola, Inc. | Low-profile ball-grid array semiconductor package |
US5592025A (en) * | 1992-08-06 | 1997-01-07 | Motorola, Inc. | Pad array semiconductor device |
US5593926A (en) * | 1993-10-12 | 1997-01-14 | Sumitomo Electric Industries, Ltd. | Method of manufacturing semiconductor device |
US5604160A (en) * | 1996-07-29 | 1997-02-18 | Motorola, Inc. | Method for packaging semiconductor devices |
US5612576A (en) * | 1992-10-13 | 1997-03-18 | Motorola | Self-opening vent hole in an overmolded semiconductor device |
US5612513A (en) * | 1995-09-19 | 1997-03-18 | Micron Communications, Inc. | Article and method of manufacturing an enclosed electrical circuit using an encapsulant |
US5635671A (en) * | 1994-03-16 | 1997-06-03 | Amkor Electronics, Inc. | Mold runner removal from a substrate-based packaged electronic device |
US5641714A (en) * | 1995-01-17 | 1997-06-24 | Sony Corporation | Method of manufacturing members |
US5652185A (en) * | 1995-04-07 | 1997-07-29 | National Semiconductor Corporation | Maximized substrate design for grid array based assemblies |
US5679977A (en) * | 1990-09-24 | 1997-10-21 | Tessera, Inc. | Semiconductor chip assemblies, methods of making same and components for same |
US5690773A (en) * | 1994-02-24 | 1997-11-25 | Gemplus Card International | Method for the manufacture of a contact-free or hybrid card |
US5700981A (en) * | 1996-02-08 | 1997-12-23 | Micron Communications, Inc. | Encapsulated electronic component and method for encapsulating an electronic component |
US5729437A (en) * | 1994-06-22 | 1998-03-17 | Seiko Epson Corporation | Electronic part including a thin body of molding resin |
US5729894A (en) * | 1992-07-21 | 1998-03-24 | Lsi Logic Corporation | Method of assembling ball bump grid array semiconductor packages |
US5776798A (en) * | 1996-09-04 | 1998-07-07 | Motorola, Inc. | Semiconductor package and method thereof |
US5926696A (en) * | 1994-01-12 | 1999-07-20 | Lucent Technologies Inc. | Ball grid array plastic package |
US5976912A (en) * | 1994-03-18 | 1999-11-02 | Hitachi Chemical Company, Ltd. | Fabrication process of semiconductor package and semiconductor package |
US5981314A (en) * | 1996-10-31 | 1999-11-09 | Amkor Technology, Inc. | Near chip size integrated circuit package |
US6302101B1 (en) * | 1999-12-14 | 2001-10-16 | Daniel Py | System and method for application of medicament into the nasal passage |
US6465743B1 (en) * | 1994-12-05 | 2002-10-15 | Motorola, Inc. | Multi-strand substrate for ball-grid array assemblies and method |
US6607943B1 (en) * | 1998-02-24 | 2003-08-19 | Micron Technology, Inc. | Low profile ball grid array package |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US500689A (en) * | 1893-07-04 | Lifting-jack | ||
EP0261324A1 (en) | 1986-09-26 | 1988-03-30 | Texas Instruments Incorporated | Plastic package for large chip size integrated circuit |
JPH0247855A (en) | 1988-08-10 | 1990-02-16 | Nec Corp | Semiconductor device |
JPH02301155A (en) | 1989-05-16 | 1990-12-13 | Citizen Watch Co Ltd | Method of fixing ic module |
JP2967215B2 (en) | 1990-10-12 | 1999-10-25 | 株式会社村田製作所 | Manufacturing method of chip-type electronic components |
JP2564707B2 (en) * | 1991-01-09 | 1996-12-18 | ローム株式会社 | Multi-type molding method and molding apparatus for molding part in lead frame for electronic component |
JPH04254363A (en) | 1991-02-06 | 1992-09-09 | Hitachi Ltd | Lead frame and semiconductor integrated circuit device utilizing the same |
KR940003560B1 (en) | 1991-05-11 | 1994-04-23 | 금성일렉트론 주식회사 | Multi-layer semiconductor package and making method |
JPH05190737A (en) | 1992-01-13 | 1993-07-30 | Ngk Insulators Ltd | Leadframe |
JPH05315515A (en) | 1992-05-07 | 1993-11-26 | Nec Corp | Semiconductor device |
JP2617402B2 (en) | 1992-06-10 | 1997-06-04 | オリジン電気株式会社 | Semiconductor device, electronic circuit device, and manufacturing method thereof |
JPH06132423A (en) | 1992-10-19 | 1994-05-13 | Sharp Corp | Manufacture of semiconductor device |
JPH06169051A (en) | 1992-11-27 | 1994-06-14 | Sumitomo Special Metals Co Ltd | Lead frame and manufacture thereof and semiconductor package |
US5363075A (en) | 1992-12-03 | 1994-11-08 | Hughes Aircraft Company | Multiple layer microwave integrated circuit module connector assembly |
JPH06216179A (en) | 1993-01-21 | 1994-08-05 | Hitachi Ltd | Manufacture for semiconductor device and lead frame and transfer molding die used in the manufacture |
-
1994
- 1994-12-05 US US08/349,281 patent/US6465743B1/en not_active Expired - Lifetime
-
1995
- 1995-10-19 TW TW084111039A patent/TW280019B/zh not_active IP Right Cessation
- 1995-10-31 KR KR1019950038366A patent/KR100400949B1/en active IP Right Grant
- 1995-11-22 JP JP32627795A patent/JP3493088B2/en not_active Expired - Lifetime
- 1995-11-24 MY MYPI95003612A patent/MY119990A/en unknown
- 1995-11-27 CN CNB951202707A patent/CN1155080C/en not_active Expired - Lifetime
-
2002
- 2002-09-26 US US10/255,257 patent/US6710265B2/en not_active Expired - Fee Related
-
2003
- 2003-12-19 US US10/741,065 patent/US7199306B2/en not_active Expired - Fee Related
-
2007
- 2007-02-20 US US11/676,810 patent/US7397001B2/en not_active Expired - Fee Related
-
2008
- 2008-06-02 US US12/131,691 patent/US20080289867A1/en not_active Abandoned
Patent Citations (97)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3444441A (en) * | 1965-06-18 | 1969-05-13 | Motorola Inc | Semiconductor devices including lead and plastic housing structure suitable for automated process construction |
US3413713A (en) * | 1965-06-18 | 1968-12-03 | Motorola Inc | Plastic encapsulated transistor and method of making same |
US3606673A (en) * | 1968-08-15 | 1971-09-21 | Texas Instruments Inc | Plastic encapsulated semiconductor devices |
US3913217A (en) * | 1972-08-09 | 1975-10-21 | Hitachi Ltd | Method of producing a semiconductor device |
US4530152A (en) * | 1982-04-01 | 1985-07-23 | Compagnie Industrielle Des Telecommunications Cit-Alcatel | Method for encapsulating semiconductor components using temporary substrates |
US4508758A (en) * | 1982-12-27 | 1985-04-02 | At&T Technologies, Inc. | Encapsulated electronic circuit |
US4808990A (en) * | 1983-11-11 | 1989-02-28 | Sharp Kabushiki Kaisha | Liquid crystal display assembly |
US4518631A (en) * | 1983-11-14 | 1985-05-21 | Dow Corning Corporation | Thixotropic curable coating compositions |
US4737395A (en) * | 1983-11-29 | 1988-04-12 | Ibiden Co. Ltd. | Printed wiring board for mounting electronic parts and process for producing the same |
US4773955A (en) * | 1983-11-29 | 1988-09-27 | Ibiden Co. Ltd. | Printed wiring board for mounting electronic parts and process for producing the same |
US4595647A (en) * | 1985-02-01 | 1986-06-17 | Motorola, Inc. | Method for encapsulating and marking electronic devices |
US4654290A (en) * | 1985-02-01 | 1987-03-31 | Motorola, Inc. | Laser markable molding compound, method of use and device therefrom |
JPS61222151A (en) * | 1985-03-27 | 1986-10-02 | Ibiden Co Ltd | Manufacture of printed wiring substrate for mounting semiconductor |
US4809990A (en) * | 1985-07-31 | 1989-03-07 | Motoren Und Turbinen Union Munchen Gmbh | Brush seals of ceramic material for thermal turbomachines |
US4703984A (en) * | 1985-10-28 | 1987-11-03 | Burroughs Corporation | Flexible access connector with miniature slotted pads |
US4674811A (en) * | 1986-07-10 | 1987-06-23 | Honeywell Inc. | Apparatus for connecting pin grid array devices to printed wiring boards |
US4870474A (en) * | 1986-12-12 | 1989-09-26 | Texas Instruments Incorporated | Lead frame |
US4887352A (en) * | 1986-12-31 | 1989-12-19 | Texas Instruments Incorporated | Method for making matrix lead frame |
US4821007A (en) * | 1987-02-06 | 1989-04-11 | Tektronix, Inc. | Strip line circuit component and method of manufacture |
US4920074A (en) * | 1987-02-25 | 1990-04-24 | Hitachi, Ltd. | Surface mount plastic package semiconductor integrated circuit, manufacturing method thereof, as well as mounting method and mounted structure thereof |
US4734820A (en) * | 1987-04-16 | 1988-03-29 | Ncr Corporation | Cryogenic packaging scheme |
US5188984A (en) * | 1987-04-21 | 1993-02-23 | Sumitomo Electric Industries, Ltd. | Semiconductor device and production method thereof |
US4866841A (en) * | 1987-09-16 | 1989-09-19 | Advanced Semiconductor Packages Ltd. | Integrated circuit chip carrier |
US4871317A (en) * | 1987-12-02 | 1989-10-03 | A. O. Smith Corporation | Surface mounted component adaptor for interconnecting of surface mounted circuit components |
US4890383A (en) * | 1988-01-15 | 1990-01-02 | Simens Corporate Research & Support, Inc. | Method for producing displays and modular components |
US5000689A (en) * | 1989-01-30 | 1991-03-19 | Japan Aviation Electronics Industry, Ltd. | Connector for integrated circuit packages |
US4930216A (en) * | 1989-03-10 | 1990-06-05 | Microelectronics And Computer Technology Corporation | Process for preparing integrated circuit dies for mounting |
US4999700A (en) * | 1989-04-20 | 1991-03-12 | Honeywell Inc. | Package to board variable pitch tab |
US5239198A (en) * | 1989-09-06 | 1993-08-24 | Motorola, Inc. | Overmolded semiconductor device having solder ball and edge lead connective structure |
US4961821A (en) * | 1989-11-22 | 1990-10-09 | Xerox Corporation | Ode through holes and butt edges without edge dicing |
US5006673A (en) * | 1989-12-07 | 1991-04-09 | Motorola, Inc. | Fabrication of pad array carriers from a universal interconnect structure |
US5071375A (en) * | 1990-01-22 | 1991-12-10 | Savage John Jun | Electrical contact and multiple contact assembly |
US4994936A (en) * | 1990-02-12 | 1991-02-19 | Rogers Corporation | Molded integrated circuit package incorporating decoupling capacitor |
US5061657A (en) * | 1990-07-18 | 1991-10-29 | The United States Of America As Represented By The Secretary Of The Navy | Method of making integrated circuit to package electrical connections after encapsulation with an organic polymer |
US5685885A (en) * | 1990-09-24 | 1997-11-11 | Tessera, Inc. | Wafer-scale techniques for fabrication of semiconductor chip assemblies |
US5347159A (en) * | 1990-09-24 | 1994-09-13 | Tessera, Inc. | Semiconductor chip assemblies with face-up mounting and rear-surface connection to substrate |
US5679977A (en) * | 1990-09-24 | 1997-10-21 | Tessera, Inc. | Semiconductor chip assemblies, methods of making same and components for same |
US5148265A (en) * | 1990-09-24 | 1992-09-15 | Ist Associates, Inc. | Semiconductor chip assemblies with fan-in leads |
US5148266A (en) * | 1990-09-24 | 1992-09-15 | Ist Associates, Inc. | Semiconductor chip assemblies having interposer and flexible lead |
US5848467A (en) * | 1990-09-24 | 1998-12-15 | Tessera, Inc. | Methods of making semiconductor chip assemblies |
US5136366A (en) * | 1990-11-05 | 1992-08-04 | Motorola, Inc. | Overmolded semiconductor package with anchoring means |
US5251107A (en) * | 1990-11-28 | 1993-10-05 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor package |
US5216278A (en) * | 1990-12-04 | 1993-06-01 | Motorola, Inc. | Semiconductor device having a pad array carrier package |
US5172214A (en) * | 1991-02-06 | 1992-12-15 | Motorola, Inc. | Leadless semiconductor device and method for making the same |
US5153385A (en) * | 1991-03-18 | 1992-10-06 | Motorola, Inc. | Transfer molded semiconductor package with improved adhesion |
US5341039A (en) * | 1991-04-19 | 1994-08-23 | Mitsubishi Denki Kabushiki Kaisha | High frequency integrated circuit device including a circuit for decreasing reflected signals in wiring formed on a semiconductor substrate |
US5433822A (en) * | 1991-04-26 | 1995-07-18 | Citizen Watch Co., Ltd. | Method of manufacturing semiconductor device with copper core bumps |
US5261962A (en) * | 1991-06-05 | 1993-11-16 | Mitsubishi Jukogyo Kabushiki Kaisha | Plasma-chemical vapor-phase epitaxy system comprising a planar antenna |
US5164817A (en) * | 1991-08-14 | 1992-11-17 | Vlsi Technology, Inc. | Distributed clock tree scheme in semiconductor packages |
US5334857A (en) * | 1992-04-06 | 1994-08-02 | Motorola, Inc. | Semiconductor device with test-only contacts and method for making the same |
US5280193A (en) * | 1992-05-04 | 1994-01-18 | Lin Paul T | Repairable semiconductor multi-package module having individualized package bodies on a PC board substrate |
US5729894A (en) * | 1992-07-21 | 1998-03-24 | Lsi Logic Corporation | Method of assembling ball bump grid array semiconductor packages |
US5592025A (en) * | 1992-08-06 | 1997-01-07 | Motorola, Inc. | Pad array semiconductor device |
US5338972A (en) * | 1992-08-10 | 1994-08-16 | Rohm Co., Ltd. | Lead frame with deformable buffer portions |
US5248903A (en) * | 1992-09-18 | 1993-09-28 | Lsi Logic Corporation | Composite bond pads for semiconductor devices |
US5612576A (en) * | 1992-10-13 | 1997-03-18 | Motorola | Self-opening vent hole in an overmolded semiconductor device |
US5450283A (en) * | 1992-11-03 | 1995-09-12 | Motorola, Inc. | Thermally enhanced semiconductor device having exposed backside and method for making the same |
US5535101A (en) * | 1992-11-03 | 1996-07-09 | Motorola, Inc. | Leadless integrated circuit package |
US5371404A (en) * | 1993-02-04 | 1994-12-06 | Motorola, Inc. | Thermally conductive integrated circuit package with radio frequency shielding |
US5497033A (en) * | 1993-02-08 | 1996-03-05 | Martin Marietta Corporation | Embedded substrate for integrated circuit modules |
US5355283A (en) * | 1993-04-14 | 1994-10-11 | Amkor Electronics, Inc. | Ball grid array with via interconnection |
US5316965A (en) * | 1993-07-29 | 1994-05-31 | Digital Equipment Corporation | Method of decreasing the field oxide etch rate in isolation technology |
US5336931A (en) * | 1993-09-03 | 1994-08-09 | Motorola, Inc. | Anchoring method for flow formed integrated circuit covers |
US5346118A (en) * | 1993-09-28 | 1994-09-13 | At&T Bell Laboratories | Surface mount solder assembly of leadless integrated circuit packages to substrates |
US5593926A (en) * | 1993-10-12 | 1997-01-14 | Sumitomo Electric Industries, Ltd. | Method of manufacturing semiconductor device |
US5467252A (en) * | 1993-10-18 | 1995-11-14 | Motorola, Inc. | Method for plating using nested plating buses and semiconductor device having the same |
US5446625A (en) * | 1993-11-10 | 1995-08-29 | Motorola, Inc. | Chip carrier having copper pattern plated with gold on one surface and devoid of gold on another surface |
US5570505A (en) * | 1993-11-16 | 1996-11-05 | International Business Machines Corporation | Method of manufacturing a circuit module |
US5471368A (en) * | 1993-11-16 | 1995-11-28 | International Business Machines Corporation | Module having vertical peripheral edge connection |
US5462636A (en) * | 1993-12-28 | 1995-10-31 | International Business Machines Corporation | Method for chemically scribing wafers |
US5926696A (en) * | 1994-01-12 | 1999-07-20 | Lucent Technologies Inc. | Ball grid array plastic package |
US5745986A (en) * | 1994-02-04 | 1998-05-05 | Lsi Logic Corporation | Method of planarizing an array of plastically deformable contacts on an integrated circuit package to compensate for surface warpage |
US5989937A (en) * | 1994-02-04 | 1999-11-23 | Lsi Logic Corporation | Method for compensating for bottom warpage of a BGA integrated circuit |
US5435482A (en) * | 1994-02-04 | 1995-07-25 | Lsi Logic Corporation | Integrated circuit having a coplanar solder ball contact array |
US5690773A (en) * | 1994-02-24 | 1997-11-25 | Gemplus Card International | Method for the manufacture of a contact-free or hybrid card |
US5635671A (en) * | 1994-03-16 | 1997-06-03 | Amkor Electronics, Inc. | Mold runner removal from a substrate-based packaged electronic device |
US6365432B1 (en) * | 1994-03-18 | 2002-04-02 | Hitachi Chemical Company, Ltd. | Fabrication process of semiconductor package and semiconductor package |
US5976912A (en) * | 1994-03-18 | 1999-11-02 | Hitachi Chemical Company, Ltd. | Fabrication process of semiconductor package and semiconductor package |
US5468999A (en) * | 1994-05-26 | 1995-11-21 | Motorola, Inc. | Liquid encapsulated ball grid array semiconductor device with fine pitch wire bonding |
US5729437A (en) * | 1994-06-22 | 1998-03-17 | Seiko Epson Corporation | Electronic part including a thin body of molding resin |
US5467253A (en) * | 1994-06-30 | 1995-11-14 | Motorola, Inc. | Semiconductor chip package and method of forming |
US5436203A (en) * | 1994-07-05 | 1995-07-25 | Motorola, Inc. | Shielded liquid encapsulated semiconductor device and method for making the same |
US5525834A (en) * | 1994-10-17 | 1996-06-11 | W. L. Gore & Associates, Inc. | Integrated circuit package |
US5491111A (en) * | 1994-10-26 | 1996-02-13 | Tai; George | Method of making a semiconductor diode |
US5541450A (en) * | 1994-11-02 | 1996-07-30 | Motorola, Inc. | Low-profile ball-grid array semiconductor package |
US5639695A (en) * | 1994-11-02 | 1997-06-17 | Motorola, Inc. | Low-profile ball-grid array semiconductor package and method |
US6465743B1 (en) * | 1994-12-05 | 2002-10-15 | Motorola, Inc. | Multi-strand substrate for ball-grid array assemblies and method |
US5641714A (en) * | 1995-01-17 | 1997-06-24 | Sony Corporation | Method of manufacturing members |
US5652185A (en) * | 1995-04-07 | 1997-07-29 | National Semiconductor Corporation | Maximized substrate design for grid array based assemblies |
US5612513A (en) * | 1995-09-19 | 1997-03-18 | Micron Communications, Inc. | Article and method of manufacturing an enclosed electrical circuit using an encapsulant |
US5700981A (en) * | 1996-02-08 | 1997-12-23 | Micron Communications, Inc. | Encapsulated electronic component and method for encapsulating an electronic component |
US5973263A (en) * | 1996-02-08 | 1999-10-26 | Micron Communications, Inc. | Encapsulated electronic component and method for encapsulating an electronic component |
US5604160A (en) * | 1996-07-29 | 1997-02-18 | Motorola, Inc. | Method for packaging semiconductor devices |
US5776798A (en) * | 1996-09-04 | 1998-07-07 | Motorola, Inc. | Semiconductor package and method thereof |
US5981314A (en) * | 1996-10-31 | 1999-11-09 | Amkor Technology, Inc. | Near chip size integrated circuit package |
US6607943B1 (en) * | 1998-02-24 | 2003-08-19 | Micron Technology, Inc. | Low profile ball grid array package |
US6302101B1 (en) * | 1999-12-14 | 2001-10-16 | Daniel Py | System and method for application of medicament into the nasal passage |
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Also Published As
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MY119990A (en) | 2005-08-30 |
US7397001B2 (en) | 2008-07-08 |
KR100400949B1 (en) | 2003-12-06 |
JPH08222654A (en) | 1996-08-30 |
US20040129452A1 (en) | 2004-07-08 |
JP3493088B2 (en) | 2004-02-03 |
CN1155080C (en) | 2004-06-23 |
US6710265B2 (en) | 2004-03-23 |
US6465743B1 (en) | 2002-10-15 |
KR960026504A (en) | 1996-07-22 |
CN1132462A (en) | 1996-10-02 |
TW280019B (en) | 1996-07-01 |
US20070137889A1 (en) | 2007-06-21 |
US20030027377A1 (en) | 2003-02-06 |
US7199306B2 (en) | 2007-04-03 |
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