|Publication number||US20080315982 A1|
|Application number||US 12/136,018|
|Publication date||Dec 25, 2008|
|Filing date||Jun 9, 2008|
|Priority date||Jun 8, 2007|
|Also published as||US8179116, US8570009, US20080303495, US20080309299|
|Publication number||12136018, 136018, US 2008/0315982 A1, US 2008/315982 A1, US 20080315982 A1, US 20080315982A1, US 2008315982 A1, US 2008315982A1, US-A1-20080315982, US-A1-2008315982, US2008/0315982A1, US2008/315982A1, US20080315982 A1, US20080315982A1, US2008315982 A1, US2008315982A1|
|Inventors||Jia Wei, Jason Houston|
|Original Assignee||Intersil Americas Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (3), Referenced by (8), Classifications (8), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims priority to U.S. Provisional Application Ser. No. 60/933,949 filed on Jun. 8, 2007, which is incorporated by reference.
This application is related to U.S. patent application Ser. No. 12/136,014 entitled POWER SUPPLY WITH A MAGNETICALLY UNCOUPLED PHASE AND AN ODD NUMBER OF MAGNETICALLY COUPLED PHASES, AND CONTROL FOR A POWER SUPPLY WITH MAGNETICALLY COUPLED AND MAGNETICALLY UNCOUPLED PHASES, filed on Jun. 9, 2008, and Ser. No. 12/136,023 entitled INDUCTOR ASSEMBLY HAVING A CORE WITH MAGNETICALLY ISOLATED FORMS, filed on Jun. 9, 2008, which have a common owner and which are incorporated herein by reference.
This Summary is provided to introduce, in a simplified form, a selection of concepts that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.
An embodiment of a coupled-inductor core includes first and second members and first and second forms extending between members. The first form has a parameter (e.g., length) of a first value, and is operable to conduct a first magnetic flux having a first density that depends on the first value of the parameter. The second form is spaced apart from the first form, has the parameter (e.g., length) of a second value different from the first value, and is operable to conduct a second magnetic flux having a second density that depends on the second value of the parameter.
Because two or more of the forms of such a core may have different values for the same parameter, the core may be suitable for use in a multiphase power supply where the currents through the phases are unequal, i.e., are unbalanced, but the windings disposed about the forms have the same number of turns. As compared to a coupled-inductor assembly—“coupled-inductor assembly” is an assembly that includes the core and the windings—having windings with different numbers of turns, a coupled-inductor assembly having windings with the same number of turns may have at least one winding with less resistance, and thus may be more energy efficient and may generate less heat.
In addition to the coupled-inductor assembly 14, the converter 10 includes a power-supply controller 18, high-side drive transistors 20 1-20 n, low-side drive transistors 22 1-22 n, a filter capacitor 24, and an optional filter inductor 26. A winding 16 and the high-side and low-side transistors 20 and 22 coupled to the winding compose a respective phase 12. For example, the winding 16 1 and transistors 20 1 and 22 1 compose the phase 12 1.
The controller 18 may be any type of controller suitable for use in a buck converter, is supplied by voltages VDDcontroller and VSScontroller, and receives the regulated output voltage Vout, a reference voltage Vref, and feedback signals IFB1-IFBn, which are respectively proportional to the phase currents i1-in that flow through the respective phase windings 16 1-16 n. For example, each of these feedback signals IFB1-IFBn may be a respective voltage that has substantially the same signal phase as the corresponding phase current i and that has an amplitude proportional to the amplitude of the corresponding phase current, and may be generated by a series coupled resistor and capacitor (not shown in
The high-side transistors 20 1-20 n, which are each switched “on” and “off” by the controller 18, are power NMOS transistors that are respectively coupled between input voltages VIN1-VINn and the windings 16 1-16 n. Alternatively, the transistors 20 1-20 n may be other than power NMOS transistors, and may be coupled to a common input voltage. Moreover, the transistors 20 1-20 n may be integrated on the same die as the controller 18, may be integrated on a same die that is separate from the die on which the controller is integrated, or may be discrete components.
Similarly, the low-side transistors 22 1-22 n, which are each switched on and off by the controller 18, are power NMOS transistors that are respectively coupled between low-side voltages VL1-VLn and the windings 16 1-16 n. Alternatively, the transistors 22 1-22 n may be other than power NMOS transistors, and may be coupled to a common low-side voltage such as ground. Moreover, the transistors 22 1-22 n may be integrated on the same die as the controller 18, may be integrated on a same die that is separate from the die on which the controller is integrated, may be integrated on a same die as the high-side transistors 20 1-20 n, may be integrated on respective dies with the corresponding high-side transistors 20 1-20 n (e.g., transistors 20 1 and 22 1 on a first die, transistors 20 2 and 22 2 on a second die, and so on), or may be discrete components.
The filter capacitor 24 is coupled between Vout and a voltage VSScap, and works in concert with the windings 16 1-16 n and the filter inductor 26 (if present) to maintain the amplitude of the steady-state ripple voltage component of the regulated output voltage Vout within a desired range that may be on the order of hundreds of microvolts to tens of millivolts. Although only one filter capacitor 24 is shown, the converter 10 may include multiple filter capacitors coupled in electrical parallel. Furthermore, VSScap may be equal to VSScontroller and to VL1-VLn; for example, all of these voltages may equal ground.
As further discussed below, the filter inductor 26 may be omitted if the leakage inductances Llk1-Llkn of the windings 16 1-16 n are sufficient to perform the desired inductive filtering function. In some applications, the filter inductor 26 may be omitted to reduce the size and component count of the converter 10.
Each of the windings 16 1-16 n of the coupled-inductor assembly 14 may be modeled as a self inductance L and a resistance DCR. For purposes of discussion, only the model components of the winding 16 1 are discussed, it being understood that the model components of the other windings 16 2-16 n are similar, except for possibly their values.
The self inductance L1 of the winding 16 1 may be modeled as two zero-resistance inductances: a magnetic-coupling inductance LC1, and a leakage inductance Llk1. When a phase current i1 flows through the winding 16 1, the current generates a magnetic flux. The value of the coupling inductance LC1 is proportional to the amount of this flux that is coupled to other windings 16 2-16 n, and the value of the leakage inductance Llk1 is proportional to the amount of the remaining flux, which is not coupled to the other windings 16 2-16 n. In one embodiment, LC1=LC2= . . . =LCn, and Llk1=Llk2= . . . =Llkn, although inequality among the coupling inductances LC, the leakage inductances Llk, or both LC and Llk, is contemplated. Furthermore, in an embodiment, the respective magnetic-coupling coefficients between pairs of coupling inductances LC are equal (e.g., a current through LC1 magnetically induces respective equal currents in LC2, . . . LCn), although unequal coupling coefficients are contemplated.
The resistance DCR1 is the resistance of the winding 16 1 when a constant voltage V is applied across the winding and causes a constant current I to flow through the winding. That is, DCR1=V/I.
Because the phase currents i1 and i2 are balanced, the maximum A1max of i1 substantially equals the maximum A2max of i2, the minimum A1min of i1 substantially equals the minimum A2min of i2, the peak-to-peak amplitude A1pp substantially equals the peak-to-peak amplitude A2pp of i2, and the average A1avg of i1 substantially equals the average A2avg of i2.
While PWM1 is high (logic 1), the high-side transistor 20 1 is on and the low-side transistor 22 1 is off, and an increasing phase current i1 flows from VIN1, through the transistor 20 1, winding 16 1, and filter inductor 26 (if present), and to the capacitor 24 and to a load 28 that is supplied by Vout. This increasing current i1 generates a magnetic flux that induces a corresponding increase in the current i2 flowing through the other coupled phase 12 2.
In contrast, while PWM1 is low (logic 0), the high-side transistor 20 1 is off and the low-side transistor 22 1 is on, and the current i1, which is now decreasing, flows from VL1, through the transistor 22 1, winding 16 1 and filter inductor 26 (if present), and to the capacitor 24 and to the load 28. The current i2 also decreases. The currents i1 and i2 continue to decrease until PWM2 goes high as discussed below.
Similarly, while PWM2 is high, the high-side transistor 20 2 is on and the low-side transistor 22 2 is off, and an increasing current i2 flows from VIN2, through the transistor 20 2, winding 16 2, and filter inductor 26 (if present), and to the capacitor 24 and to the load 28. This increasing current i2 generates a magnetic flux that induces a corresponding increase in the current i1 flowing through the phase 12 1.
In contrast, while PWM2 is low, the high-side transistor 20 2 is off and the low-side transistor 22 2 is on, and the current i2, which is now decreasing, flows from VL2, through the transistor 22 2, winding 16 2 and filter inductor 26 (if present), and to the capacitor 24 and to the load 28. The current i1 also decreases. The currents i1 and i2 continue to decrease until PWM1 goes high again as discussed above.
The controller 18 compares Vout to Vref, and controls the duty cycles of PWM1 and PWM2 to maintain a predetermined constant relationship between Vout and Vref in the steady state, e.g., Vout=2Vref for example, Vout may be the average or minimum of the output ripple component. For example, as current drawn by the load 28 increases, the controller 18 may increase the on times or otherwise alter the duty cycles of PWM1 and PWM2 to accommodate the increased load current; conversely, as the load current decreases, the controller may decrease the on times or otherwise alter the duty cycles of PWM1 and PWM2 to accommodate the decreased load current. The controller 18 may use a pulse-width-modulation (PWM) technique, a constant-on-time technique, or another technique to control the on and off times of the high-side and low-side transistors 20 1-20 2 and 22 1-22 2.
The controller 18 may also monitor the feedback signals IFB1 and IFB2, and adjusts the on times or otherwise adjusts the duty cycles of PWM1 and PWM2 as needed to maintain the balance between the currents i1 and i2. That is, the controller 18 adjusts PWM1 and PWM2 so that A1max, A1min, A1pp, and A1avg stay substantially equal to A2max, A2min, A2pp, and A2avg respectively. An embodiment of current-balancing circuitry that the controller 18 may include is disclosed in U.S. Pat. No. 6,278,263, which is incorporated by reference.
Because the currents i1 and i2 are balanced, the coupled-inductor assembly 14 may be symmetrical such that there is little or no chance of saturating the core (not shown in
But still referring to
If the converter 10 is designed for two or more windings 16 1-16 n to carry unbalanced currents, then the core of the coupled-inductor assembly 14 may be designed so that no portion of the assembly's core saturates during operation of the converter.
One technique for preventing saturation of the assembly 14 core is to make the Ni products equal in each of the phases carrying unbalanced currents i; therefore, because the currents i in these phases are unequal, the number of turns N of the respective windings 16 are also unequal.
But this technique may result in one or more of the corresponding windings 16 being longer than, and thus having a greater DCR than, respective windings in a core assembly designed to carry balanced currents i.
Furthermore, because N must be an integer per Maxwell's equations, this technique constrains the unbalanced currents i to be integer multiples of one another.
Still referring to
Reducing the DCR of one or more of the windings 16 1-16 n may reduce the amount of power (Irms 2·DCR) that the windings (and thus the coupled-inductor assembly 14) consume, and thus may reduce the amount of heat that the windings (and thus the coupled-inductor assembly) generate.
Consequently, a coupled-inductor assembly 14 allowing unbalanced phase currents and having one or more windings with reduced DCRs may allow the converter 10 to be more power efficient and to generate less heat than a converter that has unbalanced phase currents and that includes a coupled-inductor assembly with windings having different numbers of turns.
Furthermore, allowing one unbalanced current to be a non-integer multiple of another unbalanced current may increase the number of applications in which one may use a coupled-inductor power supply such as the converter 10.
Referring again to
Further descriptions of coupled-inductor power supplies appear in the following references, which are incorporated by reference: Wong et al., Investigating Coupling Inductors In The Interleaved QSW VRM, IEEE 2000, and Park et al., Modeling And Analysis Of Multi-Interphase Transformers For Connecting Power Converters In Parallel, IEEE 1997.
The circuit 30 includes an error amplifier 32, a phase-current summer 34, phase-current scalers 36 1-36 n, current-unbalancing summers 38 1-38 n, gain blocks 40 1-40 n, PWM summers 42 1-42 n, and PWM signal generators 44 1-44 n.
The error amplifier 32 generates a control voltage VEA, which is proportional to the difference between the regulated output voltage Vout (or a scaled version of Vout) and the reference voltage Vref. VEA may be the result of the amplifier 32 low-pass filtering the difference between Vout and Vref.
The phase-current summer 34 adds the feedback signals IFB1-IFBn to generate a signal ILOADcalculated, which is proportional to the actual load current ILOAD through the load 28 (
Each of the phase-current scalers 36 1-36 n scales ILOADcalculated by a respective one of the values n/a1-n/an according to the respective phase current to be carried by the respective winding 16, where n is the number of coupled phases 12 1-12 n and where a1-an are respective balancing coefficients.
Each of the current-unbalancing summers 38 1-38 n subtracts from a respective signal IFB1-IFBn a scaled signal from a respective one of the scalers 36 1-36 n.
Each of the gain blocks 40 1-40 n multiplies a sum from a respective one of the summers 38 1-38 n by a respective gain value G1-Gn to generate a respective signal ΔI1-ΔIn. The values G1-Gn may be selected to give specified frequency and error-correction responses to the respective feedback loops formed in part by the summer 34, the scalers 36 1-36 n, the summers 38 1-38 n, and the gain blocks 40 1-40 n. Alternatively, the gain blocks 40 1-40 n may be omitted, which is equivalent to G1=G2= . . . =Gn=1.
Each of the summers 42 1-42 n subtracts a respective one of the signals ΔI1-ΔIn from VEA.
Each of the PWM signal generators 44 1-44 n includes a comparator that receives on a non-inverting input node the resulting sum from a respective one of the summers 42 1-42 n, that receives on an inverting input node a respective conventional ramp signal, and that generates on an output node a respective one of the signals PWM1-PWMn. The phases of the ramp signals may be offset in a conventional manner such that the phases of PWM1-PWMn are offset, for example, by 360°/n as discussed above in conjunction with
The “on” portions of PWM1 and PWM2 (e.g., the portions of PWM1 and PWM2 at logic 1 in
As described below, the signals ΔI1-ΔI2 effectively and respectively adjust the signal VEA for the phases 12 1-12 2 via the PWM summers 42 1-42 n to set i1=3·i2.
i 1=3·i 2 (1)
I FB1=3·I FB2 (2)
n/a 1 ·I LOADcalculated =I FB1 (3)
n/a 2 ·I LOADcalculated =I FB2. (4)
Also, because n/a1·ILOADcalculated+n/a2·ILOADcalculated=ILOADcalculated, then
n/a 1 +n/a 2=1. (5)
Therefore, from equations (2)-(4), one may derive the following:
n/a 1 ·I LOADcalculated=3·I FB2=3·n/a 2 ·I LOADcalculated (6)
And, from equations (5) and (7) and that n=2 in this embodiment, one may derive the following:
a 1 =a 2 ·n/(a 2 −n) (8)
a 1=8/3 (9)
Therefore, when IFB1=3·IFB2, IFB1=2/(8/3)=¾·ILOADcalculated, IFB2=¼·ILOADcalculated, the output of the unbalancing summer 38 1 equals zero, and the output of the unbalancing summer 38 2 equals zero, and the circuit 30 makes no adjustment to the signal VEA from the error amplifier 32.
But suppose that IFB1<3·IFB2, and thus both IFB1, and i1 are too low.
Therefore, the difference output of the unbalancing summer 38 1 is negative and the value ΔI1 is negative, but the inverting input of the PWM summer 42 1 effectively makes ΔI1 positive, and thus makes the output of the PWM summer 44 1 more positive as compared to the summer output due to VEA alone. This tends to increase the on portion of PWM1, and thus tends to increase both IFB1, and i1.
In contrast, when IFB1<3IFB2, then IFB2>(IFB1)/3, and both IFB2 and i2 are too high.
Therefore, the difference output of the unbalancing summer 38 2 is positive and the value ΔI2 is positive, but the inverting input of the PWM summer 42 2 effectively makes ΔI2 negative, and thus makes the output of the PWM summer 44 2 more negative as compared to the output due to VEA alone. This tends to decrease the on portion of PWM2, and thus tends to decrease both IFB2 and i2.
Consequently, when IFB1 is too low and IFB2 is too high, the current unbalancing circuit 30 acts to increase IFB1 and reduce IFB2 to the values set by the scalers 36 1-36 2, and thus acts to increase i1 and reduce i2 toward i1=3·i2. But since the current-unbalancing circuit 30 maintains ILOADcalculated (and thus maintains the actual load current ILOAD) substantially constant, the unbalancing circuit ideally does not cause Vout to drift out of regulation by causing Vout to increase or decrease relative to Vref.
In a similar manner, the unbalancing circuit 30 acts to decrease IFB1 and i1 and to increase IFB2 and i2 to the respective values set by the scalers 36 1-36 2 when IFB1 and i1 are too high and IFB2 and i2 are too low.
And when IFB1 and IFB2 equal the values respectively set by the scalers 36 1 and 36 2 (and thus i1=3·i2), the difference signals ΔI1=ΔI2=0, and the signal VEA sets the on portions of PWM1 and PWM2 as if the circuitry generating ΔI1 and ΔI2 were not present.
Still referring to
Referring again to
In addition to the windings 16 1-16 n, the core assembly 14 includes a core 50 having winding forms 52 1-52 n and an optional leakage form 53, and members 54 and 56, which interconnect the forms. That is, using a ladder analogy, the forms 52 1-52 n are the rungs of the ladder, and the members 54 and 56 are the rails to which the rungs are connected. Spaces 58 1-58 n are located between the forms 52 1-52 n and 54.
Each winding 16 1-16 n is formed from a respective conductor 60 1-60 n, which has a respective width W1-Wn, and each conductor 60 1-60 n is wound, in a Faraday's law sense, N1-Nn turns about a respective form 52 1-52 n and extends beneath and adjacent to the remaining forms. For example, the winding 16 1 is formed from a conductor 60 1 that is wound N1=1 turn about the form 52 1 and extends beneath and adjacent to the remaining forms 52 2-52 n. Although the conductor 60 1 is adjacent to only three sides of the form 52 1, the current i1 through the conductor 60 1 traverses a closed loop through which the form 52 1 passes. The portions of this closed loop other than the conductor 60 1 may be formed, e.g., by a conductive trace on a circuit board on which the core assembly 14 is disposed. Therefore, N1 is the integer number of closed loops through which the form 52 1 extends. Similarly, the winding 16 2 is formed from a conductor 60 2 that is wound N2=1 turn about the form 52 2 and extends beneath and adjacent to the remaining forms 52 1 and 52 3-52 n, and so on. The conductors 60 1-60 n may be made from any suitable conductive material such as copper or another metal, and may, but need not be, electrically insulated from the forms 52 1-52 n.
Each form 52 1-52 n and 53 has a respective length I1-In and Ilk, a respective permeability μ1-μn and μlk, and a respective cross-sectional area A1-An and Alk. Although some of these like parameters (e.g., the lengths I1-In and Ilk) are shown as being equal in
As the current i1 flows through the conductive loop composed in part by the conductor 60 1, it generates a total magnetic flux φT. In a first-order approximation, a first portion φ1 of the total flux φT flows through the form 52 1, and a second portion φout of the total flux φT flows outside of the form 52 1 such that φT is given by the following equation:
The first flux portion φ1 flows through the remaining forms 52 2-52 n and 53 such that the sum of the fluxes φ2-φn and φlk flowing through each of the remaining forms equals φ1. Because the portion of φ1 that equals φ2+φ3+ . . . +φn flows through the forms 52 2-52 n about which the conductors 60 2-60 n are wound, this portion of φ1 is called the coupling flux. The portion φ2-φn of the coupling flux φ1 induce respective currents to flow in the conductors 60 2-60 n. As discussed further below in conjunction with
And the remaining flux equal to the sum φout+φlk is called the total leakage flux, because it does not induce any currents to flow in the conductors 60 2-60 n. Where φout<<φlk, then the total leakage flux may be approximated as φlk. As discussed further below in conjunction with
Referring again to
For known reasons that are omitted for brevity, it may be desirable to run a power supply like the buck converter 10 of
An embodiment of a technique for designing the core 50 and the core-assembly 14 so that no portion of the core saturates under expected operating conditions is discussed below in conjunction with
φ1 and φ2 of the model circuit 80 may be given by the following:
And R1, R2, and Rlk are given by the following:
Furthermore, the flux densities B1 and B2 through the forms 52 1 and 52 2 are given by the following:
Therefore, to prevent saturation of the forms 52 1 and 52 2 (and thus to prevent saturation of all portions of the core 50 in this example), one may designs the core 50 according to the following:
where B1max is the maximum flux density that the form 52 1 is able to conduct without saturating, and B2max is the maximum flux density that the form 52 2 is able to conduct without saturating. One may determine B1max and B2max in a conventional manner. For example, one may determine B1max and B2max from μ1 and μ2, or retrieve B1max and B2max from a table based on the respective materials from which the forms 52 1 and 52 2 are made.
i 1 =m·i 2 (21)
where m may be any positive number.
From equations (12)-(21), one may derive the following expressions of the respective flux densities φ1 and φ2 in the forms 52 1 and 52 2 of the core 14, where φ1 and φ2 do not saturate the respective forms 52 1 and 52 2 or any other part of the core 50 in this example:
In this design example, the following equalities are also assumed:
From equations (22)-(26), one may derive the following expressions for B1 and B2:
Then, for a specified value for i1, a designer may select values for A, N, μ, μlk, I1, I2, and Ilk such that equations (27) and (28) are true. Furthermore, to set B1 equal to B2, the designer may select the values for μ, μlk, I1, I2, and Ilk according to the following equation, which is derived from equations (27) and (28):
Furthermore, in this example, although the coupled-inductor assembly 14 is designed for the windings 16 1 and 16 2 to carry unbalanced currents i1 and i2, the windings have the same number of turns N. Moreover, unlike the number of turns N, the variable m is not constrained to only integer values.
Appendix A includes additional mathematical expressions that are derived from the circuit model 80 of
Still referring to
The system 90 includes computer circuitry 94 for performing computer functions, such as executing software to perform desired calculations and tasks. The circuitry 94 typically includes a controller, processor, or one or more other integrated circuits (ICs) 96, and the power supply 92, which provides power to the IC(s) 96. One or more input devices 98, such as a keyboard or a mouse, are coupled to the computer circuitry 94 and allow an operator (not shown) to manually input data thereto. One or more output devices 100 are coupled to the computer circuitry 94 to provide to the operator data generated by the computer circuitry. Examples of such output devices 100 include a printer and a video display unit. One or more data-storage devices 102 are coupled to the computer circuitry 94 to store data on or retrieve data from external storage media (not shown). Examples of the storage devices 102 and the corresponding storage media include drives that accept hard and floppy disks, tape cassettes, compact disk read-only memories (CD-ROMs), and digital-versatile disks (DVDs).
From the foregoing it will be appreciated that, although specific embodiments have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Furthermore, where an alternative is disclosed for a particular embodiment, this alternative may also apply to other embodiments even if not specifically stated.
The following are mathematical expressions for parameters of a two-phase embodiment of the coupled-inductor core assembly 14 of
L1=Lc1+Llk1 is the self inductance of the winding 16 1.
L2=Lc2+Llk2 is the self inductance of the winding 16 2.
Lm=Lc1=Lc2 is the coupling inductance between the windings 16 1 and 16 2.
Llk1 is the leakage inductance of the winding 16 1, and is defined in terms of the portion of the self flux L1i1 that flows through the leakage form 53 when i1=1 A.
Llk2 is the leakage inductance of the winding 16 2, and is defined in terms of the portion of the self flux L2i2 that flows through the leakage form 53 when i2=1 A.
R1 is the reluctance of the form 52 1.
R2 is the reluctance of the form 52 2.
Rlk is the reluctance of the leakage form 53.
A1 is the cross-sectional area of the form 52 1.
A2 is the cross-sectional area of the form 52 2.
Alk is the cross-sectional area of the form 53.
μ1 is the permeability of the form 52 1.
μ2 is the permeability of the form 52 2.
μ3 is the permeability of the form 53.
If core and
If Leakage rung
If core structure
If winding structure
has no air gap
(Rk = 0)
(R1 = R2)
(N1 = N2)
(R1 = R2, N1 = N2)
Lm = 0
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|Cooperative Classification||H02M7/003, H02M3/1584, H02M3/156|
|European Classification||H02M3/158P, H02M3/156, H02M7/00D|
|Jun 11, 2008||AS||Assignment|
Owner name: INTERSIL AMERICAS INC., CALIFORNIA
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|May 4, 2010||AS||Assignment|
Owner name: MORGAN STANLEY & CO. INCORPORATED,NEW YORK
Free format text: SECURITY AGREEMENT;ASSIGNORS:INTERSIL CORPORATION;TECHWELL, INC.;INTERSIL COMMUNICATIONS, INC.;AND OTHERS;REEL/FRAME:024329/0411
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