Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20090049234 A1
Publication typeApplication
Application numberUS 12/015,548
Publication dateFeb 19, 2009
Filing dateJan 17, 2008
Priority dateAug 14, 2007
Also published asCN101369451A, CN103400598A, DE102008036822A1, US8626996, US9208079, US20110138115, US20130042058, US20140101377, US20140122783, US20140337566, US20150261667, US20160231941
Publication number015548, 12015548, US 2009/0049234 A1, US 2009/049234 A1, US 20090049234 A1, US 20090049234A1, US 2009049234 A1, US 2009049234A1, US-A1-20090049234, US-A1-2009049234, US2009/0049234A1, US2009/049234A1, US20090049234 A1, US20090049234A1, US2009049234 A1, US2009049234A1
InventorsMoon-wook OH, Do-Geun Kim, Chan-ik Park
Original AssigneeSamsung Electronics Co., Ltd.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Solid state memory (ssm), computer system including an ssm, and method of operating an ssm
US 20090049234 A1
Abstract
In one aspect, data is stored in a solid state memory which includes first and second memory layers. A first assessment is executed to determine whether received data is hot data or cold data. Received data which is assessed as hot data during the first assessment is stored in the first memory layer, and received data which is first assessed as cold data during the first assessment is stored in the second memory layer. Further, a second assessment is executed to determine whether the data stored in the first memory layer is hot data or cold data. Data which is then assessed as cold data during the second assessment is migrated from the first memory layer to the second memory layer.
Images(9)
Previous page
Next page
Claims(32)
1. A method of storing data in a solid state memory including first and second memory layers, said method comprising:
executing a first assessment of whether received data is hot data or cold data;
storing received data which is assessed as hot data during the first assessment in the first memory layer;
storing received data which is assessed as cold data during the first assessment in the second memory layer;
executing a second assessment of whether the data stored in the first memory layer is hot data or cold data; and
migrating data which is assessed as cold data during the second assessment from the first memory layer to the second memory layer.
2. The method as claimed in claim 1, wherein an operational speed of the first memory layer is higher than an operational speed of the second memory layer.
3. The method as claimed in claim 2, wherein the first and second memory layers are comprised of respectively different types of memory cells.
4. The method as claimed in claim 1, wherein the first memory layer is comprised of single-level flash memory cells and the second memory layer is comprised of multi-level flash memory cells.
5. The method as claimed in claim 1, wherein the first and second memory layers are comprised of multi-level flash memory cells, and wherein data is stored in a least-significant bit only of the multi-level flash memory cells of the first memory layer.
6. The method as claimed in claim 1, wherein the first and second memory layers are comprised of a same type of memory cell.
7. The method as claimed in claim 6, wherein a mapping grain of the first memory layer is finer than a mapping grain of the second memory layer.
8. The method as claimed in claim 7, wherein the first and second memory layers are comprised of single-level flash memory cells.
9. The method as claimed in claim 7, wherein the first and second memory layers are comprised of multi-level flash memory cells.
10. The method as claimed in claim 1, wherein the data which is first assessed as cold data during the first assessment is temporarily stored in the first memory layer prior to being stored in the second memory layer.
11. The method as claimed in claim 1, wherein the second assessment further includes a determination of whether unused memory capacity of the first memory layer is less than a threshold.
12. The method as claimed in claim 1, wherein the second assessment is executed a periodic intervals or when the solid state memory enters an idle state.
13. The method as claimed in claim 1, wherein the first and second memory layers are contained in a solid state drive.
14. The method as claimed in claim 1, wherein the first and second memory layers are contained in the main memory of a computer system.
15. A method of storing received data in a solid state memory comprising initially storing hot data in a high-speed memory layer and, and then migrating a portion of the data stored in the high-speed memory layer to a low-speed memory layer for storing cold data.
16. The method as claimed in claim 15, wherein the high-speed and low-speed non-volatile memory layers are comprised of respectively different types of memory cells.
17. The method as claimed in claim 15, wherein the high-speed and low-speed non-volatile memory layers are comprised of a same type of memory cells.
18. A solid state memory system, comprising:
a first memory layer;
a second memory layer; and
a memory controller configured to execute a first assessment of whether received data is hot data or cold data, to store received data which is assessed as hot data during the first assessment in the first memory layer, and to store received data which is assessed as cold data during the first assessment in the second memory layer,
wherein the memory controller is further configured to execute a second assessment of whether the data stored in the first memory layer is hot data or cold data, and to migrate data which is assessed as cold data during the second assessment from the first memory layer to the second memory layer.
19. The solid state memory as claimed in claim 18, wherein the memory controller is operatively connected to the first and second memory layers using respectively different data channels.
20. The solid state memory as claimed in claim 18, wherein the memory controller is operatively connected to the first and second memory layers using common data channels.
21. The solid state memory as claimed in claim 18, wherein an operational speed of the first memory layer is higher than an operational speed of the second memory layer.
22. The solid state memory as claimed in claim 21, wherein the first and second memory layers are comprised of respectively different types of memory cells.
23. The solid state memory as claimed in claim 21, wherein the first and second memory layers are comprised of a same type of memory cells.
24. The solid state memory as claimed in claim 18, wherein the data which is first assessed as cold data during the first assessment is temporarily stored in the first memory layer prior to being stored in the second memory layer.
25. The solid state memory as claimed in claim 18, wherein the first and second memory layers are contained in a solid state drive.
26. The solid state memory as claimed in claim 18, wherein the first and second memory layers are contained in the main memory of a computer system.
27. A solid state memory system which is configured to operatively connect to a computer operating system and which comprises first and second memory layers, wherein an operational speed of the first memory layer is greater than an operational speed of the second memory layer, and wherein the first memory area is operationally hidden from the computer operating system when the solid state memory is operatively connected to the computer operating system.
28. The solid state memory system of claim 27, wherein the solid state memory further comprises a controller configured to execute a first assessment of whether received data is hot data or cold data, to store received data which is assessed as hot data during the first assessment in the first memory layer, and to store received data which is assessed as cold data during the first assessment in the second memory layer,
wherein the memory controller is further configured to execute a second assessment of whether the data stored in the first memory layer is hot data or cold data, and to migrate data which is assessed as cold data during the second assessment from the first memory layer to the second memory layer.
29. A computer system comprising a processor and a solid state memory, wherein the solid state memory comprises a high-speed memory layer and a low-speed memory layer, and wherein the high-speed memory area is operationally hidden from the processor.
30. The computer system as claimed in claim 29, wherein the solid state memory further comprises a memory controller configured to execute a first assessment of whether received data is hot data or cold data, to store received data which is assessed as hot data during the first assessment in the high-speed memory layer, and to store received data which is assessed as cold data during the first assessment in the low-speed memory layer,
wherein the memory controller is further configured to execute a second assessment of whether the data stored in the high-speed memory layer is hot data or cold data, and to migrate data which is assessed as cold data during the second assessment from the high-speed memory layer to the low-speed memory layer.
31. The computer system as claimed in claim 29, wherein the memory is a solid state drive.
32. The computer system as claimed in claim 29, wherein the memory is a main memory.
Description
    BACKGROUND OF THE INVENTION
  • [0001]
    1. Field of the Invention
  • [0002]
    The present invention generally relates to memory systems, and more particularly, the present invention relates to a solid state memory (SSM), a computer system which includes an SSM, and a method of operating an SSM. Examples of the SSM include the main memory of a computer system and the solid state drive (SSD) of a computer system.
  • [0003]
    A claim of priority is made to Korean Patent Application No. 2007-0081832, filed Aug. 8, 2007, the entirety of which is incorporated herein by reference.
  • [0004]
    2. Description of the Related Art
  • [0005]
    A solid state drive (SSD) is a data storage device that typically emulates a conventional hard disk drive (HDD), thus easily replacing the HDD in most applications. In contrast to the rotating disk medium of an HDD, an SSD utilizes solid state memory to store data. With no moving parts, an SSD largely eliminates seek time, latency and other electro-mechanical delays and failures associated with a conventional HDD.
  • [0006]
    An SSD is commonly composed of either NAND flash (non-volatile) or SDRAM (volatile).
  • [0007]
    SSDs based on volatile memory such as SDRAM are characterized by fast data access and are used primarily to accelerate applications that would otherwise be held back by the latency of disk drives. The volatile memory of the DRAM-based SSDs typically requires the inclusion of an internal battery and a backup disk system to ensure data persistence. If power is lost, the battery maintains power for sufficient duration of copy data from the SDRAM to the backup disk system. Upon restoration of power, data is copied back from the backup disk to SDRAM, at which time the SSD resumes normal operations.
  • [0008]
    However, most SSD manufacturers use non-volatile flash memory to create more rugged and compact alternatives to DRAM-based SSDs. These flash memory-based SSDs, also known as flash drives, do not require batteries, allowing makers to more easily replicate standard hard disk drives. In addition, non-volatile flash SSDs retain memory during power loss.
  • [0009]
    As is well know in the art, single-level cell (SLC) flash is capable of storing one bit per memory cell, while multi-level cell (MLC) flash is capable of storing two or more bits per memory cell. As such, in order to increase capacity, flash SSDs may utilize multi-level cell (MLC) memory banks. However, flash SSDs generally suffer from relatively slow random write speeds, and this operational drawback is further exasperated with relatively slow speeds of MLC flash. As such, it has been suggested to equip SSDs with two types of flash storage media—lower capacity SLC memory banks and higher capacity MLC memory banks. With such a configuration, frequently used data (e.g., directory and/or log information) can be stored in the faster SLC banks, while less frequently used data (e.g., music files, images, etc.) can be stored in the slower MLC banks.
  • SUMMARY OF THE INVENTION
  • [0010]
    According to an aspect of the present invention, data is stored in a solid state memory which includes first and second memory layers. A first assessment is executed to determine whether received data is hot data or cold data. Received data which is assessed as hot data during the first assessment is stored in the first memory layer, and received data which is assessed as cold data during the first assessment is stored in the second memory layer. Further, a second assessment is executed to determine whether the data stored in the first memory layer is hot data or cold data. Data which is then assessed as cold data during the second assessment is migrated from the first memory layer to the second memory layer.
  • [0011]
    According to another aspect of the present invention, a method of storing received data in a solid state memory includes initially storing hot data in a high-speed memory layer and, and then migrating a portion of the data stored in the high-speed memory layer to a low-speed memory layer for storing cold data.
  • [0012]
    According to yet another aspect of the present invention, a solid state memory system includes a first memory layer, a second memory layer, and a memory controller. The memory controller is configured to execute a first assessment of whether received data is hot data or cold data, to store received data which is assessed as hot data during the first assessment in the first memory layer, and to store received data which is assessed as cold data during the first assessment in the second memory layer. The memory controller is further configured to execute a second assessment of whether the data stored in the first memory layer is hot data or cold data, and to migrate data which is assessed as cold data during the second assessment from the first memory layer to the second memory layer.
  • [0013]
    According to still another aspect of the present invention, a solid state memory system is configured to operatively connect to a computer operating system and comprises first and second memory layers. An operational speed of the first memory layer is greater than an operational speed of the second memory layer, and the first memory area is operationally hidden from the computer operating system when the solid state memory is operatively connected to the computer operating system.
  • [0014]
    According to another aspect of the present invention, a computer system includes a processor and a memory. The solid state memory includes a high-speed memory layer and a low-speed memory layer, and the high-speed memory area is operationally hidden from the processor.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0015]
    The above and other aspects and features of the present invention will become readily apparent from the detailed description that follows, with reference to the accompanying drawings, in which:
  • [0016]
    FIG. 1 is a block diagram of a solid state drive (SSD) according to an embodiment of the present invention;
  • [0017]
    FIGS. 2 and 3 are block diagrams for describing a non-volatile storage media in the SSD of FIG. 1 according to an embodiment of the present invention;
  • [0018]
    FIGS. 4 and 5 are block diagrams for describing alternative ways of coupling a non-volatile storage media to an interface in the SSD of FIG. 1 according to embodiments of the present invention;
  • [0019]
    FIGS. 6 through 8 are flow charts for use in describing methods of allocating data to regions of a non-volatile storage media in the SSD of FIG. 1 according to embodiments of the present invention;
  • [0020]
    FIG. 9 is a block diagram of the computer system including an SSD according to an embodiment of the present invention; and
  • [0021]
    FIGS. 10 and 11 are block diagrams of a main memory according to embodiments of the present invention.
  • DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • [0022]
    The present invention will now be described by way of preferred, but non-limiting, embodiments of the invention. It is emphasized here that the invention is not limited by the exemplary embodiments described below, and that instead the scope of the invention is delimited by the appended claims.
  • [0023]
    FIG. 1 illustrates a block diagram of a solid state drive (SSD) 1000 according to an embodiment of the present invention. As shown, the SSD 1000 of this example includes an SSD controller 1200 and non-volatile storage media 1400.
  • [0024]
    The SSD controller 1200 includes first and second interfaces 1210 and 1230, a controller 1220, and a memory 1240.
  • [0025]
    The first interface 1210 functions as a data I/O interface with a host device, such as a host central processing unit (CPU) (not shown). Non-limiting examples of the first interface 1210 include Universal Serial Bus (USB) interfaces, Advanced Technology Attachment (ATA) interfaces, Serial ATA (SATA) interfaces, Small Computer System Interface (SCSI) interfaces.
  • [0026]
    The second interface 1230 functions as a data I/O interface with the non-volatile storage media 1400. In particular, the second interface 1230 is utilized to transmit/receive various commands, addresses and data to/from the non-volatile storage media 1400. As will be apparent to those skilled in the art, a variety of different structures and configurations of the second interface 1230 are possible, and thus a detailed description thereof is omitted here for brevity.
  • [0027]
    The controller 1220 and memory 1240 are operatively connected between the first and second interfaces 1210 and 1230, and together function to control/manage the flow of data between the host device (not shown) and the non-volatile storage media 1400. The memory 1240 may, for example, be an DRAM type of memory device, and the controller 1220 may, for example, include a central processing unit (CPU), a direct memory access (DMA) controller, and an error correction control (ECC) engine. Examples of controller functionality may be found in commonly assigned U.S. Patent Publication 2006-0152981, which is incorporated herein by reference. The operations generally executed by controller 1220 (and memory 1240) to transfer data between the host device (not shown) and SSD memory banks are understood by those skilled in the art, and thus a detailed description thereof is omitted here for brevity. Rather, the operational description presented later herein is primarily focused on inventive aspects relating to various embodiments of the invention.
  • [0028]
    Still referring to FIG. 1, the non-volatile storage media 1400 of this example includes a high-speed non-volatile memory (NVM) 1410 and a low-speed non-volatile memory (NVM) 1420. As the names suggest, the high-speed NVM 1410 is capable of operating at a relatively higher speed (e.g., random write speed) when compared to the low-speed NVM 1420.
  • [0029]
    In an exemplary embodiment, the high-speed NVM 1410 is single-level cell (SLC) flash memory, and the low-speed NVM 1420 is multi-level cell (MLC) flash memory. However, the invention is not limited in this respect. For example, the high-speed NVM 1410 may instead be comprised of phase-change random access memory (PRAM), or MLC flash memory in which one bit per cell is utilized. Also, the high-speed NVM 1410 and the low-speed NVM 1420 may be comprised of the same type of memory (e.g., SLC or MLC or PRAM), where the operational speed is differentiated by fine-grain mapping in the high-speed NVM 1410 and coarse-grain mapping in the low-speed NVM 1420.
  • [0030]
    Generally, the high-speed NVM 1410 is utilized to store frequently accessed (written) data such as meta data, and the low-speed NVM 1420 is utilized to store less frequently accessed (written) data such as media data. In other words, as will discussed later herein, a write frequency of data in the high-speed NVM 1410 is statistically higher than a write frequency of data in the low-speed NVM 1420. Also, due to the nature of the respective data being stored, the storage capacity of the low-speed NVM 1420 will typically be much higher than that of the high-speed NVM 1410.
  • [0031]
    In an exemplary embodiment, the high-speed NVM 1410 is hidden from an external operating system connected to the SSD. This aspect of the embodiment is illustrated in FIGS. 2 and 3.
  • [0032]
    Referring collectively to FIGS. 2 and 3, the high-speed NVM 1410 of the example of this embodiment is a hidden region—that is, the high-speed NVM 1410 is cannot be seen (directly addressed) by the external operating system (OS). Rather, the address space shown relative to the OS view is only the low-speed NVM 1420. On the other hand, the address space shown relative to the Flash Translation Layer (FTL) is both the high-speed NVM 1410 and the low-speed NVM 1420. The FTL translates an address provided by the OS into a physical address of the non-volatile storage media 1400 (i.e., a physical address within the high-speed NVM 1410 or the low-speed NVM 1420).
  • [0033]
    Turning to the block diagrams of FIGS. 4 and 5, there are a number of different ways in which the high-speed NVM 1410 and the low-speed NVM 1420 can be operative connected to the controller 1220 (FIG. 1) via the interface 1230. In the example of FIG. 4, the high-speed NVM 1410 and the low-speed NVM 1420 communicate via the interface 1230 using common interface channels. In the example of FIG. 5, the high-speed NVM 1410 and the low-speed NVM 1420 communicate via the interface 1230 using separate interface channels.
  • [0034]
    It is again noted, however, that the high-speed NVM 1410 and the low-speed NVM 1420 need not be composed of different types of memory. That is, a single type of memory may be operationally segregated into a high-speed layer and a low-speed layer. For example, the grain mapping in the two layers may differ, or the number of bits utilized per cell in the two layers may differ. Further, the high-speed memory layer and the low-speed memory layer may be segregated at the chip level (e.g., contained in different memory chips), or within the same memory chip (e.g., contained in different memory blocks or groups of memory cells of the same memory chip).
  • [0035]
    An operational description of the SSD according to embodiments of the present invention is presented next.
  • [0036]
    According to an embodiment of the present invention in which data is stored in the SSD, a first assessment is executed to determine whether received data is hot data or cold data. As will be understood by those skilled in the art, “hot” data is a term of art that refers to data which is frequently written or updated (requiring write access), such a directory information and/or logging information. “Cold” data is all other data, i.e., data which is not frequently written or updated, such as image files, sound files, program code and so on. Cold data may be written once or infrequently, but read frequently. Thus, it is the frequency of write access that separates hot data from cold.
  • [0037]
    Received data which is assessed as hot data during the first assessment is stored in the high-speed NVM 1410, and received data which is first assessed as cold data during the first assessment is stored in the low-speed NVM 1420.
  • [0038]
    Then, a second assessment is executed to determine whether the data stored in the high-speed NVM 1410 is hot data or cold data. In other words, the data stored in the high-speed NVM 1410 reassessed to determine with the data should be reclassified as cold data. Data which is then assessed as cold data during the second assessment is migrated from the high-speed NVM 1410 to the low-speed NVM 1420.
  • [0039]
    By periodically migrating data which initially determined to be hot data from the high-speed NVM 1410 to the low-speed NVM 1420, the size of the high-speed NVM 1410 can be reduced. This can potentially result in cost savings, and increase the overall storage capacity of the SSD (e.g., by allowing for more space for the high-capacity MLC layer).
  • [0040]
    The second assessment and migration of data to the low-speed NVM 1420 can be programmed to occur, for example, when the unused capacity of the high-speed NVM 1410 is less than a preset value. Alternately, for example, the second assessment and migration of data to the low-speed NVM 1420 can be programmed to occur at given periodic intervals, or when the SSD is idle. Examples of an idle state may include periods in which no read/write request is received from the host, or when the activation ratio or intensity of read/write requests is less than a threshold.
  • [0041]
    FIG. 6 is a flow chart for use in describing the first assessment and storage (write) of data in the SSD according to an embodiment of the present invention.
  • [0042]
    Initially, at step 100, a write command, an address and data are received. Then, at step 110, a determination is made as to whether the received data is classified as hot data. If the received data is classified as hot data, the received data is stored in the high-speed NVM 1410 at step 120. On the other hand, if the received data is not classified as hot data, the received data is stored in the low-speed NVM 1420 at step 130.
  • [0043]
    It should be noted that data stored in the low-speed NVM 1420 at step 130 may first be “passed through” the high-speed NVM 1410. In other words, the data may first be briefly (temporarily) stored in the high-speed NVM 1410, and then stored in the low-speed NVM. In this case, the high-speed NVM 1410 essentially acts as a memory buffer for the low-speed NVM 1420.
  • [0044]
    FIG. 7 is a flow chart for use in describing the first assessment and storage (write) of data in the SSD according to another embodiment of the present invention.
  • [0045]
    Initially, at step 300, a write command, an address and data are received. Then, at steps 310 a through 310 e, a determination is made as to whether the received data is to be classified as hot data. If the received data is classified as hot data, and if there is sufficient available space in the high-speed NVM 1410 (step 320), the received data is stored in the high-speed NVM 1410 at step 340. On the other hand, if the received data is not to be classified as hot data, or if there is insufficient available space in the high-speed NVM 1410, the received data is stored in the low-speed NVM 1420 at step 330.
  • [0046]
    There are a number of different ways in which the received data might be classified as hot data, and steps 310 a through 310 e of FIG. 7 represent a non-exhaustive list of decision processes which can be used in the classification. These steps can be used in combinations of two or more, or individually, depending on the desired level of accuracy in the first assessment of the received data.
  • [0047]
    At step 310 a, a determination is made as to whether the operating system (OS) has provided information that the data is hot data. If so, the data is classified as hot data, and the process proceeds to step 320.
  • [0048]
    At step 310 b, a determination is made as to whether the write count of the logical block address has exceeded a predetermined threshold. If so, the data is classified as hot data, and the process proceeds to step 320.
  • [0049]
    At step 310 c, a determination is made as to whether the request size of the data is less then predetermined threshold (e.g., less than 32 KB). If so, the data is classified as hot data, and the process proceeds to step 320.
  • [0050]
    At step 310 d, a determination is made as to whether there is a non-sequential address increment relative to the previously received command. If so, the data is classified as hot data, and the process proceeds to step 320.
  • [0051]
    At step 310 e, a determination is made as to whether a merge operation is likely to be induced in the low-speed NVM. If so, the data is classified as hot data, and the process proceeds to step 320.
  • [0052]
    Although not shown in FIG. 7, in the case where insufficient space exists in the high-speed NVM (step 320), and alternative would be to create available space by migrating already stored cold data of the high-speed NVM to the low-speed NVM, and then storing the new hot data in the high-speed NVM.
  • [0053]
    Also, with reference to above-described processes of FIGS. 6 and 7, it is noted that the embodiments thereof are not limited to storing all of the hot and cold data in the high-speed and low-speed NVMs, respectively. For example, some of the data initially assessed as cold data may be stored in the high-speed NVM. Also, though less preferable, some of the data initially assessed as hot data may be stored in the low-speed NVM.
  • [0054]
    FIG. 8 is a flow chart for use in describing an example of the second assessment and migration of data to the low-speed NVM in the SSD according to an embodiment of the present invention.
  • [0055]
    Initially, at step 410, a determination is made as to whether an unused memory capacity of the high-speed NVM is less than a predetermined threshold value. As suggested previously, this step can be supplemented with (or replaced with) a periodic execution step in which step 410 (or step 420 below) is executed at periodic intervals, and/or with a SSD idle determination step in which step 410 (or step 420) is executed at periodic intervals.
  • [0056]
    Next, at step 420, a determination is made as to whether data stored in the high-speed NVM is hot data, i.e., whether the data may be reclassified as cold data.
  • [0057]
    Then, at step 430, reclassified cold data which stored in the high-speed NVM is migrated to the low-speed NVM.
  • [0058]
    There are a number of different ways in which the determination of step 420 may be executed. For example, it is possible to examine the write count value of each valid data in the high-speed NVM, and to then reclassify data having low write counts as cold data. Alternately, it is possible to carry out a FIFO-type assessment in which old (first come) valid data is reclassified as cold data.
  • [0059]
    With reference to above-described process of FIG. 8, it is noted that the embodiment thereof is not limited to migrating all of the cold data to the low-speed NVM. For example, some of the data assessed as cold data may be retained in the high-speed NVM.
  • [0060]
    FIG. 9 is a block diagram of a computer system according to an embodiment of the present invention. As shown in the figure, a processor (host) 2100 and main memory 2200 communicate over a data bus 2001. Also connected to the bus 2001 are an output device 2500 (e.g., display), an input device 2300 (e.g., keyboard), other I/O devices 2400, and a solid state drive SSD. The solid state drive is configured according to one or more of the previously described embodiments of the invention.
  • [0061]
    Embodiments of the present invention have been described primarily in the context of solid state drives (SSDs). However, the invention is not limited to SSD applications. For example, FIG. 10 illustrates an embodiment where the high-speed memory layer and the low speed memory layer constitute the main memory 2200 of the computer system shown in FIG. 9. In FIG. 10, the high-speed memory layer 1510 includes DRAM cells and may be a hidden region relative to the processor 2100 of FIG. 9. The low-speed memory layer 1520 of FIG. 10 includes flash cells (either SLC or MLC) and may be open relative to the processor 2100 of FIG. 9. FIG. 11 illustrates another example of a main memory 2200. As shown, the high-speed memory layer 1610 includes DRAM cells and may be a hidden region relative to the processor 2100 of FIG. 9, and the low-speed memory layer 1620 includes phase-change random access memory (PRAM) cells and may be open relative to the processor 2100 of FIG. 9.
  • [0062]
    The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the present invention. Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.
Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US5671388 *May 3, 1995Sep 23, 1997Intel CorporationMethod and apparatus for performing write operations in multi-level cell storage device
US5802554 *Mar 5, 1997Sep 1, 1998Panasonic Technologies Inc.Method and system for reducing memory access latency by providing fine grain direct access to flash memory concurrent with a block transfer therefrom
US5966326 *Sep 12, 1997Oct 12, 1999Samsung Electronics, Co., Ltd.Nonvolatile semiconductor memory equipped with single bit and multi-bit cells
US6785767 *Dec 26, 2000Aug 31, 2004Intel CorporationHybrid mass storage system and method with two different types of storage medium
US7457897 *Mar 17, 2004Nov 25, 2008Suoer Talent Electronics, Inc.PCI express-compatible controller and interface for flash memory
US20020051394 *Aug 13, 2001May 2, 2002Tsunehiro TobitaFlash memory control method and apparatus processing system therewith
US20060152981 *Dec 19, 2005Jul 13, 2006Ryu Dong-RyulSolid state disk controller apparatus
US20070011421 *Jul 7, 2005Jan 11, 2007Keller Thomas W JrMethod and system for decreasing power consumption in memory arrays having usage-driven power management
US20070061502 *Dec 28, 2005Mar 15, 2007M-Systems Flash Disk Pioneers Ltd.Flash memory storage system and method
US20090144501 *Jul 13, 2006Jun 4, 2009Samsung Electronics Co., Ltd.Data storage system with complex memory and method of operating the same
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7697326May 10, 2007Apr 13, 2010Anobit Technologies Ltd.Reducing programming error in memory devices
US7751240Jan 24, 2008Jul 6, 2010Anobit Technologies Ltd.Memory device with negative thresholds
US7773413Oct 5, 2008Aug 10, 2010Anobit Technologies Ltd.Reliable data storage in analog memory cells in the presence of temperature variations
US7821826Oct 30, 2007Oct 26, 2010Anobit Technologies, Ltd.Memory cell readout using successive approximation
US7864573Feb 23, 2009Jan 4, 2011Anobit Technologies Ltd.Programming analog memory cells for reduced variance after retention
US7881107Apr 12, 2010Feb 1, 2011Anobit Technologies Ltd.Memory device with negative thresholds
US7900102Dec 17, 2007Mar 1, 2011Anobit Technologies Ltd.High-speed programming of memory devices
US7924587Feb 19, 2009Apr 12, 2011Anobit Technologies Ltd.Programming of analog memory cells using a single programming pulse per state transition
US7924613Jul 6, 2009Apr 12, 2011Anobit Technologies Ltd.Data storage in analog memory cells with protection against programming interruption
US7924648Nov 27, 2007Apr 12, 2011Anobit Technologies Ltd.Memory power and performance management
US7925936Jul 11, 2008Apr 12, 2011Anobit Technologies Ltd.Memory device with non-uniform programming levels
US7975192Oct 30, 2007Jul 5, 2011Anobit Technologies Ltd.Reading memory cells using multiple thresholds
US7995388Aug 4, 2009Aug 9, 2011Anobit Technologies Ltd.Data storage using modified voltages
US8000135Sep 13, 2009Aug 16, 2011Anobit Technologies Ltd.Estimation of memory cell read thresholds by sampling inside programming level distribution intervals
US8000141Oct 15, 2008Aug 16, 2011Anobit Technologies Ltd.Compensation for voltage drifts in analog memory cells
US8001320Mar 10, 2008Aug 16, 2011Anobit Technologies Ltd.Command interface for memory devices
US8050086May 10, 2007Nov 1, 2011Anobit Technologies Ltd.Distortion estimation and cancellation in memory devices
US8059457Mar 17, 2009Nov 15, 2011Anobit Technologies Ltd.Memory device with multiple-accuracy read commands
US8060806Aug 27, 2007Nov 15, 2011Anobit Technologies Ltd.Estimation of non-linear distortion in memory devices
US8068360Jul 23, 2008Nov 29, 2011Anobit Technologies Ltd.Reading analog memory cells using built-in multi-threshold commands
US8085586Dec 25, 2008Dec 27, 2011Anobit Technologies Ltd.Wear level estimation in analog memory cells
US8145984May 24, 2011Mar 27, 2012Anobit Technologies Ltd.Reading memory cells using multiple thresholds
US8151163Dec 3, 2007Apr 3, 2012Anobit Technologies Ltd.Automatic defect management in memory devices
US8151166Feb 26, 2008Apr 3, 2012Anobit Technologies Ltd.Reduction of back pattern dependency effects in memory devices
US8156398Feb 3, 2009Apr 10, 2012Anobit Technologies Ltd.Parameter estimation based on error correction code parity check equations
US8156403May 10, 2007Apr 10, 2012Anobit Technologies Ltd.Combined distortion estimation and error correction coding for memory devices
US8169825Sep 1, 2009May 1, 2012Anobit Technologies Ltd.Reliable data storage in analog memory cells subjected to long retention periods
US8174857Dec 30, 2009May 8, 2012Anobit Technologies Ltd.Efficient readout schemes for analog memory cell devices using multiple read threshold sets
US8174905Mar 11, 2010May 8, 2012Anobit Technologies Ltd.Programming orders for reducing distortion in arrays of multi-level analog memory cells
US8208304Nov 15, 2009Jun 26, 2012Anobit Technologies Ltd.Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N
US8209588Dec 11, 2008Jun 26, 2012Anobit Technologies Ltd.Efficient interference cancellation in analog memory cell arrays
US8225181Nov 26, 2008Jul 17, 2012Apple Inc.Efficient re-read operations from memory devices
US8228701Feb 28, 2010Jul 24, 2012Apple Inc.Selective activation of programming schemes in analog memory cell arrays
US8230300Mar 4, 2009Jul 24, 2012Apple Inc.Efficient readout from analog memory cells using data compression
US8234545May 12, 2008Jul 31, 2012Apple Inc.Data storage with incremental redundancy
US8238157Apr 11, 2010Aug 7, 2012Apple Inc.Selective re-programming of analog memory cells
US8239734Oct 15, 2009Aug 7, 2012Apple Inc.Efficient data storage in storage device arrays
US8239735May 10, 2007Aug 7, 2012Apple Inc.Memory Device with adaptive capacity
US8248831Dec 30, 2009Aug 21, 2012Apple Inc.Rejuvenation of analog memory cells
US8259497Aug 6, 2008Sep 4, 2012Apple Inc.Programming schemes for multi-level analog memory cells
US8259506Mar 22, 2010Sep 4, 2012Apple Inc.Database of memory read thresholds
US8261159Oct 28, 2009Sep 4, 2012Apple, Inc.Data scrambling schemes for memory devices
US8270246Nov 4, 2008Sep 18, 2012Apple Inc.Optimized selection of memory chips in multi-chips memory devices
US8369141Mar 11, 2008Feb 5, 2013Apple Inc.Adaptive estimation of memory cell read thresholds
US8397131Dec 30, 2009Mar 12, 2013Apple Inc.Efficient readout schemes for analog memory cell devices
US8400858Aug 22, 2011Mar 19, 2013Apple Inc.Memory device with reduced sense time readout
US8429358Jan 11, 2010Apr 23, 2013Samsung Electronics Co., Ltd.Method and data storage device for processing commands
US8429493Apr 16, 2008Apr 23, 2013Apple Inc.Memory device with internal signap processing unit
US8438334Dec 22, 2009May 7, 2013International Business Machines CorporationHybrid storage subsystem with mixed placement of file contents
US8438361Mar 10, 2010May 7, 2013Seagate Technology LlcLogical block storage in a storage device
US8456905Dec 11, 2008Jun 4, 2013Apple Inc.Efficient data storage in multi-plane memory devices
US8458417Mar 10, 2010Jun 4, 2013Seagate Technology LlcGarbage collection in a storage device
US8479080Jun 24, 2010Jul 2, 2013Apple Inc.Adaptive over-provisioning in memory systems
US8482978Jun 28, 2011Jul 9, 2013Apple Inc.Estimation of memory cell read thresholds by sampling inside programming level distribution intervals
US8495465Sep 27, 2010Jul 23, 2013Apple Inc.Error correction coding over multiple memory pages
US8498151Aug 4, 2009Jul 30, 2013Apple Inc.Data storage in analog memory cells using modified pass voltages
US8527819Oct 12, 2008Sep 3, 2013Apple Inc.Data storage in analog memory cell arrays having erase failures
US8543756 *Jan 27, 2010Sep 24, 2013Marvell World Trade Ltd.Solid-state drive command grouping
US8570804Sep 22, 2011Oct 29, 2013Apple Inc.Distortion estimation and cancellation in memory devices
US8572311Jan 10, 2011Oct 29, 2013Apple Inc.Redundant data storage in multi-die memory systems
US8572423Feb 6, 2011Oct 29, 2013Apple Inc.Reducing peak current in memory systems
US8595591Jul 6, 2011Nov 26, 2013Apple Inc.Interference-aware assignment of programming levels in analog memory cells
US8599611Sep 22, 2011Dec 3, 2013Apple Inc.Distortion estimation and cancellation in memory devices
US8635494 *Apr 30, 2010Jan 21, 2014Taejin Info Tech Co., Ltd.Backup and restoration for a semiconductor storage device
US8645794Jul 28, 2011Feb 4, 2014Apple Inc.Data storage in analog memory cells using a non-integer number of bits per cell
US8677054Dec 9, 2010Mar 18, 2014Apple Inc.Memory management schemes for non-volatile memory devices
US8677203Jan 10, 2011Mar 18, 2014Apple Inc.Redundant data storage schemes for multi-die memory systems
US8694814Sep 12, 2010Apr 8, 2014Apple Inc.Reuse of host hibernation storage space by memory controller
US8694853Apr 17, 2011Apr 8, 2014Apple Inc.Read commands for reading interfering memory cells
US8694854Aug 2, 2011Apr 8, 2014Apple Inc.Read threshold setting based on soft readout statistics
US8700841 *Apr 19, 2010Apr 15, 2014International Business Machines CorporationSub-LUN input/output profiling for SSD devices
US8713244 *May 3, 2012Apr 29, 2014International Business Machines CorporationSub-LUN input/output profiling for SSD devices
US8751733 *Oct 22, 2012Jun 10, 2014Round Rock Research, LlcHybrid memory management
US8767459Jul 28, 2011Jul 1, 2014Apple Inc.Data storage in analog memory cells across word lines using a non-integer number of bits per cell
US8769241Nov 19, 2010Jul 1, 2014Marvell World Trade Ltd.Virtualization of non-volatile memory and hard disk drive as a single logical drive
US8782370Mar 22, 2012Jul 15, 2014Apple Inc.Selective data storage in LSB and MSB pages
US8812775Mar 27, 2012Aug 19, 2014Samsung Electronics Co., Ltd.System and method for controlling nonvolatile memory
US8832354Mar 22, 2010Sep 9, 2014Apple Inc.Use of host system resources by memory controller
US8838916Sep 15, 2011Sep 16, 2014International Business Machines CorporationHybrid data storage management taking into account input/output (I/O) priority
US8856475Jun 29, 2011Oct 7, 2014Apple Inc.Efficient selection of memory blocks for compaction
US8904084 *May 14, 2010Dec 2, 2014Samsung Electronics Co., Ltd.Solid state drive device
US8914600Jul 14, 2014Dec 16, 2014Apple Inc.Selective data storage in LSB and MSB pages
US8924661Jan 17, 2010Dec 30, 2014Apple Inc.Memory system including a controller and processors associated with memory devices
US8949684Sep 1, 2009Feb 3, 2015Apple Inc.Segmented data storage
US8959286Apr 1, 2013Feb 17, 2015International Business Machines CorporationHybrid storage subsystem with mixed placement of file contents
US8984251Dec 4, 2012Mar 17, 2015Apple Inc.Hinting of deleted data from host to storage device
US8996799 *Dec 16, 2009Mar 31, 2015Nec CorporationContent storage system with modified cache write policies
US9021181Sep 14, 2011Apr 28, 2015Apple Inc.Memory management for unifying memory cell conditions by using maximum time intervals
US9052838Nov 4, 2014Jun 9, 2015Samsung Electronics Co., Ltd.Solid state drive device
US9098395 *Sep 2, 2009Aug 4, 2015Phison Electronics Corp.Logical block management method for a flash memory and control circuit storage system using the same
US9098402Dec 21, 2012Aug 4, 2015Intel CorporationTechniques to configure a solid state drive to operate in a storage mode or a memory mode
US9104580Mar 23, 2011Aug 11, 2015Apple Inc.Cache memory for hybrid disk drives
US9122607 *Jun 19, 2013Sep 1, 2015Marvell International Ltd.Hotspot detection and caching for storage devices
US9153337 *Feb 4, 2009Oct 6, 2015Marvell World Trade Ltd.Fatigue management system and method for hybrid nonvolatile solid state memory system
US9164895Jun 25, 2014Oct 20, 2015Marvell World Trade Ltd.Virtualization of solid state drive and mass storage drive devices with hot and cold application monitoring
US9183134Apr 22, 2010Nov 10, 2015Seagate Technology LlcData segregation in a storage device
US9262077May 13, 2015Feb 16, 2016Samsung Electronics Co., Ltd.Solid state drive device
US9280466Sep 9, 2009Mar 8, 2016Kabushiki Kaisha ToshibaInformation processing device including memory management device managing access from processor to memory and memory management method
US9304692 *Sep 20, 2013Apr 5, 2016Marvell World Trade Ltd.Solid-state drive command grouping
US9317429Sep 30, 2011Apr 19, 2016Intel CorporationApparatus and method for implementing a multi-level memory hierarchy over common memory channels
US9342453Sep 30, 2011May 17, 2016Intel CorporationMemory channel that supports near memory and far memory access
US9355109 *Jun 13, 2011May 31, 2016The Research Foundation For The State University Of New YorkMulti-tier caching
US9372625Mar 26, 2013Jun 21, 2016Seagate Technology InternationalController, data storage device, and data communication system having variable communication speed
US9378142Sep 30, 2011Jun 28, 2016Intel CorporationApparatus and method for implementing a multi-level memory hierarchy having different operating modes
US9390004 *May 30, 2014Jul 12, 2016Round Rock Research, LlcHybrid memory management
US9417803 *Jun 28, 2012Aug 16, 2016Apple Inc.Adaptive mapping of logical addresses to memory devices in solid state drives
US9563371 *Jul 26, 2013Feb 7, 2017Globalfoundreis Inc.Self-adjusting phase change memory storage module
US9569351Feb 15, 2011Feb 14, 2017Seagate Technology LlcStoring corresponding data units in a common storage unit
US9594523Mar 20, 2014Mar 14, 2017International Business Machines CorporationSub-LUN input/output profiling for SSD devices
US9600407Sep 30, 2011Mar 21, 2017Intel CorporationGeneration of far memory access signals based on usage statistic tracking
US9600416 *Sep 30, 2011Mar 21, 2017Intel CorporationApparatus and method for implementing a multi-level memory hierarchy
US9606935 *Feb 18, 2014Mar 28, 2017Intel CorporationMethod and apparatus for preventing non-temporal entries from polluting small structures using a transient buffer
US9619408Mar 25, 2016Apr 11, 2017Intel CorporationMemory channel that supports near memory and far memory access
US9684590Feb 15, 2011Jun 20, 2017Seagate Technology LlcStoring corresponding data units in a common storage unit
US9703505 *Dec 17, 2014Jul 11, 2017Teradata Us, Inc.Management of data in multi-storage systems that can include non-volatile and volatile storages
US9710387Jan 27, 2012Jul 18, 2017Intel CorporationGuest instruction to native instruction range based mapping using a conversion look aside buffer of a processor
US9715445Jul 22, 2013Jul 25, 2017Sandisk Technologies LlcFile differentiation based on data block identification
US9720623 *Dec 17, 2014Aug 1, 2017Teradata Us, Inc.Management of data in multi-storage systems that can include non-volatile and volatile storages
US9727455Oct 1, 2015Aug 8, 2017Marvell World Trade Ltd.Method and apparatus for mapping a logical address between memories of a storage drive based on write frequency rankings
US20080148115 *Dec 17, 2007Jun 19, 2008Anobit Technologies Ltd.High-speed programming of memory devices
US20080158958 *Dec 17, 2007Jul 3, 2008Anobit Technologies Ltd.Memory device with reduced reading
US20080219050 *Feb 26, 2008Sep 11, 2008Anobit Technologies Ltd.Reduction of back pattern dependency effects in memory devices
US20080263262 *Mar 10, 2008Oct 23, 2008Anobit Technologies Ltd.Command interface for memory devices
US20080282106 *May 12, 2008Nov 13, 2008Anobit Technologies LtdData storage with incremental redundancy
US20090024905 *May 10, 2007Jan 22, 2009Anobit Technologies Ltd.Combined distortion estimation and error correction coding for memory devices
US20090103358 *May 10, 2007Apr 23, 2009Anobit Technologies Ltd.Reducing programming error in memory devices
US20090106485 *Jul 23, 2008Apr 23, 2009Anobit Technologies Ltd.Reading analog memory cells using built-in multi-threshold commands
US20090138654 *Feb 4, 2009May 28, 2009Pantas SutardjaFatigue management system and method for hybrid nonvolatile solid state memory system
US20090158126 *Dec 11, 2008Jun 18, 2009Anobit Technologies LtdEfficient interference cancellation in analog memory cell arrays
US20090168524 *Dec 25, 2008Jul 2, 2009Anobit Technologies Ltd.Wear level estimation in analog memory cells
US20090199074 *Feb 3, 2009Aug 6, 2009Anobit Technologies Ltd.Parameter estimation based on error correction code parity check equations
US20090213653 *Feb 19, 2009Aug 27, 2009Anobit Technologies LtdProgramming of analog memory cells using a single programming pulse per state transition
US20090228761 *Mar 4, 2009Sep 10, 2009Anobit Technologies LtdEfficient readout from analog memory cells using data compression
US20090240872 *Mar 17, 2009Sep 24, 2009Anobit Technologies LtdMemory device with multiple-accuracy read commands
US20100017564 *Jun 18, 2009Jan 21, 2010Samsung Electronics Co., Ltd.Controller, data storage device, and data communication system having variable communication speed
US20100091535 *Mar 11, 2008Apr 15, 2010Anobit Technologies LtdAdaptive estimation of memory cell read thresholds
US20100115376 *Dec 3, 2007May 6, 2010Anobit Technologies Ltd.Automatic defect management in memory devices
US20100124088 *Nov 15, 2009May 20, 2010Anobit Technologies LtdStorage at m bits/cell density in n bits/cell analog memory cell devices, m>n
US20100157641 *May 10, 2007Jun 24, 2010Anobit Technologies Ltd.Memory device with adaptive capacity
US20100157675 *Mar 11, 2010Jun 24, 2010Anobit Technologies LtdProgramming orders for reducing distortion in arrays of multi-level analog memory cells
US20100165689 *Dec 30, 2009Jul 1, 2010Anobit Technologies LtdRejuvenation of analog memory cells
US20100195390 *Apr 12, 2010Aug 5, 2010Anobit Technologies LtdMemory device with negative thresholds
US20100199033 *Jan 27, 2010Aug 5, 2010Lau NguyenSolid-state drive command grouping
US20100199150 *Oct 12, 2008Aug 5, 2010Anobit Technologies LtdData Storage In Analog Memory Cell Arrays Having Erase Failures
US20100220510 *Nov 4, 2008Sep 2, 2010Anobit Technologies LtdOptimized Selection of Memory Chips in Multi-Chips Memory Devices
US20100250836 *Mar 22, 2010Sep 30, 2010Anobit Technologies LtdUse of Host System Resources by Memory Controller
US20100293319 *May 14, 2010Nov 18, 2010Samsung Electronics Co., Ltd.Solid state drive device
US20110010489 *Sep 2, 2009Jan 13, 2011Phison Electronics Corp.Logical block management method for a flash memory and control circuit storage system using the same
US20110138112 *Nov 19, 2010Jun 9, 2011Hsing-Yi ChiangVirtualization of Storage Devices
US20110153931 *Dec 22, 2009Jun 23, 2011International Business Machines CorporationHybrid storage subsystem with mixed placement of file contents
US20110225346 *Mar 10, 2010Sep 15, 2011Seagate Technology LlcGarbage collection in a storage device
US20110225347 *Mar 10, 2010Sep 15, 2011Seagate Technology LlcLogical block storage in a storage device
US20110225472 *May 24, 2011Sep 15, 2011Anobit Technologies Ltd.Reading memory cells using multiple thresholds
US20110258363 *Apr 19, 2010Oct 20, 2011International Business Machines CorporationSub-lun input/output profiling for ssd devices
US20110314205 *Dec 16, 2009Dec 22, 2011Nec CorporationStorage system
US20120166749 *Sep 7, 2010Jun 28, 2012International Business Machines CorporationData management in solid-state storage devices and tiered storage systems
US20120290779 *Jul 27, 2012Nov 15, 2012International Business Machines CorporationData management in solid-state storage devices and tiered storage systems
US20120303870 *Mar 22, 2012Nov 29, 2012Chul-Sung ParkMemory chip, memory system, and method of accessing the memory chip
US20120311113 *Oct 19, 2010Dec 6, 2012Nec CorporationStorage device
US20130073807 *Oct 22, 2012Mar 21, 2013Round Rock Research, LlcHybrid memory management
US20130073822 *Jun 28, 2012Mar 21, 2013Eran SandelAdaptive mapping of logical addresses to memory devices in solid state drives
US20140025873 *Sep 20, 2013Jan 23, 2014Marvell World Trade Ltd.Solid-state drive command grouping
US20140129767 *Sep 30, 2011May 8, 2014Raj K RamanujanApparatus and method for implementing a multi-level memory hierarchy
US20140281177 *May 30, 2014Sep 18, 2014Micron Technology, Inc.Hybrid memory management
US20140297983 *Mar 19, 2014Oct 2, 2014Fujitsu LimitedMethod of arranging data, information processing apparatus, and recording medium
US20140317351 *Feb 18, 2014Oct 23, 2014Soft Machines, Inc.Method and apparatus for preventing non-temporal entries from polluting small structures using a transient buffer
US20150032979 *Jul 26, 2013Jan 29, 2015International Business Machines CorporationSelf-adjusting phase change memory storage module
US20150186045 *Dec 17, 2014Jul 2, 2015Teradata CorporationManagement of data in multi-storage systems that can include non-volatile and volatile storages
US20150186046 *Dec 17, 2014Jul 2, 2015Teradata CorporationManagement of data in multi-storage systems that can include non-volatile and volatile storages
US20150186047 *Dec 17, 2014Jul 2, 2015Teradata CorporationManagement of data in multi-storage systems that can include non-volatile and volatile storages
US20160011781 *Sep 18, 2015Jan 14, 2016Samsung Electronics Co., Ltd.Memory chip, memory system, and method of accessing the memory chip
US20160232169 *Apr 20, 2016Aug 11, 2016The Research Foundation For The State University Of New YorkMulti-tier caching
USRE46346Mar 26, 2014Mar 21, 2017Apple Inc.Reading memory cells using multiple thresholds
CN102073602A *Dec 14, 2010May 25, 2011鸿富锦精密工业(深圳)有限公司Computer system, connection control device as well as connecting and disconnecting method
EP2417524A1 *Oct 27, 2009Feb 15, 2012Kaminario Tehnologies Ltd.A mass-storage system utilizing auxiliary solid-state storage subsystem
EP2417524A4 *Oct 27, 2009Mar 6, 2013Kaminario Tehnologies LtdA mass-storage system utilizing auxiliary solid-state storage subsystem
EP2455865A1 *Mar 8, 2010May 23, 2012Kabushiki Kaisha ToshibaMemory management device
EP2455865A4 *Mar 8, 2010Dec 10, 2014Toshiba KkMemory management device
EP2525293A1May 14, 2012Nov 21, 2012Apple Inc.Selecitve data storage in LSB and MSB pages of multi-level flash memory devices
WO2011056002A2 *Nov 4, 2010May 12, 2011(주)피스페이스Apparatus and method for managing a file in a distributed storage system
WO2011056002A3 *Nov 4, 2010Nov 10, 2011(주)피스페이스Apparatus and method for managing a file in a distributed storage system
WO2011068699A1 *Nov 19, 2010Jun 9, 2011Marvell World Trade Ltd.Virtualization of storage devices
WO2011076565A1 *Dec 8, 2010Jun 30, 2011International Business Machines CorporationHybrid storage subsystem
WO2013005118A1 *May 13, 2012Jan 10, 2013Apple Inc.Selective data storage in lsb and msb pages
WO2014088749A1Nov 6, 2013Jun 12, 2014Apple Inc.Hinting of deleted data from host to storage device
WO2014099025A1 *Jun 28, 2013Jun 26, 2014Intel CorporationTechniques to configure a solid state drive to operate in a storage mode or a memory mode
WO2014149859A1 *Mar 6, 2014Sep 25, 2014Sandisk Technologies Inc.Data tag sharing from host to storage systems
WO2014209234A1 *Jun 26, 2014Dec 31, 2014Agency For Science, Technology And ResearchMethod and apparatus for hot data region optimized dynamic management
Classifications
U.S. Classification711/103, 711/E12.008, 365/189.17, 365/185.03
International ClassificationG11C16/10, G06F12/02
Cooperative ClassificationG06F3/0649, G06F12/0246, G06F3/0605, G06F3/0659, G11C11/56, G06F12/08, G11C16/10, G06F3/0647, G06F2212/7202, G06F3/0658, G06F2003/0697, G06F3/0604, G06F3/0679
European ClassificationG11C16/10, G06F12/02D2E2, G06F12/08
Legal Events
DateCodeEventDescription
Mar 7, 2008ASAssignment
Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:OH, MOON-WOOK;KIM, DO-GEUN;PARK, CHAN-IK;REEL/FRAME:020620/0723
Effective date: 20080229