US20090140439A1 - Method of manufacturing a chip and a chip stack - Google Patents
Method of manufacturing a chip and a chip stack Download PDFInfo
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- US20090140439A1 US20090140439A1 US12/364,475 US36447509A US2009140439A1 US 20090140439 A1 US20090140439 A1 US 20090140439A1 US 36447509 A US36447509 A US 36447509A US 2009140439 A1 US2009140439 A1 US 2009140439A1
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- chip
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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Definitions
- the present invention relates to a chip, a chip stack, and a method of manufacturing the same, and more particularly, to a chip, a chip stack, and a method of manufacturing the same in which a chip manufacturing process is simplified, chip performance is improved, and a footprint for a chip stack is made small by forming a metal layer protruding from the bottom of a wafer up to a predetermined thickness in a via hole penetrating the wafer to expose the bottom of a pad formed on the wafer.
- SoC system on chip
- SoC technology can only integrate ICs manufactured by the same processes into one chip.
- SoC technology cannot be applied to a metal oxide semiconductor, a bipolar semiconductor, and a RF chip because these IC's are fabricated on different wafers.
- SoP system on package
- Such a chip stack is classified into a package stack and a bare chip stack.
- the bare chip stack has a relatively small footprint and the advantage of small size compared to the package stack.
- the package stack has the disadvantage of involving a bulky process using wire bonding or a chip carrier. This results in large inductance which degrades the performance of ICs. Thus, the chip stack better facilitates miniaturization.
- PCT/US1999-08744 entitled “Chip Stack and Method of Making the same” discloses a conventional chip stack technique using a carrier. The method involves sticking chips by putting a chip on a chip carrier and forming a bump on the carrier.
- conventional art using the chip carrier has the problem of a large footprint.
- U.S. Pat. No. 6,395,630 entitled “Stacked Integrated Circuits” discloses a chip stack technique in which a bump is formed in the chip such that a hole having an aspect ratio of 100 to 200 is formed to penetrate a wafer and a coaxial conductor is formed in the hole using a chemical vapor deposition (CVD) technique.
- CVD chemical vapor deposition
- the conventional art in which the bump is formed in the chip has several problems. These are, it is difficult to form a hole having a high aspect ratio, a process for forming the coaxial conductor in the hole using the CVD technique has a low deposition rate (e.g., 100 ⁇ /min) and requires a long processing time, and an inner conductor process and an outer conductor process should be performed separately.
- the present invention is directed to a chip, a chip stack, and a method of manufacturing the same in which a plurality of chips, which each comprise at least one pad formed on a wafer and a metal layer which protrudes up to a predetermined thickness from the bottom of the wafer in a via hole penetrating the wafer to expose the bottom of the pad, are stacked such that the pad and the metal layer of adjacent chips are bonded.
- a first aspect of the present invention provides a chip, comprising: at least one pad formed on a wafer; and a metal layer formed to protrude up to a predetermined thickness from the bottom of the wafer in a via hole penetrating the wafer to expose the bottom of the pad.
- a second aspect of the present invention provides a chip stack, comprising: a plurality of chips which include at least one pad formed on a wafer and a metal layer formed to protrude up to a predetermined thickness from the bottom of the wafer in a via hole penetrating the wafer to expose the bottom of the pad, wherein the pad and the metal layer of adjacent chips are bonded to each other.
- a third aspect of the present invention provides a method of manufacturing a chip, comprising: (a) depositing a seed metal layer on the entire surface of a wafer on which at least one pad is formed; (b) lapping a lower portion of the wafer so that the wafer has a predetermined thickness and then forming a via hole forming pattern on the exposed wafer; (c) etching the wafer to expose the bottom of the pad using the via hole forming pattern as an etching mask to form a via hole; and (d) forming a plated metal layer to protrude tip to a predetermined thickness from the bottom of the wafer in the via hole to contact the exposed bottom of the pad and then removing the seed metal layer and the via hole forming pattern.
- FIG. 1 is a cross-sectional view of a chip according to an exemplary embodiment of the present invention
- FIG. 2 is a cross-sectional view of a chip stack according to an exemplary embodiment of the present invention.
- FIGS. 3 a to 3 g are cross-sectional views illustrating a method of manufacturing a chip according to an exemplary embodiment of the present invention.
- FIG. 1 is a cross-sectional view of a chip according to an exemplary embodiment of the present invention
- FIG. 2 is a cross-sectional View of a chip stack according to an exemplary embodiment of the present invention.
- the chip of the present invention comprises at least one pad 200 formed on a wafer 100 , a via hole (see 600 in FIG. 3 e ) which penetrates the wafer to expose the bottom of the pad 200 , and a metal layer 700 which protrudes from the bottom of the wafer 100 by a predetermined thickness.
- the chip stack of the present invention has a structure that a plurality of chips are stacked so that the pad 200 and the metal line 700 of adjacent chips are bonded to each other.
- FIG. 2 shows that only three chips are stacked, but the number of chips to be stacked is not limited. That is, two or more chips can be stacked.
- FIGS. 3 a to 3 g are cross-sectional views illustrating a method of manufacturing a chip according to an exemplary embodiment of the present invention.
- At least one pad 200 is formed on a wafer 100 at a regular interval, and then a seed metal layer 300 is deposited on the entire surface of the wafer 100 including the pad 200 .
- the seed metal layer 300 is made of, e.g., titanium/copper (Ti/Cu) and deposited by a sputtering technique.
- the titanium/copper (Ti/Cu) layer is formed to a thickness of about 400 ⁇ to 600 ⁇ /2000 ⁇ to 4000 ⁇ (preferably, about 500 ⁇ /3000 ⁇ ).
- the seed metal layer 300 serves as an electrode when, e.g., an electroplating technique is used to fill a metal layer (see 700 in FIG. 3 f ) in a via hole (see 600 in FIG. 3 e ) which will be described later.
- the bottom surface of the wafer 100 is subjected to a lapping process so that the wafer 100 has a relatively thin thickness of about 100 ⁇ m to 400 ⁇ m (preferably, about 300 ⁇ m).
- the lapping process may reduce a processing time of a dry-etching process for forming the via hole (see 600 in FIG. 3 e ) since it reduces the thickness of the wafer 100 .
- the lapping process may also reduce a plating time when an electroplating technique is used to form the metal layer (see 700 in FIG. 3 f ) in the via hole.
- the thickness of the metal layer 700 can be easily adjusted by reducing an aspect ratio of the via hole 600 .
- an oxide layer 400 is deposited on the exposed bottom of the wafer 100 , and then a photoresist is coated on the oxide layer 400 .
- the photoresist is etched by exposure and developing techniques using a via hole forming mask (not shown) to thereby form a photoresist pattern 500 .
- the oxide layer 400 is etched using the photoresist pattern (see 500 in FIG. 3 c ) as an etching mask, and then the photoresist pattern 500 is removed, thereby forming a pattern 400 ′ for forming a via hole.
- the oxide layer 400 is preferably dry-etched by reactive ion etching (RIE) equipment using, e.g., CF 4 or CHF 3 .
- RIE reactive ion etching
- the wafer 100 is etched using the via hole Forming pattern 400 ′ as an etching mask to expose the bottom of the pad 200 , thereby forming the via hole 600 having a constant aspect ratio (e.g., about 1 to 3).
- a constant aspect ratio e.g., about 1 to 3
- the via hole 600 is formed by a dry etching technique employing the RIE equipment using a gas containing fluorine (F) such as C 4 F 8 and SF 6 to etch silicon (Si) or a gas such as SF 6 and BCl 3 to etch a gallium arsenide (GaAs).
- F fluorine
- Si silicon
- SF 6 and BCl 3 a gas containing fluorine
- GaAs gallium arsenide
- the wafer 100 is mounted in plating equipment of a fountain type to which a lead free solder solution is sprayed, and a plating metal layer 700 is formed in the via hole 600 to protrude up to a predetermined thickness from the bottom of the wafer in the via hole using an electroplating technique so that the plating metal layer 700 contacts the exposed bottom of the pad 200 .
- the metal layer 700 is formed such that a first metal layer is formed to a predetermined thickness by the electroplating technique using a copper plating solution and then a second metal layer is formed on the first metal layer to protrude up to a predetermined thickness from the bottom of the wafer 100 by the electroplating technique using a plating solution which is lead-free and has a low melting point such as stannum/copper (Sn/Cu), stannum (Sn) and stannum/bismuth (Sn/Bi).
- a portion of the metal layer 700 from the bottom of the pad 200 to the bottom of the wafer 100 is referred to as a via metal layer, and a portion of the metal layer which protrudes up to a predetermined thickness From the bottom of the wafer 100 is referred to as a bump.
- the plating speed is fast and uniformity of the plating layer can be adjusted within about 5%, and thus the bump with a thickness of several tens of micrometers ⁇ m can be formed in a short time.
- the seed metal layer 300 and the via hole forming pattern 400 ′ are etched and thus removed, thereby completing the chip having the bump protruding from the bottom of the wafer 100 according to the present invention.
- the chip stack of FIG. 2 can be formed by stacking at least two chips manufactured with reference to FIGS. 3 a to 3 g in the way that the pad 200 and the metal layer 700 are bonded by a fusion bonding technique.
- the protruding bump is formed on the bottom of the wafer 100 , there is no need for flip when the chips are stacked, and since the bump made of a lead free metal has a low melting point of about 220° C., it can be melted on a typical hot plate, leading to high processing efficiency.
- the chips can be stacked using the bump protruding from the bottom of the chip without a conventional adhesive, and the bump serves as a heat path for dissipating heat generated in the chip, and thus the present invention has ant advantage in that heat dissipation efficiency is improved and the footprint is reduced compared to conventional chip stack technology using a wire.
- a chip, a chip stack, and a method of manufacturing the same have an advantage in that at least one pad is formed on the wafer, and the metal layer which protrudes up to a predetermined thickness from the bottom of the wafer is formed in the via hole penetrating the wafer to expose the bottom of the pad, i.e., a signal of the pad is leaded to the bottom of the chip, so that a metal layer, i.e., a bump protruding from the bottom of the wafer can be formed without redistributing the signal line, leading to a simplified manufacturing process.
- the bump protruding from the bottom of the wafer serves as an interconnection point as well as a contact point when the chips are stacked, the bonding length is short and degradation of the chip performance is small compared to the interconnection of the conventional art using wire boding.
- the bump serves as a heat sink for dissipating the heat generated from the chips when the chips are stacked, heat dissipation efficiency is improved.
Abstract
Provided are a chip, a chip stack, and a method of manufacturing the Same. A plurality of chips which each include: at least one pad formed on a wafer; and a metal layer which protrudes up to a predetermined thickness from the bottom of the wafer and is formed in a via hole exposing the bottom of the pad are stacked such that the pad and the metal layer of adjacent chips are bonded. This leads to a simplified manufacturing process, high chip performance and a small footprint for a chip stack.
Description
- This application claims priority to and the benefit of Korean Patent Application No. 2005-89724, filed on Sep. 27, 2005, the disclosure of which is incorporated herein by reference in its entirety.
- 1. Field of the Invention
- The present invention relates to a chip, a chip stack, and a method of manufacturing the same, and more particularly, to a chip, a chip stack, and a method of manufacturing the same in which a chip manufacturing process is simplified, chip performance is improved, and a footprint for a chip stack is made small by forming a metal layer protruding from the bottom of a wafer up to a predetermined thickness in a via hole penetrating the wafer to expose the bottom of a pad formed on the wafer.
- 2. Discussion of Related Art
- The ongoing development of wireless communication and digital multimedia technology, coupled with increasing consumer demand, continues to fuel the trend toward miniaturization, high performance, high integration, and multi-functionality of portable digital electronic devices such as portable phones, personal digital assistants (PDA), and high performance multimedia devices.
- For miniaturization of such portable digital electronic devices, system on chip (SoC) technology, in which integrated circuits (ICs) having different functions are integrated into one chip to function as a system, has been extensively researched.
- However, SoC technology can only integrate ICs manufactured by the same processes into one chip. For example, SoC technology cannot be applied to a metal oxide semiconductor, a bipolar semiconductor, and a RF chip because these IC's are fabricated on different wafers.
- As an alternative to SoC, research into system on package (SoP) technology is currently progressing. SoP integrates ICs not integrated into one chip by SoC. In order to implement SoP technology, a method of stacking ICs to be mounted has been suggested as a way to reduce a footprint of the ICs.
- Such a chip stack is classified into a package stack and a bare chip stack. The bare chip stack has a relatively small footprint and the advantage of small size compared to the package stack.
- Many chip stacking methods have been suggested to date. The package stack has the disadvantage of involving a bulky process using wire bonding or a chip carrier. This results in large inductance which degrades the performance of ICs. Thus, the chip stack better facilitates miniaturization.
- PCT/US1999-08744, entitled “Chip Stack and Method of Making the same” discloses a conventional chip stack technique using a carrier. The method involves sticking chips by putting a chip on a chip carrier and forming a bump on the carrier. However, conventional art using the chip carrier has the problem of a large footprint.
- U.S. Pat. No. 6,395,630, entitled “Stacked Integrated Circuits” discloses a chip stack technique in which a bump is formed in the chip such that a hole having an aspect ratio of 100 to 200 is formed to penetrate a wafer and a coaxial conductor is formed in the hole using a chemical vapor deposition (CVD) technique.
- However, the conventional art in which the bump is formed in the chip has several problems. These are, it is difficult to form a hole having a high aspect ratio, a process for forming the coaxial conductor in the hole using the CVD technique has a low deposition rate (e.g., 100 Å/min) and requires a long processing time, and an inner conductor process and an outer conductor process should be performed separately.
- The present invention is directed to a chip, a chip stack, and a method of manufacturing the same in which a plurality of chips, which each comprise at least one pad formed on a wafer and a metal layer which protrudes up to a predetermined thickness from the bottom of the wafer in a via hole penetrating the wafer to expose the bottom of the pad, are stacked such that the pad and the metal layer of adjacent chips are bonded. This leads to a simplified manufacturing process, high chip performance and a small footprint for a chip stack.
- A first aspect of the present invention provides a chip, comprising: at least one pad formed on a wafer; and a metal layer formed to protrude up to a predetermined thickness from the bottom of the wafer in a via hole penetrating the wafer to expose the bottom of the pad.
- A second aspect of the present invention provides a chip stack, comprising: a plurality of chips which include at least one pad formed on a wafer and a metal layer formed to protrude up to a predetermined thickness from the bottom of the wafer in a via hole penetrating the wafer to expose the bottom of the pad, wherein the pad and the metal layer of adjacent chips are bonded to each other.
- A third aspect of the present invention provides a method of manufacturing a chip, comprising: (a) depositing a seed metal layer on the entire surface of a wafer on which at least one pad is formed; (b) lapping a lower portion of the wafer so that the wafer has a predetermined thickness and then forming a via hole forming pattern on the exposed wafer; (c) etching the wafer to expose the bottom of the pad using the via hole forming pattern as an etching mask to form a via hole; and (d) forming a plated metal layer to protrude tip to a predetermined thickness from the bottom of the wafer in the via hole to contact the exposed bottom of the pad and then removing the seed metal layer and the via hole forming pattern.
- The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail preferred embodiments thereof with reference to the attached drawings in which:
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FIG. 1 is a cross-sectional view of a chip according to an exemplary embodiment of the present invention; -
FIG. 2 is a cross-sectional view of a chip stack according to an exemplary embodiment of the present invention; and -
FIGS. 3 a to 3 g are cross-sectional views illustrating a method of manufacturing a chip according to an exemplary embodiment of the present invention. - Hereinafter, an exemplary embodiment of the present invention will be described in detail. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various types. Therefore, the present embodiment is provided for complete disclosure of the present invention and to fully inform the scope of the present invention to those ordinarily skilled in the art.
-
FIG. 1 is a cross-sectional view of a chip according to an exemplary embodiment of the present invention, andFIG. 2 is a cross-sectional View of a chip stack according to an exemplary embodiment of the present invention. - Referring to
FIG. 1 , the chip of the present invention comprises at least onepad 200 formed on awafer 100, a via hole (see 600 inFIG. 3 e) which penetrates the wafer to expose the bottom of thepad 200, and ametal layer 700 which protrudes from the bottom of thewafer 100 by a predetermined thickness. - Referring to
FIG. 2 , the chip stack of the present invention has a structure that a plurality of chips are stacked so that thepad 200 and themetal line 700 of adjacent chips are bonded to each other. - For the convenience of description,
FIG. 2 shows that only three chips are stacked, but the number of chips to be stacked is not limited. That is, two or more chips can be stacked. -
FIGS. 3 a to 3 g are cross-sectional views illustrating a method of manufacturing a chip according to an exemplary embodiment of the present invention. - Referring to
FIG. 3 a, at least onepad 200 is formed on awafer 100 at a regular interval, and then aseed metal layer 300 is deposited on the entire surface of thewafer 100 including thepad 200. Theseed metal layer 300 is made of, e.g., titanium/copper (Ti/Cu) and deposited by a sputtering technique. The titanium/copper (Ti/Cu) layer is formed to a thickness of about 400 Å to 600 Å/2000Å to 4000 Å (preferably, about 500 Å/3000 Å). - The
seed metal layer 300 serves as an electrode when, e.g., an electroplating technique is used to fill a metal layer (see 700 inFIG. 3 f) in a via hole (see 600 inFIG. 3 e) which will be described later. - Referring to
FIG. 3 b, the bottom surface of thewafer 100 is subjected to a lapping process so that thewafer 100 has a relatively thin thickness of about 100 μm to 400 μm (preferably, about 300 μm). - The lapping process may reduce a processing time of a dry-etching process for forming the via hole (see 600 in
FIG. 3 e) since it reduces the thickness of thewafer 100. The lapping process may also reduce a plating time when an electroplating technique is used to form the metal layer (see 700 inFIG. 3 f) in the via hole. In addition, the thickness of themetal layer 700 can be easily adjusted by reducing an aspect ratio of thevia hole 600. - Referring to
FIG. 3 c, anoxide layer 400 is deposited on the exposed bottom of thewafer 100, and then a photoresist is coated on theoxide layer 400. The photoresist is etched by exposure and developing techniques using a via hole forming mask (not shown) to thereby form aphotoresist pattern 500. - Referring to
FIG. 3 d, theoxide layer 400 is etched using the photoresist pattern (see 500 inFIG. 3 c) as an etching mask, and then thephotoresist pattern 500 is removed, thereby forming apattern 400′ for forming a via hole. - Here, the
oxide layer 400 is preferably dry-etched by reactive ion etching (RIE) equipment using, e.g., CF4 or CHF3. - Referring to
FIG. 3 e, thewafer 100 is etched using the viahole Forming pattern 400′ as an etching mask to expose the bottom of thepad 200, thereby forming thevia hole 600 having a constant aspect ratio (e.g., about 1 to 3). - Preferably, the
via hole 600 is formed by a dry etching technique employing the RIE equipment using a gas containing fluorine (F) such as C4F8 and SF6 to etch silicon (Si) or a gas such as SF6 and BCl3 to etch a gallium arsenide (GaAs). - Referring to
FIG. 3 f, thewafer 100 is mounted in plating equipment of a fountain type to which a lead free solder solution is sprayed, and a platingmetal layer 700 is formed in thevia hole 600 to protrude up to a predetermined thickness from the bottom of the wafer in the via hole using an electroplating technique so that the platingmetal layer 700 contacts the exposed bottom of thepad 200. - At this time, the
metal layer 700 is formed such that a first metal layer is formed to a predetermined thickness by the electroplating technique using a copper plating solution and then a second metal layer is formed on the first metal layer to protrude up to a predetermined thickness from the bottom of thewafer 100 by the electroplating technique using a plating solution which is lead-free and has a low melting point such as stannum/copper (Sn/Cu), stannum (Sn) and stannum/bismuth (Sn/Bi). - Here, a portion of the
metal layer 700 from the bottom of thepad 200 to the bottom of thewafer 100 is referred to as a via metal layer, and a portion of the metal layer which protrudes up to a predetermined thickness From the bottom of thewafer 100 is referred to as a bump. - When the
metal layer 700 is formed by the electroplating technique, the plating speed is fast and uniformity of the plating layer can be adjusted within about 5%, and thus the bump with a thickness of several tens of micrometers μm can be formed in a short time. - Referring to
FIG. 3 g, theseed metal layer 300 and the viahole forming pattern 400′ are etched and thus removed, thereby completing the chip having the bump protruding from the bottom of thewafer 100 according to the present invention. - The chip stack of
FIG. 2 can be formed by stacking at least two chips manufactured with reference toFIGS. 3 a to 3 g in the way that thepad 200 and themetal layer 700 are bonded by a fusion bonding technique. - As described above, since the protruding bump is formed on the bottom of the
wafer 100, there is no need for flip when the chips are stacked, and since the bump made of a lead free metal has a low melting point of about 220° C., it can be melted on a typical hot plate, leading to high processing efficiency. - The chips can be stacked using the bump protruding from the bottom of the chip without a conventional adhesive, and the bump serves as a heat path for dissipating heat generated in the chip, and thus the present invention has ant advantage in that heat dissipation efficiency is improved and the footprint is reduced compared to conventional chip stack technology using a wire.
- As described above, according to the present invention, a chip, a chip stack, and a method of manufacturing the same have an advantage in that at least one pad is formed on the wafer, and the metal layer which protrudes up to a predetermined thickness from the bottom of the wafer is formed in the via hole penetrating the wafer to expose the bottom of the pad, i.e., a signal of the pad is leaded to the bottom of the chip, so that a metal layer, i.e., a bump protruding from the bottom of the wafer can be formed without redistributing the signal line, leading to a simplified manufacturing process.
- Further, since the bump protruding from the bottom of the wafer serves as an interconnection point as well as a contact point when the chips are stacked, the bonding length is short and degradation of the chip performance is small compared to the interconnection of the conventional art using wire boding.
- Furthermore, it is easy to stack the chips and it is possible to stack the chips using the bump, and thus the footprint for the chip stack can be small, and since the bump serves as a heat sink for dissipating the heat generated from the chips when the chips are stacked, heat dissipation efficiency is improved.
- While the invention has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made Therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (4)
1. A chip, comprising:
at least one pad formed on a wafer; and
a metal layer formed to protrude up to a predetermined thickness from the bottom of the wafer in a via hole penetrating the wafer to expose the bottom of the pad.
2. The chip of claim 1 , wherein the via hole has an aspect ratio of 1 to 3.
3. The chip of claim 1 , wherein the metal layer includes a first metal layer formed to a predetermined thickness from the exposed bottom of the pad using a copper and a second metal layer formed on the first metal layer to protrude up to a predetermined thickness from the bottom of the wafer using one of stannum/copper (Sn/Cu), stannum (Sn) and stannum/bismuth (Sn/Bi).
4. A chip stack, comprising:
a plurality of chips which include at least one pad formed on a wafer and a metal layer formed to protrude Up to a predetermined thickness from the bottom of the wafer in a via hole penetrating the wafer to expose the bottom of the pad,
wherein the pad and the metal layer of adjacent chips are bonded to each other.
Priority Applications (1)
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US12/364,475 US20090140439A1 (en) | 2005-09-27 | 2009-02-02 | Method of manufacturing a chip and a chip stack |
Applications Claiming Priority (4)
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KR1020050089724A KR100713121B1 (en) | 2005-09-27 | 2005-09-27 | Chip and a chip stack using the same and a method for manufacturing the same |
KR2005-89724 | 2005-09-27 | ||
US11/499,116 US7494909B2 (en) | 2005-09-27 | 2006-08-03 | Method of manufacturing a chip |
US12/364,475 US20090140439A1 (en) | 2005-09-27 | 2009-02-02 | Method of manufacturing a chip and a chip stack |
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US11/499,116 Division US7494909B2 (en) | 2005-09-27 | 2006-08-03 | Method of manufacturing a chip |
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US11/499,116 Expired - Fee Related US7494909B2 (en) | 2005-09-27 | 2006-08-03 | Method of manufacturing a chip |
US12/364,475 Abandoned US20090140439A1 (en) | 2005-09-27 | 2009-02-02 | Method of manufacturing a chip and a chip stack |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080311719A1 (en) * | 2002-08-15 | 2008-12-18 | Tang Sanh D | Method Of Forming A Field Effect Transistor |
US20120252203A1 (en) * | 2011-03-31 | 2012-10-04 | Globalfoundries Inc. | Controlled electroplated solder bumps |
US10515801B2 (en) | 2007-06-04 | 2019-12-24 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100713121B1 (en) * | 2005-09-27 | 2007-05-02 | 한국전자통신연구원 | Chip and a chip stack using the same and a method for manufacturing the same |
KR101176187B1 (en) | 2007-11-21 | 2012-08-22 | 삼성전자주식회사 | Stacked semiconductor device and method for thereof serial path build up |
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US8536693B2 (en) | 2010-07-20 | 2013-09-17 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Tiered integrated circuit assembly and a method for manufacturing the same |
KR101144082B1 (en) * | 2012-01-26 | 2012-05-23 | 한국기계연구원 | Semiconductor chip stack package and manufacturing method thereof |
CN105590906B (en) * | 2016-01-11 | 2019-02-01 | 江苏科技大学 | It is a kind of for being fanned out to the radiating component and manufacturing method of formula wafer level packaging |
KR102323877B1 (en) | 2016-09-28 | 2021-11-10 | 한국전자통신연구원 | Apparatus for electroplating |
Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6395630B2 (en) * | 1998-11-23 | 2002-05-28 | Micron Technology, Inc. | Stacked integrated circuits |
US6864171B1 (en) * | 2003-10-09 | 2005-03-08 | Infineon Technologies Ag | Via density rules |
US7126214B2 (en) * | 2001-12-05 | 2006-10-24 | Arbor Company Llp | Reconfigurable processor module comprising hybrid stacked integrated circuit die elements |
US20070072419A1 (en) * | 2005-09-27 | 2007-03-29 | Electronics And Telecommunications Research Institute | Chip, ship stack, and method of manufacturing the same |
US7514276B1 (en) * | 2008-08-12 | 2009-04-07 | International Business Machines Corporation | Aligning stacked chips using resistance assistance |
US7528006B2 (en) * | 2005-06-30 | 2009-05-05 | Intel Corporation | Integrated circuit die containing particle-filled through-silicon metal vias with reduced thermal expansion |
US7663231B2 (en) * | 2007-06-13 | 2010-02-16 | Industrial Technology Research Institute | Image sensor module with a three-dimensional die-stacking structure |
US7666768B2 (en) * | 2006-09-29 | 2010-02-23 | Intel Corporation | Through-die metal vias with a dispersed phase of graphitic structures of carbon for reduced thermal expansion and increased electrical conductance |
US7683459B2 (en) * | 2008-06-02 | 2010-03-23 | Hong Kong Applied Science and Technology Research Institute Company, Ltd. | Bonding method for through-silicon-via based 3D wafer stacking |
US7692278B2 (en) * | 2006-12-20 | 2010-04-06 | Intel Corporation | Stacked-die packages with silicon vias and surface activated bonding |
US7775119B1 (en) * | 2009-03-03 | 2010-08-17 | S3C, Inc. | Media-compatible electrically isolated pressure sensor for high temperature applications |
US7786584B2 (en) * | 2007-11-26 | 2010-08-31 | Infineon Technologies Ag | Through substrate via semiconductor components |
US7834440B2 (en) * | 2008-09-29 | 2010-11-16 | Hitachi, Ltd. | Semiconductor device with stacked memory and processor LSIs |
US7843064B2 (en) * | 2007-12-21 | 2010-11-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and process for the formation of TSVs |
US7851346B2 (en) * | 2008-07-21 | 2010-12-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonding metallurgy for three-dimensional interconnect |
US7855455B2 (en) * | 2008-09-26 | 2010-12-21 | International Business Machines Corporation | Lock and key through-via method for wafer level 3 D integration and structures produced |
US20110050320A1 (en) * | 2009-09-02 | 2011-03-03 | Mosaid Technologies Incorporated | Using interrupted through-silicon-vias in integrated circuits adapted for stacking |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000294677A (en) * | 1999-04-05 | 2000-10-20 | Fujitsu Ltd | High-density thin film wiring board and its manufacture |
US6261943B1 (en) * | 2000-02-08 | 2001-07-17 | Nec Research Institute, Inc. | Method for fabricating free-standing thin metal films |
KR100345166B1 (en) * | 2000-08-05 | 2002-07-24 | 주식회사 칩팩코리아 | Wafer level stack package and method of fabricating the same |
US6607941B2 (en) * | 2002-01-11 | 2003-08-19 | National Semiconductor Corporation | Process and structure improvements to shellcase style packaging technology |
AU2003227514A1 (en) * | 2002-06-07 | 2003-12-22 | Oticon A/S | Feed-through process and amplifier with feed-through |
US7399683B2 (en) * | 2002-06-18 | 2008-07-15 | Sanyo Electric Co., Ltd. | Manufacturing method of semiconductor device |
US6784544B1 (en) * | 2002-06-25 | 2004-08-31 | Micron Technology, Inc. | Semiconductor component having conductors with wire bondable metalization layers |
JP2004228392A (en) * | 2003-01-24 | 2004-08-12 | Seiko Epson Corp | Manufacturing method of semiconductor device and manufacturing method of semiconductor module |
KR100537892B1 (en) * | 2003-08-26 | 2005-12-21 | 삼성전자주식회사 | Chip stack package and manufacturing method thereof |
EP1515364B1 (en) * | 2003-09-15 | 2016-04-13 | Nuvotronics, LLC | Device package and methods for the fabrication and testing thereof |
US7410833B2 (en) * | 2004-03-31 | 2008-08-12 | International Business Machines Corporation | Interconnections for flip-chip using lead-free solders and having reaction barrier layers |
US7195981B2 (en) * | 2004-08-23 | 2007-03-27 | Enpirion, Inc. | Method of forming an integrated circuit employable with a power converter |
US7199050B2 (en) * | 2004-08-24 | 2007-04-03 | Micron Technology, Inc. | Pass through via technology for use during the manufacture of a semiconductor device |
KR100604049B1 (en) * | 2004-09-01 | 2006-07-24 | 동부일렉트로닉스 주식회사 | Semiconductor package and method for fabricating the same |
JP2006286966A (en) * | 2005-03-31 | 2006-10-19 | Fujitsu Ltd | Semiconductor device and production management method thereof |
US7772116B2 (en) * | 2005-09-01 | 2010-08-10 | Micron Technology, Inc. | Methods of forming blind wafer interconnects |
-
2005
- 2005-09-27 KR KR1020050089724A patent/KR100713121B1/en not_active IP Right Cessation
-
2006
- 2006-08-03 US US11/499,116 patent/US7494909B2/en not_active Expired - Fee Related
-
2009
- 2009-02-02 US US12/364,475 patent/US20090140439A1/en not_active Abandoned
Patent Citations (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6395630B2 (en) * | 1998-11-23 | 2002-05-28 | Micron Technology, Inc. | Stacked integrated circuits |
US7126214B2 (en) * | 2001-12-05 | 2006-10-24 | Arbor Company Llp | Reconfigurable processor module comprising hybrid stacked integrated circuit die elements |
US7282951B2 (en) * | 2001-12-05 | 2007-10-16 | Arbor Company Llp | Reconfigurable processor module comprising hybrid stacked integrated circuit die elements |
US6864171B1 (en) * | 2003-10-09 | 2005-03-08 | Infineon Technologies Ag | Via density rules |
US7528006B2 (en) * | 2005-06-30 | 2009-05-05 | Intel Corporation | Integrated circuit die containing particle-filled through-silicon metal vias with reduced thermal expansion |
US20070072419A1 (en) * | 2005-09-27 | 2007-03-29 | Electronics And Telecommunications Research Institute | Chip, ship stack, and method of manufacturing the same |
US7494909B2 (en) * | 2005-09-27 | 2009-02-24 | Electronics And Telecommunications Research Institute | Method of manufacturing a chip |
US7666768B2 (en) * | 2006-09-29 | 2010-02-23 | Intel Corporation | Through-die metal vias with a dispersed phase of graphitic structures of carbon for reduced thermal expansion and increased electrical conductance |
US7692278B2 (en) * | 2006-12-20 | 2010-04-06 | Intel Corporation | Stacked-die packages with silicon vias and surface activated bonding |
US7663231B2 (en) * | 2007-06-13 | 2010-02-16 | Industrial Technology Research Institute | Image sensor module with a three-dimensional die-stacking structure |
US7786584B2 (en) * | 2007-11-26 | 2010-08-31 | Infineon Technologies Ag | Through substrate via semiconductor components |
US7843064B2 (en) * | 2007-12-21 | 2010-11-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and process for the formation of TSVs |
US7683459B2 (en) * | 2008-06-02 | 2010-03-23 | Hong Kong Applied Science and Technology Research Institute Company, Ltd. | Bonding method for through-silicon-via based 3D wafer stacking |
US7851346B2 (en) * | 2008-07-21 | 2010-12-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonding metallurgy for three-dimensional interconnect |
US7514276B1 (en) * | 2008-08-12 | 2009-04-07 | International Business Machines Corporation | Aligning stacked chips using resistance assistance |
US7855455B2 (en) * | 2008-09-26 | 2010-12-21 | International Business Machines Corporation | Lock and key through-via method for wafer level 3 D integration and structures produced |
US7834440B2 (en) * | 2008-09-29 | 2010-11-16 | Hitachi, Ltd. | Semiconductor device with stacked memory and processor LSIs |
US7775119B1 (en) * | 2009-03-03 | 2010-08-17 | S3C, Inc. | Media-compatible electrically isolated pressure sensor for high temperature applications |
US20110050320A1 (en) * | 2009-09-02 | 2011-03-03 | Mosaid Technologies Incorporated | Using interrupted through-silicon-vias in integrated circuits adapted for stacking |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080311719A1 (en) * | 2002-08-15 | 2008-12-18 | Tang Sanh D | Method Of Forming A Field Effect Transistor |
US8440515B2 (en) * | 2002-08-15 | 2013-05-14 | Micron Technology, Inc. | Method of forming a field effect transistor |
US20130230959A1 (en) * | 2002-08-15 | 2013-09-05 | Micron Technology, Inc. | Method of Forming a Field Effect Transistor Having Source/Drain Material Over Insulative Material |
US8802520B2 (en) * | 2002-08-15 | 2014-08-12 | Micron Technology, Inc. | Method of forming a field effect transistor having source/drain material over insulative material |
US10515801B2 (en) | 2007-06-04 | 2019-12-24 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
US20120252203A1 (en) * | 2011-03-31 | 2012-10-04 | Globalfoundries Inc. | Controlled electroplated solder bumps |
US8741765B2 (en) * | 2011-03-31 | 2014-06-03 | Globalfoundries Inc. | Controlled electroplated solder bumps |
Also Published As
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US20070072419A1 (en) | 2007-03-29 |
US7494909B2 (en) | 2009-02-24 |
KR20070035175A (en) | 2007-03-30 |
KR100713121B1 (en) | 2007-05-02 |
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