US 20090238016 A1
Various embodiments include method and apparatus for receiving a clock signal, determining a number of delay elements based on a relationship between the clock signal and a delayed feedback signal generated based on the clock signal, calculating an amount of time corresponding to the number of delay elements, and delaying a control signal by the amount of time to generate an additional clock signal, the control signal having a frequency higher than a frequency of the clock signal. Other embodiments are described.
1. A method comprising:
receiving a clock signal;
determining a number of delay elements based on a relationship between the clock signal and a delayed feedback signal generated based on the clock signal;
calculating an amount of time corresponding to the number of delay elements; and
delaying a control signal by the amount of time to generate an additional clock signal, the control signal having a frequency higher than a frequency of the clock signal.
2. The method of
receiving an input signal; and
multiplying a frequency of the input signal by a frequency ratio less than one to generate the clock signal such that the frequency of the clock signal is less than the frequency of the input signal.
3. The method of
receiving an input signal; and
multiplying a frequency of the input signal by a frequency ratio greater than one to generate the clock signal such that the frequency of the clock signal is greater than the frequency of the input signal.
4. The method of
controlling a reading of data from a memory device using the additional clock signal.
5. The method of
6. The method of
generating the clock signal based on an input signal that has a frequency equal to the frequency of the control signal.
7. The method of
delaying the clock signal to generate a feedback signal;
delaying the feedback signal to generate a delayed feedback signal; and
sampling the clock signal and the delayed feedback signal to determine the number of delay elements based on a phase difference between the clock signal and delayed feedback signal.
8. A method comprising:
receiving a first clock signal;
generating a second clock signal based on the first clock signal;
determining a number of delay elements corresponding to an amount of a period of the second clock signal;
calculating an amount of time corresponding to the number of delay elements;
receiving a control signal having a frequency higher than a frequency of the second clock signal; and
delaying the control signal by the amount of time corresponding to the number of delay elements.
9. The method of
10. The method of
11. The method of
12. The method of
13. The method of
14. The method of
15. The method of
16. An apparatus comprising:
a first circuit to receive a first clock signal to generate a second clock signal based on the first clock signal;
a second circuit including plurality of delay elements to delay the second clock signal with a number of delay element among the plurality of delay elements;
a third circuit to calculate an amount of time corresponding to the number of delay elements; and
a delay circuit to receive a control signal having a frequency higher than a frequency of the second signal and to delay the control signal by the amount of time corresponding to the number of delay elements.
17. The apparatus of
18. The apparatus of
19. The apparatus of
20. The apparatus of
This application is a continuation of U.S. patent application Ser. No. 11/466,311, filed on Aug. 22, 2006, which is incorporated herein by reference in its entirety.
The present embodiments of the invention relate to dynamic-random-access-memory (DDR-SDRAM) devices, including circuitry to control timing signals to capture data and data.
DDR-SDRAM devices can transfer data twice as fast as single-data-rate SDRAM memory devices (SDR-SDRAM). This is because DDR-SDRAM devices can send and receive signals twice per clock cycle. This feature increases the complexity of writing data to and reading data from the DDR-SDRAM device since the valid-data window is narrower than in SDR-SDRAM devices.
Referring now to
In an application system, for example a microcontroller circuit connected to DDR-SDRAM devices on a printed circuit board, the signal DQS is a bidirectional control signal transmitted by the DDR-SDRAM devices during read operations and by the memory controller during write operations. The memory controller may be part of a microcontroller integrated circuit. For DDR device circuitry optimization, the DQS signal is provided edge-aligned with data for read operations and should be center-aligned with data for write operations. The DQS signal and its relationship to the valid data windows of a DDR-SDRAM in a typical write operation is shown in
To write data to DDR-SDRAM devices without increasing the complexity of the DDR-SDRAM controller and to guaranty that the signal is center-aligned with data, it is possible to use the falling edge of a clock signal running at twice the frequency of the clock that drives the DDR-SDRAM devices. This aspect of operation of a DDR-SDRAM device is shown with reference to
As also shown in
During read operation, the DQS signal is edge-aligned with data, the controller delays the DQS signal by a period of time corresponding to about ¼ of the DDR device clock period to allow alignment of the delayed DQS signal with the center of the valid data window. Under this condition, the data from the DDR device can be properly sampled because the hold/setup time margins are optimal (middle of data valid window, 321, 322, 331, 332). Of course, the delay must be stable.
A simple delay circuitry having DQS as its input and formed from a delay line of cascaded basic cell elements such as buffers or inverters does not guaranty a stable delay because basic element intrinsic delay depends on de-rating factors such as process, voltage, and temperature variations.
The present embodiments of the invention are used to delay the DQS signal provided by DDR-SDRAM devices in order to sample DDR data. The present embodiments of the invention will typically operate in a DDR-SDRAM controller that interlaces with a DDR-SDRAM device. The DDR-SDRAM controller is a digital circuitry that can be found in many standard micro-controllers.
A circuit according to the present embodiments of the invention for delaying an input control signal, comprises a clock circuit to generate a clock signal having a frequency different from an input clock signal to delay and including a clock signal input, a derivative clock signal output, an input to program a frequency ratio between its input clock frequency and its output clock frequency. A clock capturing circuit provides a determined number of delay elements required to provide a delay of an amount of the period of the signal provided by the clock circuit. A delay calculation circuit receives the determined number of delay elements and calculates a number of delay elements needed to delay the input control signal by an amount of time. A delay circuit includes a control signal input, a select input for receiving the number of delay elements provided by the delay calculation circuit.
During read operation, the DQS signal is edge-aligned with data. According to the present embodiments of the invention, the controller must delay the DQS signal by a theoretical period of time corresponding to ¼ of the DDR device clock period. Due to different derating factors, the DQS and DATA signals are not 100% edge aligned in real life operations, and therefore the delay value must be adjustable around ¼ of the DDR device clock period. Under this condition, the data from the DDR device can be properly sampled because the hold/setup time margins are optimally located in the middle of the data-valid window.
The logic to delay a signal by a known stable amount of time is a delay locked loop acting as master circuitry to calculate the number of cascaded basic elements required to produce a known delay and keep it stable with respect to conditions such as process variations, voltage, and temperature. The master circuitry drives a slave delay circuit that applies the required and stable delay to the DQS signal. The master circuitry (DLL) allows determination of a stable delay (about ¼ of a clock period) regardless of the derating factors (e.g., process, voltage and temperature). The time reference entered into the master circuitry is a clock signal whose frequency is a fraction of the DDR device clock frequency (e.g., ¼, ⅓, or ⅕ of the DDR clock). The DQS and data phases relative to the DDR device clock may vary from one printed circuit board to another due to their different topologies and differences in internal circuitry topologies of the memory devices. The DQS phase may also vary due to derating factors such voltage drops.
The slave circuitry delays the DQS signal by the stable delay (about ¼ DDR clock period). Therefore the output of the slave circuitry can be used as data sampling command. The DLL circuitry determines the number of basic elements such as buffers or inverters to be cascaded to delay the DQS signal by a given amount of time (about ¼ of the DDR clock). The number of delay elements may be modified/adjusted on the fly to obtain a stable delay.
The present embodiments of the invention avoid the use of circuitry containing analog cells which are touchy in terms of noise, foundry testability, consumption, and portability over different technologies.
Persons of ordinary skill in the art will realize that the following description of specific embodiments of present invention is illustrative only and not in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons.
Referring now to
As may be seen from an examination of
To make the DQS signal delay stable, a programmable delay line must be used and tuned with regard to variations in the derating factor. This tuning will be automatically performed by a locked loop circuit. Therefore a programmable delay line more complex than a simple delay line is used in the present embodiments of the invention. Such a programmable delay line employs a programmable number of basic delay units as will be disclosed herein. Independent master circuitry is used to keep track of the derating variations to select, in real-time, the number of basic delay elements used in the programmable delay line to provide a given delay for the DQS signal input.
The respective DQS and data phases may also vary from one printed circuit board to another due to different printed circuit board topologies and different internal circuit topologies of memory devices, resulting in the necessity to tune the delay applied to the DQS signal. The phase of the DQS signal may also vary due to de-rating factors such internal or external voltage drops. This kind of tuning, used to modify the delay amount, is totally different from automatic tuning of the master locked circuitry. The tuning performed by the present embodiments of the invention provides the capability to adjust a delay around the theoretical value of ¼ of the clock period.
Independent master circuitry is provided with a stable delay reference and locks on to the stable delay reference using a number of basic delay cells identical to the programmable delay line used to delay the DQS signal input. The locked system ensures tracking variations in the derating factor.
The stable time reference entered into the master circuitry is the clock signal of the DDR-SDRAM memory controller or a clock signal having a frequency which is a sub-multiple (divided by 2, etc.) of the frequency of the memory controller to make the DQS delay circuitry more simple to design and to make the reference entered into the master circuitry more predictable especially when duty-cycle of the DDR-SDRAM controller may not be stable or different from a known value such as 50%.
The slave circuitry receives the DQS signal as input and delays it by the stable delay (about ¼ DDR clock period, subject to fine tuning to match DQS and data phase variations). Therefore the output of the slave circuitry driven by the master circuitry can be used as data sampling command.
Referring now to
Block 42 allows obtaining a programmable reference delay by employing circuitry that multiplies the input frequency on line 50 by the programmable ratio N/M in multiplier 52, whose output has a frequency value equal to [(N/M)*Finput], where Finput is the input frequency on line 50. The output of block 42 is the system clock of the DQS delay circuitry 40 and will act as a reference signal delay.
This programmable value allows modification of the optimal data sampling point. The theoretical value of the optimal data sampling point is ¼ of the DDR-SDRAM clock period, but due to different printed circuit boards on which data and DQS signals are routed with different wire lengths and/or capacitances, plus differences in the internal circuits of the memory devices, the terminal points of these signals may be differently phased. Therefore, the optimal sampling point will be nominally about ¼ of the clock period but may end up to be a little bit more or less. As these conditions can vary from one printed circuit board to another, it is important to provide the capability to tune the sampling point through the user interface of the DDR-SDRAM controller.
Different methods exist to generate a programmable delay, and the module 40 of
For the descriptions of next modules, it is assumed that module 42 provides an output clock period on signal line 54 being twice the input clock period provided to the DDR-SDRAM device (i.e. if the DDR-SDRAM is clocked at 100 MHz, the frequency at signal line 54 is 50 MHz).
Block 44 contains the circuitry that locks on the reference delay provided by module 42. It allows determination of the number of basic delay elements of a delay line 56 to obtain a delay which is a fraction of the system clock period.
The number of delay elements determined by block 44 will be a known fraction of the number of elements required to delay the DQS signal from DDR-SDRAM devices. The delay line used in module 44 is designed with the same basic delay elements as the one that will be used in the slave delay line to delay the DQS signal.
In the following example, the module 44 is designed in such a way that it locks on half of a system clock period. This leads to a simplified circuit architecture to reach the lock state from initial or reset state or from lock to lock state (due to a derating factor variation).
As in all locked systems, the architecture comprises a phase detector circuit to provide the information necessary to add or remove basic delay elements in the programmable delay line 56 to match the reference delay provided by stable clock signal 54.
In the example shown in
When system reset is asserted on line 68, the D-flip-flops 58 and 60 are cleared, the programmable master delay line provides a feedback clock at the output of master programmable delay line 56 delayed by a single basic delay element because the up/down counter 70 is set accordingly from the outputs of NOR gate 64 and an AND gate 66.
After de-assertion of system reset on line 68, the D-flip-flops 58 and 60 start sampling logical 0 (the low portion of the waveform at the output of master programmable delay line 56). When the outputs of both D-flip-flops are cleared, the 2-input NOR gate 64 provides a logical 1 at the UP input of up/down counter 70 to indicate that the phase detector 44 is unlocked and requires more basic delay elements to be included in the master programmable delay line to reach the lock state. The 2-input AND gate 66 drives the DOWN input of the up/down counter 70 with a logical 0 to indicate that there is no need to remove delay elements in the programmable delay line 56. An example of this state is shown in
The up/down counter 70 modifies its output to instruct master programmable delay line 56 to add more delay. The programmable delay line increases its internal delay accordingly by selecting 1 more basic delay. The phase detector module 44 is still in its unlocked state.
If the delay becomes greater than the reference delay provided by the clock period of system clock at its output 54, both D-flip-flops 58 and 60 sample a logical 1. The 2-inputs NOR gate 64 returns logical 0 to the UP input of up/down counter 70 and the 2-input AND gate 66 provides a logical 1 to the DOWN input of up/down counter 70. Under these conditions, up/down counter 70 modifies the value provided on its output to instruct the master programmable delay line 56 to remove one basic delay element. The master programmable delay line decreases its internal delay accordingly. The phase detector 44 is still in its unlocked phase. An example of this state is shown in
When the programmable delay line 56 delays the system clock on signal line 54 by half the system clock period (locked state), D-flip-flop 58 samples a logical 1 whereas D-flip-flop 60 samples a logical 0. This difference of sampled values is possible due to the presence of delay line 62 in the path of the data input of D-flip-flop 58.
Delay line 62 allows locating the falling edge of the delayed feedback clock at the output of delay line 62 to a time after the rising edge of system clock on line 54 and locating the falling edge of the feedback clock prior to the rising edge of the system clock on line 54. In this case both NOR gate 64 and AND gate 66 provide logical 0 to the UP and DOWN inputs of up/down counter 70. The output of up/down counter 70 does not change, indicating that the phase error provided by the phase detector is zero and the phase detector 44 is locked. An example of this state is shown in
The delay line 62 can be designed with basic delay elements such classical inverters or buffers. There is no need for more complex delay elements as will be disclosed with reference to the master programmable delay line 56.
The propagation delay between the input of delay line 62 and its output must be greater than a value defined as the sum of the setup and hold time of the D-flip-flops 58 and 60. This will limit the metastable behavior on both D-flip-flops for each sampling point. If one of the delayed signals to the data inputs of D-flip-flops 58 and 60 arrives in the metastable period of one D-flip-flop, then the other signal cannot be in the metastable period of the second one.
Persons of ordinary skill in the art will appreciate that there is still a probability of one of the D-flip-flops sampling data in a setup or hold period. There is no way to avoid this situation but an improvement exists in the definition of the intrinsic delay value (in delay line 62) of phase detector 44.
If the propagation delay of phase detector 44 is greater than the higher value of the metastable period among D-flip-flops 58 and 60 plus the minimum delay in the programmable delay line 62, the phase detector will stay in a locked state without metastable behavior of D-flip-flops 58 and 60. Metastable states will occur in transient phases.
In its locked state, the phase detector 44 defines a number of basic delay elements needed to delay the system clock by half the system clock period. A main objective of the present embodiments of the invention is to get ¼ of the DQS period or ¼ of the DDR-SDRAM device clock period. Therefore a conversion must be performed and applied to programmable delay line connected to DQS control input signals.
Referring now to
Multiplexers 96, 100, 104, 108, 112, and 116 are controlled by select inputs S0, Si, S2, S3, . . . S(n-1) and S(n) respectively. If the select input of a unit delay element is set to logic zero, its multiplexer selects the inverted output of the multiplexer in the next unit delay element. If the select input of a unit delay element is set to logic one, its multiplexer selects the output of its own inverter. Thus, only one select input in the programmable delay line circuit 80 need be set to logic one, in which unit delay element the signal is turned around and is directed back down through the chain of multiplexers and ultimately to the output buffer 122. Any select inputs further downstream in the chain that are set to logic one do not affect the operation of the programmable delay line circuit 80.
As an example, if the select input S0 and S1, are set to logic zero and the select input Sz is set to logic one, the signal will pass through the input buffer 120, inverters 94, 98 and 102, multiplexers 104, 100 and 96, and through output buffer 122. The states of select inputs S3, . . . S(n-1) and S(n) will not affect the operation of the circuit.
Referring again to
Block 46 includes a fractional coefficient multiplier 134, whose input may be updated as necessary by the output of up/down counter 70. Its output is presented to D-flip-flop 136 via multiplexer 138. The data latched in D-flip-flop 136 is used to drive slave programmable delay lines 130 and 132 of block 48. The select input of multiplexer 138 is driven by the update delay line signal at line 140. As long as the update signal is not asserted, the output of D-flip-flop 136 is fed back to its data input through multiplexer 138. When the update signal 140 is asserted, the input of D-flip-flop 136 is driven by the output of up/down counter 70.
Due to the structure of the programmable delay line 56 as has been shown and described with reference to
Care must be taken when changing the delay value. The value returned by fractional coefficient multiplier 134 cannot be applied to the slave programmable delay line at any time. It is preferable to apply a new value when there is no access being made to data from the DDR-SDRAM device. If this value is altered when the memory device is being accessed, the value must be held to avoid modifying the DQS delay when the DQS signal is in use to avoid the risk of a parasitic pulse when switching from one delay to another one in the programmable delay line. At any rate, if accesses are performed without interruption, there is a need to update the delay to take into account the possible derating factor variations. The DDR-SDRAM devices need to periodically interrupt the accesses to be able to refresh their contents. The times of these refresh cycles are known by the memory controller. This information can be used to safely enable the update of the slave delay line during refresh operations when the DQS signals are not used by the DDR-SDRAM memory controller and glitches on that line will not matter.
If such a scheme is used, when the memory controller (not shown) instructs the DDR-SDRAM device to perform refresh, it asserts a signal on line 140, thereby refreshing the contents of D-flip-flop 136. As soon as refresh period is finished, the line 140 is de-asserted and the multiplexer 138 re-circulates data to D-flip-flop 136.
Referring now to
While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art that many more modifications than mentioned above are possible without departing from the inventive concepts herein. Embodiments of the invention, therefore, are not to be restricted except in the scope of the appended claims.
The Abstract is provided to comply with 37 C.F.R. §1.72(b) and is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.