US 20090315085 A1
In order to realize a higher reliability TFT and a high reliability semiconductor device, an NTFT of the present invention has a channel forming region, n-type first, second, and third impurity regions in a semiconductor layer. The second impurity region is a low concentration impurity region that overlaps a tapered potion of a gate electrode with a gate insulating film interposed therebetween, and the impurity concentration of the second impurity region increases gradually from the channel forming region to the first impurity region. And, the third impurity region is a low concentration impurity region that does not overlap the gate electrode.
Moreover, a plurality of NTFTs on the same substrate should have different second impurity region lengths, respectively, according to difference of the operating voltages. That is, when the operating voltage of the second TFT is higher than the operating voltage of the first TFT, the length of the second impurity region is longer on the second TFT than on the first TFT.
1. A semiconductor device comprising:
a semiconductor layer formed over a substrate having an insulating surface, the semiconductor layer comprising at least one channel region, source and drain regions, and at least one impurity region located between one of source and drain regions and the channel region; and
a gate electrode formed over the semiconductor layer with a gate insulating film interposed therebetween;
wherein only a portion of the impurity region is overlapped with a portion of the gate electrode, and
wherein the overlapped portion of the gate electrode has a thinner thickness than that of a portion of the gate electrode above the channel region.
1. Field of the Invention
The present invention relates to a thin film transistor (hereinafter referred to as TFT) and to a semiconductor device having a circuit structured with a thin film transistor. The present invention relates to such semiconductor devices as electro-optical devices, typically active matrix liquid crystal display devices (hereinafter referred to as AM-LCDs), and semiconductor circuits including processors, etc. The present invention also relates to electronic equipment loaded with the electro-optical devices or semiconductor circuits. Note that throughout this specification semiconductor device indicates general devices that acquire their function through the use of semiconductor characteristics, and that electro-optical devices, semiconductor circuits, and electronic equipment are semiconductor devices.
2. Description of the Related Art
Active matrix type liquid crystal display devices composed of TFT circuits that use polysilicon films have been in the spotlight in recent years. They are the backbone for realizing high definition image displays, in which a multiple number of pixels are arranged in a matrix state, and the electric fields that occur in liquid crystals are controlled in that matrix state.
With this type of active matrix type liquid crystal display device, as the resolution becomes high definition in XGA and SXGA, the number of pixels alone exceeds one million. A driver circuit that drives all of the pixels is therefore extremely complex, and furthermore is formed from a large number of TFTs.
The required specifications for actual liquid crystal display device (also called liquid crystal panels) are strict, and in order for all of the pixels to operate normally, high reliability must be secured for both the pixels and the driver circuit. If an abnormality occurs in the driver circuit, especially, this invites a fault called a line defect in which one column (or one row) of pixels turns off completely
However, from a reliability point of view, TFTs that use polysilicon films still fall behind MOSFETs (transistors formed on a single crystal semiconductor substrate), etc., used in LSIs. As long as this shortcoming is not overcome, the point of view that it is difficult to use TFTs when forming an LSI circuit will get stronger.
The applicant of the present invention considers that when comparing a TFT with a MOSFET, the problems associated with the TFT structure affect its reliability (especially hot carrier resistance).
The present invention is technology for overcoming those problems, and therefore an object of the present invention is to realize a TFT that shows the same or higher reliability than a MOSFET. In addition, another object of the present invention is to realize a high reliability semiconductor device that includes semiconductor circuits formed by circuits using such TFT.
In order to solve the above problems, an n-channel TFT (hereinafter referred to as NTFT) of the present invention has: an n-type first impurity region that functions as a source region or drain region in a semiconductor layer where an inversion layer is formed; and two types of impurity regions (a second impurity region and a third impurity region), in between a channel forming region and the first impurity region, that show the same conductivity type as the first impurity region. The concentration of the impurity that determines the conductivity in the second and third impurity regions is less than that of the first impurity region. The second and third impurity regions function as high resistance regions, also called LDD regions.
The second impurity region is a low concentration impurity region that overlaps a gate electrode with a gate insulating film interposed therebetween, and has the effect of enhancing hot carrier resistance. On the other hand, the third impurity region is a low impurity region that does not overlap the gate electrode, and has the effect to prevent the off current from increasing.
The most important characteristic of the present invention, then, is that a first NTFT and a second NTFT exist on the same substrate, but have different second impurity region lengths, respectively. In other words, according to difference of the operating voltages, the appropriate TFTs having suitable second impurity region length should be arranged. Specifically, when the operating voltage of the second TFT is higher than the operating voltage of the first TFT, the length of the second impurity region is longer on the second TFT than on the first TFT.
Conventionally, it is known that hot carrier resistance increases with a so-called GOLD structure (gate-drain overlapped LDD). This technique has begun to be applied to TFTs, but the problem that with a conventional GOLD structure the off current increases (the current flow when the TFT is in an off state) has been unreasonably ignored.
The applicant of the present invention considers that the above problem must be resolved, and investigates to verify that the off current is reduced dramatically by forming an impurity region (the third impurity region) that does not overlap the gate electrode. Therefore it can be said that the present invention is characterized in the active formation of the third impurity region.
Note that the gate electrode is an electrode that intersects with the semiconductor layer with a gate insulating film interposed therebetween, and is an electrode for applying an electric field to the semiconductor layer and forming an inversion layer. The portion of a gate wiring that intersects with the semiconductor layer with a gate insulating film interposed therebetween is the gate electrode.
In addition, the film thickness of the gate electrode of the present invention decreases either linearly or stepwise from a central flat section, at the periphery of the gate electrode, outward. Namely, it is characterized by being patterned into a tapered shape.
The second impurity region is doped through (passing an impurity through) the tapered region of the gate electrode with the impurity to impart conductivity. Therefore the concentration gradient reflects the inclination (change in film thickness of the tapered portion) of the side face of the gate electrode. In other words, the concentration of the impurity doped into the second impurity region increases gradually from the channel forming region to the first impurity region.
This is caused by the change in the depth that the impurity reaches due to the difference in film thickness in the tapered region. In other words, when looking at the impurity concentration distribution in the depth direction, the depth at which the doped impurity is at peak concentration changes along with the inclination of the tapered portion of the gate electrode.
An impurity concentration gradient can be formed in the inside of the second impurity region with this type of structure. The present invention is characterized by actively forming this type of such a concentration gradient, forming a TFT structure that enhances the electric field relaxation effect.
Further, the structure of other gate electrodes in the present invention is a laminate of a first gate electrode, in contact with the gate insulating film, and a second gate electrode formed on the first gate electrode. Of course, a single layer first gate electrode may also be used.
In this structure, the side face (tapered portion) of the first gate electrode is has a tapered shape that forms with the gate insulating film an angle (shown by θ, and hereinafter referred to as taper angle) equal to or greater than 3° and equal to or less than 40° (desirable if equal to or greater than 5° and equal to or less than 35°, even better if equal to or greater than 8° and equal to or less than 20°). On the other hand, the width of the second gate electrode in the longitudinal direction of the channel is narrower than the first gate electrode.
Also for a thin film transistor having the above type of laminated gate electrode, the concentration distribution of the impurity included in the second impurity region reflects the change in film thickness in the tapered portion of the first gate electrode. The impurity concentration thereof increases gradually from the channel forming region in the direction of the first impurity region.
An NTFT with the above structure has high hot carrier resistance, and its voltage resistance characteristics (resistance to dielectric breakdown due to electric field concentration) are also good, so it is possible to prevent age-based deterioration in the on current (the current flow when the TFT is in an on state). This effect is due to the formation of the second impurity region.
In addition, it is possible to greatly reduce the off current by formation of the third impurity region. As outlined above, the formation of the third impurity region is a characteristic of the NTFT of the present invention.
The NTFT of the present invention has very high reliability. Thus it is possible to form a high reliability circuit when the NTFT is complementally combined with a PTFT to form a CMOS circuit, or used in a pixel region (pixel matrix circuit) of a liquid crystal display device or an electroluminescence display device. In other words, compared with a conventional NTFT, the drop in capability of a circuit due to deterioration of the NTFT can be prevented.
Note that it is not especially necessary to use the above TFT structure for a p-channel type thin film transistor (hereinafter referred to as PTFT) in the present invention. Namely, a known structure may be used because a PTFT does not have as much of a deterioration problem as an NTFT. It is of course possible to use the same structure as the NTFT.
In the accompanying drawings:
In Embodiment Mode 1,
First, a base film 101 is formed over the entire surface of a substrate 100, and a semiconductor layer 102 with an island shape is formed on the base film 101. An insulating film 103 that becomes a gate insulating film is then formed over the entire surface area of the substrate 100, covering the semiconductor layer 102 (see
The following can be used as the substrate 100: a glass substrate; a quartz substrate; a crystalline glass substrate; a metallic substrate; a stainless steel substrate; and a resin substrate such as polyethylene terephthalate (PET).
The base film 101 is a film that prevents diffusion of mobile ions such as sodium ions, from the substrate 100 to the semiconductor layer 102, and increases adhesion of the semiconductor layer formed on the substrate 100. Either single layer or multiple layer inorganic insulating films such as a silicon oxide film, a silicon nitride film or an oxidized silicon nitride film can be used for the base film 101.
The base film need not only be a film deposited by CVD or sputtering. If a heat resistant substrate such as quartz is used, an amorphous silicon film, for example, may be deposited and then thermally oxidized, forming an oxidized silicon film.
The semiconductor layer 102 material may be chosen so that it conforms with the required characteristics of the TFT. An amorphous silicon film, an amorphous germanium film, or an amorphous silicon germanium film, or crystalline silicon, crystalline germanium or crystalline silicon germanium which are formed by crystallizing these amorphous semiconductor films with laser irradiation or annealing can be used. A known technique may be used as the means of crystallization. The thickness of the semiconductor layer 102 is between 10 and 150 nm (typically from 20 to 50 nm).
The insulating film 103 is a film that constitutes the gate insulating film. A single layer or multiple layer inorganic insulating film of silicon oxide, silicon nitride, or oxidized silicon nitride deposited by plasma CVD or sputtering can be used. In the case of a laminate film, a two layer film of oxidized silicon nitride and silicon oxide, or a laminate film of silicon nitride film sandwiched by silicon oxide films can be used, for example.
A first conductive film 104 and a second conductive film 105, which constitute a gate electrode (gate wiring) are formed on the insulating film 103 (see
The first conductive film 104 constitutes a first gate electrode (first gate wiring) having a tapered portion. Therefore a thin film of a material which can easily be taper etched is desirable. For example, a chromium (Cr) film, a tantalum (Ta) film, a thin film with tantalum as its main constituent (equal to or greater than 50% composition ratio), or an n-type silicon (Si) film containing phosphorous is typically used.
Further, the film thickness of the first conductive film 104 is an important parameter for the present invention because it determines the length (in the channel longitudinal direction) of the second impurity region (the impurity region overlapping the gate electrode). The length is selected in the range of 50 to 500 nm (desirable between 150 and 300 nm, even better between 200 and 250 nm) for the present invention.
In addition, the second conductive film 105 is a thin film that constitutes a second gate electrode (second gate wiring), and can be formed by a thin film of one of the following: an aluminum (Al) film; a copper (Cu) film; a thin film with either aluminum or copper as its main constituent (equal to or greater than 50% composition ratio); a chromium (Cr) film; a tantalum (Ta) film; a tantalum nitride (TaN) film; titanium (Ti) film; tungsten (W) film; molybdenum (Mo) film; an n-type silicon film containing phosphorous; a tungsten molybdenum (W—Mo) film; a tantalum molybdenum (Ta—Mo) film; etc. Further, not only can the above thin film be used as a single layer film, but a laminate with any combination of those may also be used.
However, it is necessary to choose a material for the first conductive film and the second conductive film in which a selective etching ratio can be obtained in mutual patterning.
For example, the following combinations can be selected as the first conductive film 104/the second conductive film 105 materials: n-type Si/Ta; n-type Si/W—Mo alloy; Ta/Al; Ti/Al; etc. As further guidelines for material selection, it is desirable that the second conductive film 105 have as low as possible resistivity, and should at least be from a material with a sheet resistance lower than that of the first conductive film 104. This is because the connection of the gate wiring and an upper layer wiring goes through the second gate wiring.
Next, a resist mask 106 is formed on the second conductive film 105. The second conductive film 105 is etched using the resist mask 106, forming a second gate electrode 107. Isotropic wet etching may be used for etching (see
Anisotropic etching of the first conductive film 104 is performed next using the same resist mask 106, forming a first gate electrode (first gate wiring) 108. Note that a new resist mask can be formed for use in this etching.
Through this etching, as shown in
Furthermore, if the taper angle exceeds 40°, then the length of the second impurity region (the region in which the impurity concentration changes gradually), the most important characteristic of the NTFT of the present invention, gets extremely short, so it is desirable that the taper angle is kept 40° or smaller.
The taper angle is defined as tan θ=HG/WG, where WG is the width of the tapered portion and HG is the thickness (the film thickness of the first gate electrode 108).
The resist mask 106 is removed next, and the second gate electrode 107 and the first gate electrode 108 are used as masks for doping an n-type or p-type impurity into the semiconductor layer 102. Ion implantation (mass separation type), and ion doping (non-mass separation type) can be used as the doping method.
An n-type impurity is an impurity that becomes a donor, and typically periodic table group XV (15) elements phosphorous (P) and arsenic (As) are used for silicon and germanium. A p-type impurity is an impurity that becomes an acceptor, and typically periodic table group VIII (13) elements boron (B) and gallium (Ga) are used for silicon and germanium.
Phosphorous is doped by ion doping here, forming n−-type impurity regions 109 and 110. In this case phosphorous is doped through the gate insulating film 103 and the tapered portion of the first gate electrode 108, so it is necessary to set the acceleration voltage considerably high at between 80 and 160 keV for the ion doping process. Note that it is necessary to be careful because, as will be discussed later, the concentration and distribution of the phosphorous, which goes into the area underneath the tapered portion, changes in accordance with acceleration voltage.
This doping process determines the concentration distribution of phosphorous in an n−-type second impurity region and an n−-type third impurity region, discussed later (see
Specifically, phosphorous is doped into the n−-type impurity regions 109 and 110 through (passing through) the tapered portion of the first gate electrode 108, so the concentration gradient reflects change in the film thickness of the tapered portion of the first gate electrode 108. In other words, the concentration of phosphorous doped into the n−-type impurity regions 109 and 110 gradually increases with distance from the channel forming region underneath the tapered portion.
This is because the doping concentration of phosphorous in the depth direction changes due to the difference in film thickness in the tapered portion. Namely, when looking at the doping depth of an arbitrary concentration in the concentration distribution of phosphorous in the depth direction (for example, at an average concentration in the depth direction), the depth changes along with the inclination in the gate electrode tapered portion, in the cross sectional direction of the semiconductor layer.
The phosphorous concentration distribution is shown by wavy lines in
Note that it is not necessary for the phosphorous doping process to be performed perpendicularly to the substrate at this time, and an ion containing phosphorous may be doped obliquely. This type of doping process is effective for cases in which phosphorous is doped deep into the inside of the gate electrode.
Next a resist mask 111 is formed, covering the first gate electrode 107 and the second gate electrode 108. The resist mask 111 determines the length of the third impurity region. The n-type impurity phosphorous is again doped into the semiconductor layer 102, through the resist mask 111, by ion doping. In this case there is no need to dope through the tapered portion of the first gate electrode 108, so the acceleration voltage may be set to around 80 to 100 keV (see
By this doping process, phosphorous is selectively doped into the n−-type impurity regions 109 and 110 not covered by the resist mask 111, forming n+-type first impurity regions 112 and 113. In addition, phosphorous is not doped into a region 114 underneath the second gate electrode 107 in the doping process of
Furthermore, in the n−-type impurity regions 109 and 110, into which phosphorous is not doped by the above process, regions denoted by reference numerals 115 and 116, which overlap the first gate electrode 108, become n−-type second impurity regions. Regions that do not overlap the first gate electrode 108 become n−-type third impurity regions 117 and 118.
Note that the gate wiring may be used as a mask prior to the
At this point, as shown in
As shown in
Furthermore, at this point the phosphorous concentration distribution inside the second impurity region 115A, as shown in the explanation of
This is because a concentration gradient in the cross sectional direction inside the second impurity region 115A is formed due to phosphorous being doped through the tapered portion of the first gate electrode 108. In this case a channel length LA corresponds to the width of the second gate electrode 107 in the longitudinal direction of the channel.
A channel length LB corresponds to the width of the second gate electrode 107 in the longitudinal direction of the channel for this case. In addition, even if the acceleration voltage is the same as in
By making the acceleration voltage even larger, as shown in
In other words, a region begins to form in which phosphorous is doped from the outside (the side close to the third impurity region) of the channel junction. The channel length does not coincide with the width of the second gate electrode 107 in the longitudinal direction of the channel, and instead becomes longer than that width.
Further, even if the acceleration voltage is the same as in
At this point the length of the first impurity regions 112 and 113 is between 2 and 20 μm (typically between 3 and 10 μm). Further, the phosphorous concentration in the semiconductor layer is between 1×1019 and 1×1021 atoms/cm3 (typically between 1×1020 and 5×1020 atoms/cm3). The first impurity regions 112 and 113 are low resistance regions and each of them electrically connects the source wiring or drain wiring to the TFT, and is a source region or a drain region.
In addition, the second impurity regions 115 and 116 have a length of between 0.1 and 3.5 μm (typically from 0.1 to 0.5 μm, desirable between 0.1 and 0.3 μm), and have a phosphorous concentration of 1×1015 to 1×1017 atoms/cm3 (typically between 5×1015 and 5×1011 atoms/cm3, desirable from 1×1016 to 2×1016 atoms/cm3).
Further, the third impurity regions 117 and 118 have a length of between 0.5 and 3.5 μm (typically from 1.5 to 2.5 μm), and have a phosphorous concentration from 1×1016 to 1×1019 atoms/cm3 (typically between 1×1017 and 5×1018 atoms/cm3, desirable from 5×1017 to 1×1018 atoms/cm3).
Additionally, the channel forming region 114 is an intrinsic semiconductor layer, or a region in which boron is doped to a concentration from 1×1016 to 5×1018 atoms/cm3. Boron is used to control the threshold voltage and prevent punch-through, but another element may be substituted provided that similar effects are obtained.
Note that an example is shown in
The resist mask 111 is removed after forming the first impurity regions 112 and 113. Then heat treatment is performed, activating the phosphorous doped into the semiconductor layer. Photo annealing by excimer laser or infrared lamp irradiation can be performed for the activation process, not only the heat treatment.
Next an interlayer insulating film 119 is formed from a silicon oxide film, etc. Contact holes are next formed in the gate insulating film 103 and the interlayer insulating film 119 to reach the first impurity regions 112 and 113, and the second gate wiring 107. Then a drain wiring 120, a source wiring 121, and extraction lead wiring for the gate wiring, not shown in the figures, are formed. Thus an NTFT with the structure as shown in
Embodiment Mode 2 is an example in which the gate electrode (gate wiring) structure is different than in Embodiment Mode 1. Specifically, the gate electrode has a laminated structure of two gate electrodes with different widths in Embodiment Mode 1, but in Embodiment Mode 2 the upper second gate electrode is omitted, and the gate electrode is formed from only a first gate electrode, which has a tapered portion.
Embodiment Mode 2 is shown in
A material that can easily be taper etched is desirable for the conductive film that becomes the gate electrode 130. Regarding the thin films that can be used, the material used as the first conductive film 104 in Embodiment Mode 1 may be used.
In addition, the taper angle of the gate electrode 130 is between 3° and 40°. It is desirable that the taper angle be between 5° and 35°, and even better if it is from 7° to 20°. This taper shape can be achieved by a known etching technique, but it is possible to easily obtain a desired taper angle by controlling the bias power density of an etching apparatus that uses high density plasma.
Furthermore, Embodiment Mode 1 may be referred to for detailed conditions of the manufacturing process for forming an NTFT with the structure of Embodiment Mode 2.
In addition, in Embodiment Mode 2 the second impurity regions may be classified into 4 types as shown in
However, in Embodiment Mode 1 even if the thickness of the first gate electrode 108 is made thinner, by making the second gate electrode 107 thicker it is possible to get low resistance because the gate electrode has a laminate structure. However, the gate electrode 130 is a single layer electrode with a tapered portion in Embodiment Mode 2, so the film thickness becomes thicker than that of the first gate electrode 108, explained in Embodiment Mode 1.
Thus it is possible to lengthen the width WG on the tapered portion by regulating the taper angle, and this is advantageous when one want to lengthen the second impurity regions. On the other hand, phosphorous becomes more difficult to dope by the same amount the film thickness gets thicker due to a small taper angle, and a structure like that of
The applicant of the present invention investigated by simulation the concentration of phosphorous, and its distribution, doped under the tapered portion of the first gate electrode in the phosphorous doping process shown in
It can be clearly determined by looking at
The acceleration voltage was 110 keV here, but if the acceleration voltages is made higher it can be expected that the phosphorous concentration will get even higher on the inside (the inside of the first gate electrode). Further, the concentration distribution may change by using an ion implantation method. However, the main objects of the present invention are to form this type of phosphorous concentration gradient on the inside of the LDD region (including the portions overlapping the gate electrode), and to enhance the electric field relaxation effect, so the operator may appropriately determine an optimal concentration distribution.
Embodiment 1 shows an example in which the NTFT explained in the embodiment modes is used to fabricate an active matrix type liquid crystal display device (AM-LCD).
In addition, a signal processing circuit 204 is formed on the substrate in order to process the video signals transmitted to the source driver circuit 203. A D/A converter circuit, a signal division circuit, a v correction circuit, etc., can be given as examples of the signal processing circuit. Then, an external terminal is formed in order to input the video signals, and an FPC 205 is connected to the external terminal.
A transparent conductive film such as an ITO film is formed over a surface of a glass opposing substrate 206. The transparent conductive film is an opposing electrode to the pixel electrode in the pixel region 201, and the liquid crystal material is driven by an electric field formed between the pixel electrode and the opposing electrode. Furthermore, if necessary, wiring films, color filters, black masks, etc., may be formed on the opposing substrate 206.
An AM-LCD with the above arrangement has a different minimally required operating voltage (supply voltage) depending upon the circuits. For example, by considering the voltage applied to the liquid crystal and the voltage to drive the pixel TFT in the pixel region, the operating voltage would be between 14 and 20 V. Thus, a TFT that can withstand a high applied voltage (hereinafter referred to as high voltage resistant type TFT) must be used.
Further, an operating voltage having about 5 to 10 V is sufficient for the shift register circuits, etc., used in source driver circuits and gate driver circuits. As the operating voltage gets lower, there are advantages in compatibility with external signals and suppressed power consumption. However, while the above high voltage resistant type TFT has good voltage resistant characteristics, its operating speed is sacrificed, so it is not appropriate in circuits that demand high speed operation such as a shift register circuit.
Thus, the circuits formed on the substrate are classified into circuits that require a TFT that places great importance on voltage resistant characteristics, and into circuits that require a TFT that focuses on operating speed, depending upon their purpose. Therefore, in order to effectively apply the NTFT of the present invention, it is important to apply a structure corresponding to the circuit in use.
The specific structure of Embodiment 1 is shown in
Note that the AM-LCD includes gate driver circuits 12 to sandwich the pixel region 11 therebetween, as shown in
In addition, reference numeral 13 a denotes a shift register circuit, 13 b denotes a level shifter circuiter circuit, 13 c denotes a buffer circuit, and 13 d denotes a sampling circuit. These circuits together form a source driver circuit 13. A pre-charge circuit 14 is formed on the side opposite the source driver circuit, sandwiching the pixel region therebetween.
In an AM-LCD with this type of structure, the shift resister circuits 12 a and 13 a are circuits that demand high speed operation, the operating voltage is as low as between 3.3 and 10 V (typically from 3.3 to 5 V), and there is no special requirement for high voltage resistant characteristics. Therefore, when using the NTFT of the present invention, it is desirable that a structure that does not lower the operating speed be employed. In this connection, the second impurity regions and the third impurity regions, which are resistance components, are narrowed to the minimum.
In addition, the cross sectional structure of the CMOS circuit of
Further, it is appropriate that a third impurity region 22 a be as small as possible, and depending upon the circumstances, it may not be formed at all. This is because it is not necessary to be very concerned with the off current in a shift register circuit or a signal processing circuit, etc. If so, it will be formed in the range of 0.1 to 1.5 μm (typically between 0.3 to 1.0 μm).
Summing up the circuit of
Next, the CMOS circuit shown in
In this case as well, it is desirable that the third impurity region 22 b be as small as possible, and it is acceptable not to form it. The reason is the same as for the shift register circuit, etc. It is not necessary to be concerned much about the off current. Note that when formed, the third impurity region 25 has a length in the range of 0.1 to 5.5 μm (preferably from 1.0 to 3.0 μm). However, depending on the circumstances, a high voltage of 20 V may be applied to the buffer circuit on the gate driver side, and in that case, it is necessary to form a longer third impurity region to reduce the off current.
Summing up the circuit of
Especially for a sampling circuit, the channel length may be 4.0±2.0 μm, the length of the second impurity region may be 1.5±1.0 μm, and the third impurity region may be made 2.0±1.5 μm.
In addition, the pixel electrode 30, which is connected to the drain electrode 29, forms a retention capacitor with an insulating film 32 interposed between the pixel electrode 30 and a transparent conductive film 31, as shown in
Then, by taking into account that a voltage is applied to the liquid crystal, a 14 to 16 V operating voltage is necessary for the pixel TFT (switching element in the pixel region). In addition, the electric is charge that accumulates in the liquid crystal and the retention capacitor must be retained for the period of one frame, so the off current must be as small as possible.
For this reason, a double gate structure is used for the NTFT of the present invention in Embodiment 1, and the length (WG3) of a second impurity region 34 is between 0.5 and 3.0 μm (preferably between 1.5 and 2.5 μm). Further, WG2 (see
The desired length can be obtained by controlling the taper angle of the first gate electrode 25 at this time as well. For example, the taper angle may be between 3° and 30°. However, the appropriate value changes in accordance with the film thickness of the first gate electrode 25.
Additionally, the pixel region shown in
As explained with reference to
Summing up the circuit of
As stated above, various circuits can be formed on a single substrate in the example of an AM-LCD, and the necessary operating voltage (supply voltage) differs depending on the circuit. These results are shown in Table 1.
Thus, there arc cases in which withstand characteristics to be required may differ so as to correspond to the purpose of the circuit, and it is necessary to adapt the TFT in such a case as in Embodiment 1. It can be stated that the adaptability of the NTFT of the present invention demonstrates its true value.
A modified example of the NTFT of Embodiment 1, which constitutes the CMOS circuit and the pixel region is explained in Embodiment 2.
A CMOS circuit ordinarily has a fixed source region and drain region, and a low concentration impurity region (LDD region) is only necessary on the drain region side. On the contrary, an LDD region (or an offset region) formed on the source region side simply works as a resistance component, and is a cause of lowered operating speed.
Thus, a structure with the third impurity region formed only on the drain region side is desirable as in Embodiment 2. The third impurity region is formed by using a resist mask, so it is easy to form it only on the drain region side.
An example case in which the structure of Embodiment 2 is used for a pixel TFT (NTFT) that forms a pixel region is shown in
In the case of a pixel TFT, the operating mode is different than that of a CMOS circuit, and the source region and the drain region alternately operate. It is necessary for third impurity regions 45 and 46 to be formed in the area where the pixel TFT and the output terminal (source wiring or drain wiring) connect with each other.
However, for the double gate structure shown in
If a high definition display screen is required for a liquid crystal display device, then the write time to the pixels (the time for the necessary voltage to be applied to the liquid crystals) becomes extremely short. Thus, a certain amount of operating speed is also required for the pixel TFT, and a structure that reduces resistance components as much as possible is necessary. For this reason, it can be stated that the structure of Embodiment 2 is a very preferable.
Namely, it is a structure in which the first impurity region (source region) 47, which connects to the source wiring 36, is directly in contact with the channel forming region. Thus, the formation of unnecessary resistance components on the source side can be avoided, and the CMOS circuit capable of a high-speed operation can be realized.
Note that the structure of Embodiment 2 is effective for all of the circuits shown in Embodiment 1. In other words, no third impurity region is formed on the source region side of the NTFT, but a third impurity region is only formed on the drain region side thereof, so that it is possible to increase the operating speed while maintaining high reliability. Of course, Embodiment 2 can be combined with all of the cases shown in
An explanation of the manufacturing process of a CMOS circuit using the present invention is given in Embodiment 3.
First, processing is performed in accordance with Embodiment 1 above, through
Note that in order to make the lengths of the second impurity regions different so as to correspond to the circuits on the same substrate as shown in
Next, a phosphorous doping process is performed using the second gate electrodes 53 and 54 as masks, forming n−-type impurity regions 57 to 59. Embodiment 1 may be referred to for the doping conditions. Phosphorous is doped by penetrating the first gate electrodes at the tapered portions of the first gate electrodes 51 and 52, where the impurity regions are formed which exhibits concentration gradients as explained by using
Next, a resist mask 60 is formed, and after that, a phosphorous doping process is again performed, forming n+-type impurity regions 61 to 63. A third impurity region explained with reference to
The NTFT of the CMOS circuit is completed when the processes of
Next, a resist mask 65 is formed so as to cover the NTFT, and a boron doping process is performed under the conditions of Embodiment 1. The above n−-type impurity regions and n+-type impurity regions are both inverted by this process, forming p++-type impurity regions 66 and 67 (see
Then, after removing the resist mask 65, the first gate electrodes and the second gate electrodes are covered with a silicon nitride film 68, and doped phosphorous and doped boron are activated. This process may be performed in free combination of furnace annealing, laser annealing, and lamp annealing. Further, the silicon nitride film 68 is intended to protect the first gate electrodes and the second gate electrodes from heat and oxidation reactions.
Next, an interlayer insulating film 69 is formed on the silicon nitride film 68, and after forming contact holes, source wirings 70 and 71, and a drain wiring 72 are formed. Thus a CMOS circuit with the structure shown in
Note that one example of a CMOS circuit that uses the NTFT of the present invention is shown in Embodiment 3, but it is not necessary to place limitations on the structure of the CMOS circuit of Embodiment 3. Further, in cases of realizing the arrangement shown in
Furthermore, it is possible to freely combine the structure of Embodiment 3 freely with the structures of Embodiments 1 and 2.
In Embodiment 4, etching conditions, in order to taper the side face of the first gate electrode on the NTFT of the present invention, are explained. In Embodiment 4, the conductive film that forms the first gate electrode is formed by sputtering, using a tungsten target with a purity of 6N (99.9999%) or greater. An inert gas may be used as the sputtering gas, but a tungsten nitride film can be formed by adding nitrogen (N2).
A laminate structure is used in Embodiment 4, with a 370 nm tungsten film on a 30 nm tungsten nitride film. However, it is alright not to form the tungsten nitride film, and a silicon film may be formed under the tungsten nitride film. Further, a laminate film with a tungsten nitride film on a tungsten film may be formed.
The laminate film thus obtained has an oxygen content of 30 ppm or less. Due to this, the electrical resistivity can be made 20 μΩcm or less, typically between 6 and 15 μΩcm, and the film stress can be between −5×109 and 5×109 dyn/cm2.
Next, a resist pattern is formed on the above laminate film, and etching is performed on the laminate film, forming a first gate electrode. At this point, in Embodiment 4, an ICP (Inductively Coupled Plasma) etching apparatus using a high density plasma is employed for the patterning the laminate film.
Embodiment 4 is characterized by the regulation of the bias power density on the ICP etching apparatus in order to obtain a desired taper angle.
The taper angle is 20° in Embodiment 4, so the bias power density is set to 0.4 W/cm2. Of course, the taper angle can be made to be 20° if setting the bias power not lower than 0.4 W/cm2. Note that the ICP power is 500 W, the gas pressure is 1.0 Pa, and the gas flow rate CF4/Cl2 is 30/30 sccm.
In addition, the taper angle can also be controlled by regulating the flow rate ratio of CF4 in the etching gas (of CF4 and Cl2 gas mixture).
Thus, the taper angle is changed depending on the selectivity ration between the tungsten film and the resist. A relationship of the tungsten film/resist selectivity ratio and the taper angle is shown in
As described above, the taper angle that occurs on the side face of the first gate electrodes can be easily controlled by using an ICP etching apparatus to regulate the bias power density and the reactive gas flow ratio. Note that although the experimental data only shows taper angles in the range of 20° to 80°, angles not greater than 20° (from 3° to 20°) can also be formed by setting the conditions appropriately.
Also, note that a tungsten film is shown as one example in Embodiment 4, but by using an ICP etching apparatus, for conductive films such as Ta, Ti, Mo, Cr, Nb, Si, etc., a tapered shape can easily be made on the edge of a pattern.
In addition, an example is given in which a CF4 and Cl2 gas mixture is used as the etching gas, but it is not necessary to limit the etching gas to this mixture, and it is possible to use a gas mixture of a reactive gas containing fluorine, selected from C2F6 or C4F8, and a gas containing chlorine, selected from Cl2, SiCl4, or BCl3. Furthermore, a gas mixture of CF4 and Cl2 added with 20-60% oxygen may be used as an etching gas.
The etching technique of Embodiment 4 may be combined with the structure of any of Embodiment Mode 1, Embodiment Mode 2, and Embodiments 1 to 3.
It is possible to apply the structure of the present invention to all semiconductor circuits, not only the liquid crystal display device of Embodiment 1. Namely, the present invention may be applied to micro processors such as RISC processors, ASIC processors, etc., and a range from signal processing circuits such as D/A converters, etc. to high frequency circuits of portable devices (portable telephones, PHS, mobile computers).
In addition, it is possible to realize semiconductors devices with three dimensional structures by manufacturing a semiconductor circuit using the present invention on an interlayer insulating film formed on a conventional MOSFET. Thus, it is possible to apply the present invention to all semiconductor devices in which current LSIs are used. In other words, the present invention may be applied to SOI structures (TFT structures using single crystal semiconductor thin films) such as SIMOX, Smart-Cut (a trademark of SOITEC Co.), ELTRAN (a trademark of Canon, Inc.), etc.
Further, the semiconductor circuits of Embodiment 5 can be realized using any combination of Embodiments 1 to 4.
This example demonstrates a process for producing an active matrix type EL (electroluminescence) display device according to the invention of the present application.
The pixel portion, preferably together with the driving circuit, is enclosed by a covering material 6000, a first sealing material (or housing material) 7000, and a second sealing material (or second sealing material) 7001.
In this embodiment, the CMOS circuit shown in
Upon completion of the driving circuit portion 4022 and the pixel portion 4023 according to the invention of the present application, a pixel electrode (cathode) 4025 is formed on the interlayer insulating film (planarizing film) 4024 made of a resin. This pixel electrode 4025 is electrically connected to the drain of TFT 4023 for the pixel portion and may comprise a light-shielding conductive film (representatively, a conductive film including aluminum, copper, or silver as the main component or a laminated film consisting of the above conductive film and another conductive film). Then, an insulating film 4026 is formed on the pixel electrode 4025, and an opening in the insulating film 4026 is formed above the pixel electrode 4025.
Subsequently, the EL (electroluminescence) layer 4027 is formed. It may be of single-layer structure or multi-layer structure by freely combining known EL materials such as a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer. Any known technology may be available for such structure. The EL material is either a low-molecule T material or a high-molecular material (polymer). The former may be applied by vapor deposition, and the latter may be applied by a simple method such as spin coating, printing, or ink-jet method.
In this example, the EL layer is formed by vapor deposition through a shadow mask. The resulting EL layer permits each pixel to emit light differing in wavelength (red, green, and blue). This realizes the color display. Alternative systems available include the combination of color conversion layer (CCM) and color filter and the combination of white light emitting layer and color filter. Needless to say, the EL display device may be monochromatic.
An anode 4028 comprising a transparent conductive film is formed on the EL layer 4027. The transparent conductive film may be formed from a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide. It is desirable to clear moisture and oxygen as much as possible from the interface between the EL layer 4027 and the anode 4028. Accordingly, the object may be achieved by forming the EL layer 4027 and the anode 4028 subsequently in a vacuum, or by forming the EL layer 4027 in an inert atmosphere and then forming the anode 4028 in the same atmosphere without exposing to air. In this Example, the desired film was formed by using a film-forming apparatus of multi-chamber system (cluster tool system).
The anode 4028 is connected to wiring 4016 at a region 4029. The wiring 4016 is a wiring to supply a prescribed voltage to the anode 4028 and is electrically connected to the FPC 4017 through a conductive material 4030.
In the region 4029, the electrical connection between the anode 4028 and the wiring 4016 needs contact holes in the interlayer insulating film 4024 and the insulating film 4026. These contact holes may be formed when the interlayer insulating film 4024 undergoes etching to form the contact hole for the pixel electrode or when the insulating film 4026 undergoes etching to form the opening before the EL layer is formed. When the insulating film 4026 undergoes etching, the interlayer insulating film 4024 may be etched simultaneously. Contact holes of good shape may be formed if the interlayer insulating film 4024 and the insulating film 4026 are made of the same material.
Then, a passivation film 4031 is formed so as to cover the surface of the EL element. Moreover the first sealing material 7000 is formed so as to surround the EL element and to put a covering material 6000 on the substrate 4010. Then a filling material 6004 are formed within a region surrounded by the substrate 4010, the covering material 6000, and the first sealing material 7000.
The filling material 6004 also functions as an adhesive to adhere to the covering material 6000. As the filling material 6004, PVC (polyvinyl chloride), an epoxy resin, a silicon resin, PVB (polyvinyl butyral), or EVA (ethylenvinyl acetate) can be utilized. It is preferable to form a hygroscopic material (e.g. barium oxide) in the filling material 6004, since a moisture absorption effect can be maintained.
Also, spacers can be contained in the filling material 6004. It is preferable to use spherical spacers comprising barium oxide to maintain the moisture absorption in the spacers.
In the case of that the spaces are contained in the filling material, the passivation film 4031 can relieve the pressure of the spacers. Of course, the other film different from the passivation film, such as an organic resin, can be used for relieving the pressure of the spacers.
Moreover, in stead of the filling material, an inert gas (such as argon, helium, and nitrogen) can be introduced into the region surrounded by the substrate 4010, the covering material 6000, and the first sealing material 7000.
As the covering material 6000, a glass plate, a FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a Mylar film, a polyester film or an acryl film can be used. In this embodiment, the covering material should be a transparent material because the light emitted from the EL element goes toward the covering material 6000.
However, when the light emitted from the EL element goes in the opposite direction, a metal plate (e.g. a stainless steel plate), a ceramics plate, and an aluminum foil sandwiched by a PVF film or a Mylar film can be used as the covering material 6000.
The wiring 4016 is electrically connected to FPC 4017 through the gap between the first sealing material 7000 and the substrate 4010. As in the wiring 4016 explained above, other wirings 4014 and 4015 are also electrically connected to FPC 4017 under the first sealing material 7000.
Finally, a second scaling material 7001 is form so as to cover exposed potions of the first sealing material 7000 and a portion of the FPC 4017 for obtaining a structure that cut of the air completely. Accordingly, the EL display device having a cross section shown in
By incorporating the EL display device as described in this Embodiment into the present invention, it is advantageous to obtain an EL display device having a high reliability. The constitution of this Embodiment can be combined with any constitution of Embodiments 1 to 5 in any desired manner.
In this embodiment, the structure of the pixel region in the EL display device in Embodiment 6 is illustrated in more detail.
In this Embodiment, the switching TFT 1702 has such a double-gate structure, but is not limitative. It may have a single-gate structure or a triple-gate structure, or even any other multi-gate structure having more than three gates. As the case may be, the switching TFT 1702 may be PTFT as shown in
The current-control TFT 1703 is NTFT as shown in
It is very important that the current-control TFT 1703 has the structure defined in the invention. The current-control TFT is an element for controlling the quantity of current that passes through the EL device. Therefore, a large quantity of current passes through it, and the element, current-control TFT has a high risk of thermal degradation and degradation with hot carriers. To this element, therefore, the structure of the invention is extremely favorable, in which an LDD region is so constructed that the gate electrode overlaps with the drain area in the current-control TFT, via a gate insulating film therebetween.
In this Embodiment, the current-control TFT 1703 is illustrated to have a single-gate structure, but it may have a multi-gate structure with plural TFTs connected in series. In addition, plural TFTs may be connected in parallel so that the channel forming region is substantially divided into plural sections. In the structure of that type, heat radiation can be effected efficiently. The structure is advantageous for protecting the device with it from thermal deterioration.
On the switching TFT 1702 and the current-control TFT 1703, a first passivation film 1710 is formed. On the film 1710, formed is a planarizing film 1711 of an insulating resin. It is extremely important that the difference in level of the layered portions in TFT is removed through planarization with the planarizing film 1711. This is because the EL layer to be formed on the previously formed layers in the later step is extremely thin, and if there exist a difference in level of the previously formed layers, the EL device will be often troubled by light emission failure. Accordingly, it is desirable to previously planarize as much as possible the previously formed layers before the formation of the pixel electrode thereon so that the EL layer could be formed on the planarized surface.
The reference numeral 1712 indicates a pixel electrode (a cathode in the EL device) of an conductive film with high reflectivity. The pixel electrode 1712 is electrically connected with the drain region in the current-control TFT 1703. In this case, it is preferable that an NTFT is used as the current-control TFT 1703. Also, it is preferable that the pixel electrode 1712 is of a low-resistance conductive film of an aluminum alloy, a copper alloy or a silver alloy, or of a laminate of those films. Needless-to-say, the pixel electrode 1712 may have a laminate structure with any other conductive films.
In the recess (this corresponds to the pixel) formed between the banks 1713 a and 1713 b of an insulating film (preferably of a resin), the light-emitting layer 1714 is formed. In the illustrated structure, only one pixel is shown, but plural light-emitting layers could be separately formed in different pixels, corresponding to different colors of R (red), G (Green) and B (blue). In this Embodiment, the organic EL material for the light-emitting layer may be any n-conjugated polymer material. Typical polymer materials usable herein include polyparaphenylenevinylene (PVV) materials, polyvinylcarbazole (PVK) materials, polyfluorene materials, etc.
Various types of PVV-type organic EL materials are known, such as those disclosed in H. Shenk, H. Becker, O. Gelsen, E. Klunge, W. Kreuder, and H. Spreitzer; Polymers for Light Emitting Diodes, Euro Display Proceedings, 1999, pp. 33-37 and in Japanese Patent Laid-Open No. 10-92576 (1998). Any of such known materials are usable herein.
Concretely, cyanopolyphenylenevinylenes may be used for red-emitting layers; polyphenylenevinylenes may be for green-emitting layers; and polyphenylenevinylenes or polyalkylphenylenes may be for blue-emitting layers. The thickness of the film for the light-emitting layers may fall between 30 and 150 nm (preferably between 40 and 100 nm).
These compounds mentioned above are referred to merely for examples of organic EL materials employable herein and are not limitative at all. The light-emitting layer may be combined with a charge transportation layer or a charge injection layer in any desired manner to form the intended EL layer (this is for light emission and for carrier transfer for light emission).
Specifically, this embodiments to demonstrate an embodiment of using polymer materials to form light-emitting layers, which, however, is not limitative. Low-molecular organic EL materials may also be used for light-emitting layers. For charge transportation layers and charge injection layers, further employable are inorganic materials such as silicon carbide, etc. Various organic EL materials and inorganic materials for those layers are known, any of which are usable herein.
In this Embodiment, a hole injection layer 1715 of PEDOT (polythiophene) or PAni (polyaniline) is formed on the light-emitting layer 1714 to give a laminate structure for the EL layer. On the hole injection layer 1715, formed is an anode 1716 of a transparent conductive film. In this Embodiment, the light having been emitted by the light-emitting layer 1714 radiates therefrom in the direction toward the top surface (that is, in the upward direction of TFT). Therefore, in this, the anode must transmit light. For the transparent conductive film for the anode, usable are compounds of indium oxide and tin oxide, and compounds of indium oxide and zinc oxide. However, since the anode is formed after the light-emitting layer and the hole injection layer having poor heat resistance have been formed, it is preferable that the transparent conductive film for the anode is of a material capable of being formed into a film at as low as possible temperatures.
When the anode 1716 is formed, the EL device 1717 is finished. The EL device 1717 thus fabricated herein indicates a capacitor comprising the pixel electrode (cathode) 1712, the light-emitting layer 1714, the hole injection layer 1715 and the anode 1716. As in
In this Embodiment, a second passivation film 1718 is formed on the anode 1716. For the second passivation film 1718, preferably used is a silicon nitride film or a silicon nitride oxide film. The object of the film 1718 is to insulate the EL device from the outward environment. The film 1718 has the function of preventing the organic EL material from being degraded through oxidation and has the function of preventing it from degassing. With the second passivation film 1718 of that type, the reliability of the EL display device is improved.
As described hereinabove, the EL display device of the invention fabricated in this Embodiment has a pixel portion for the pixel having the constitution as in
The constitution of this Embodiment can be combined with any constitution of Embodiments 1 to 5 in any desired manner.
This Embodiment is to demonstrate a modification of the EL display device of Embodiment 7, in which the EL device 1717 in the pixel portion has a reversed structure. For this Embodiment, referred to is
In this Embodiment, the pixel electrode (anode) 1902 is of a transparent conductive film. Concretely, used is an conductive film of a compound of indium oxide and zinc oxide. Needless-to-say, also usable is an conductive film of a compound of indium oxide and tin oxide.
After the banks 1903 a and 1903 b of an insulating film have been formed, a light-emitting layer 1904 of polyvinylcarbazole is formed between them in a solution coating method. On the light-emitting layer 1904, formed are an electron injection layer 1905 made of alkali metal complex (e.g. acetylacetonatopotassium), and a cathode 1906 of an aluminum alloy. In this case, the cathode 1906 serves also as a passivation film. Thus is fabricated the EL device 1907.
In this Embodiment, the light having been emitted by the light-emitting layer 1904 radiates in the direction toward the substrate with TFT formed thereon, as in the direction of the arrow illustrated.
The constitution of this Embodiment can be combined with any constitution of Embodiments 1 to 5 in any desired manner.
This Embodiment is to demonstrate modifications of the pixel with the circuit structure of
In the embodiment of
In the embodiment of
The structure of the embodiment of
The constitution of this Embodiment can be combined with any constitution of Embodiment 1 to 5 in any desired manner.
The embodiment of Embodiment 7 illustrated in
In the embodiment of Embodiment 7, the current-control TFT 1703 is NTFT as shown in
The parasitic capacitance in question varies, depending on the area in which the gate electrode overlaps with the LDD region, and is therefore determined according to the length of the LDD region in the overlapped area.
Also in the embodiments of Embodiment 9 illustrated in
The constitution of this Embodiment can be combined with any constitution of Embodiment 1 to 5 in any desired manner.
In addition to nematic liquid crystals, it is possible to use many kinds of liquid crystals for the electro-optical devices of the present invention, specifically the liquid crystal display devices of the present invention. For example, it is possible to use the liquid crystals published in any of the following papers: H. Furue et al, “Characteristics and Driving Scheme of Polymer-Stabilized Monostable FLCD Exhibiting Fast Response Time and High Contrast Ratio with Gray-Scale Capability”, SID, 1998; T. Yoshida, T. et al, “A Full-Color Thresholdless Antiferroelectric LCD Exhibiting Wide Viewing Angle with Fast Response Time”, SID DIGEST, 841, 1997; S. Inui et al, “Thresholdless Antiferroelectricity in Liquid Crystals and its Application to Displays”, J. Mater. Chem., 6(4), 1996, p. 671-673; and in U.S. Pat. No. 5,594,569.
In addition, ferroelectric liquid crystals (FLCs) showing a phase transition system of an isotropic phase—cholesterol phase—chiralsumectic C phase is used, and a phase transition is caused while applying a DC voltage, from the cholesterol phase to the chiralsumectic C phase. The resulting electro-optical characteristics of the monostable FLC in which the cone edge is made to nearly conform with the rubbing direction are shown in
The display mode of the ferroelectric liquid crystal as shown in
As shown in
In addition, a liquid crystal that exhibits an anti-ferroelectric phase in a certain temperature range is called an anti-ferroelectric liquid crystal (AFLC). There are mixed liquid crystals that have an anti-ferroelectric liquid crystal, which show electro-optical response characteristics in which the transmittance continuously changes in response to the electric field, and are called thresholdless antiferroelectric mixed liquid crystals. There are thresholdless antiferroelectric mixed liquid crystals that show V-type electro-optical response characteristics, and some have been shown to have a drive voltage of approximately ±2.5 V (when the cell thickness is between 1 and 2 μm).
Further, in general the spontaneous polarization of a thresholdless antiferroelectric mixed liquid crystal is large, and the dielectric constant of the liquid crystal itself is high. Thus, a relatively large retention capacitance is required for pixels when a thresholdless antiferroelectric mixed liquid crystal is used for a liquid crystal display device. Therefore, it is desirable to use a Thresholdless antiferroelectric mixed liquid crystal that has a small spontaneous polarization.
Note that by using this type of thresholdless antiferroelectric mixed liquid crystal in the liquid crystal display devices of the present invention, a low drive voltage can be realized, so low power consumption can also be realized.
The liquid crystal described in Embodiment 11 can be employed in the liquid crystal display device having the structure of any of Embodiments 1 to 4.
The electro-optical device or semiconductor device according to the present invention can be employed as a display section or a signal processing circuit in electronic equipment. As such electronic equipment, a video camera, a digital camera, a projector, a projection television, a goggle-type display (head mount display), a navigation system for vehicles, a sound reproduction device, a note-type personal computer, game equipment, a portable information terminal (a mobile computer, a cellular phone, a handheld game unit, or an electronic book, etc.), an imaging device equipped with recording medium, and the like may be enumerated. Examples of those are shown in
A description of an optical engine will be made in detail with reference to
The optical engine shown in
In addition, as shown in
As described above, the scope of application of the semiconductor device of the present invention is very broad, and the present invention can be applied to electronic equipment of any field. The semiconductor device of Embodiment 12 can be realized even if the structure of any combination of Embodiments 1 to 11 is used.
It is possible to increase the reliability of an NTFT by implementing the present invention. Therefore, it is possible to ensure the reliability of an NTFT having high electrical characteristics (especially high mobility) that demand strict reliability. At the same time, by forming a CMOS circuit with an NTFT and a PTFT that have a superior balance of characteristic, a semiconductor circuit showing is high reliability and outstanding electrical characteristics can be formed.
In addition, the lengths of the second impurity region and/or the third impurity region in the present invention are optimized and made different for circuits having different drive voltages on the same substrate. Thus a circuit can be formed which has an operating speed to meet circuits that demand high operating speed, and a circuit can be formed which has voltage resistance characteristics to meet circuits that demand good voltage resistance characteristics.
Therefore, by appropriately arranging NTFTs with structures corresponding to circuit types (especially when arranged as CMOS circuits), it becomes possible to pull out circuit performance to the most extent, and a semiconductor circuit (or electro-optical device) that has high reliability and good operating performance can be realized.
Furthermore, it is possible to improve the reliability and performance of electronic equipment in which the above electro-optical devices and semiconductor circuits are loaded as parts.