|Publication number||US20100006908 A1|
|Application number||US 12/169,810|
|Publication date||Jan 14, 2010|
|Filing date||Jul 9, 2008|
|Priority date||Jul 9, 2008|
|Also published as||CN102067316A, CN102067316B, EP2311091A2, US8076170, US20110059572, WO2010027395A2, WO2010027395A3|
|Publication number||12169810, 169810, US 2010/0006908 A1, US 2010/006908 A1, US 20100006908 A1, US 20100006908A1, US 2010006908 A1, US 2010006908A1, US-A1-20100006908, US-A1-2010006908, US2010/0006908A1, US2010/006908A1, US20100006908 A1, US20100006908A1, US2010006908 A1, US2010006908A1|
|Inventors||Frederick T. Brady|
|Original Assignee||Brady Frederick T|
|Export Citation||BiBTeX, EndNote, RefMan|
|Referenced by (10), Classifications (13), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention is related to the inventions described in commonly-assigned U.S. Patent Applications Kodak Docket No. 94870, entitled “Color Filter Array Alignment Mark Formation in Backside Illuminated Image Sensors,” Kodak Docket No. 94872, entitled “Wafer Level Processing for Backside Illuminated Image Sensors,” and Kodak Docket No. 94889, entitled “Backside Illuminated Image Sensor with Reduced Dark Current,” which are concurrently filed herewith. The disclosures of these related applications are incorporated by reference herein in their entirety.
The present invention relates generally to electronic image sensors for use in digital cameras and other types of imaging devices, and more particularly to processing techniques for use in forming backside illuminated image sensors.
A typical electronic image sensor comprises a number of light sensitive picture elements (“pixels”) arranged in a two-dimensional array. Such an image sensor may be configured to produce a color image by forming an appropriate color filter array (CFA) over the pixels. Examples of image sensors of this type are disclosed in U.S. Patent Application Publication No. 2007/0024931, entitled “Image Sensor with Improved Light Sensitivity,” which is incorporated by reference herein.
As is well known, an image sensor may be implemented using complementary metal-oxide-semiconductor (CMOS) circuitry. In such an arrangement, each pixel typically comprises a photodiode and other circuitry elements that are formed in a silicon sensor layer on a silicon substrate. One or more dielectric layers are usually formed above the silicon sensor layer and may incorporate additional circuitry elements as well as multiple levels of metallization used to form interconnects. The side of the image sensor on which the dielectric layers and associated levels of metallization are formed is commonly referred to as the frontside, while the side having the silicon substrate is referred to as the backside.
In a frontside illuminated image sensor, light from a subject scene is incident on the frontside of the image sensor, and the silicon substrate is relatively thick. However, the presence of metallization level interconnects and various other features associated with the dielectric layers on the frontside of the image sensor can adversely impact the fill factor and quantum efficiency of the image sensor.
A backside illuminated image sensor addresses the fill factor and quantum efficiency issues associated with the frontside dielectric layers by thinning or removing the thick silicon substrate and arranging the image sensor such that light from a subject scene is incident on the backside of the image sensor. Thus, the incident light is no longer impacted by metallization level interconnects and other features of the dielectric layers, and fill factor and quantum efficiency are improved.
However, in many backside illuminated image sensors, charge storage regions associated with the sensor photodiodes are located a substantial distance away from the backside surface. This is problematic in that many carriers generated by the photodiodes from incident light are lost before they can be collected, for example, due to recombination with other carriers or crosstalk between adjacent photodiodes.
Accordingly, a need exists for an improved backside illuminated image sensor which does not suffer from the excessive carrier loss problem described above.
Illustrative embodiments of the invention provide backside illuminated image sensors having reduced carrier recombination and crosstalk, and thus improved performance.
In accordance with one aspect of the invention, a process of forming a backside illuminated image sensor is provided. The process is a wafer level process for forming a plurality of image sensors each having a pixel array configured for backside illumination, with the image sensors being formed utilizing an image sensor wafer. The image sensor wafer comprises a substrate and a sensor layer formed over the substrate. The process includes the steps of forming backside trenches in a backside surface of the sensor layer, implanting a dopant into the sensor layer through the backside trenches so as to form backside field isolation implant regions corresponding to the backside trenches, filling the backside trenches, forming at least one antireflective layer over the filled backside trenches, and further processing the image sensor wafer to form the plurality of image sensors.
The image sensor wafer may be, for example, a silicon-on-insulator (SOI) wafer having a buried oxide layer arranged between the substrate and the sensor layer, or an epitaxial wafer having a P− sensor layer formed over a P+ substrate.
Prior to forming the backside trenches, a pad oxide layer may be formed over the sensor layer, and a pad nitride layer may be formed over the pad oxide layer. Alignment marks may then be formed that extend through the oxide and nitride layers and into the sensor layer. The backside trenches may be etched through the nitride and oxide layers, and a liner oxide layer may be formed within the backside trenches. The backside trenches may then be filled with a material such as oxide or polysilicon.
The antireflective layer may comprise an antireflective oxide layer formed on the backside surface of the sensor layer, and an antireflective nitride layer formed over the antireflective oxide layer. Prior to or after forming the antireflective oxide layer, a backside passivation implant operation may be performed.
The process may further include a backside well isolation implant operation. This may involve, for example, depositing a photoresist over the antireflective layer, patterning the photoresist to form openings over the backside trenches, and implanting a dopant through the openings to form backside well isolation implant regions corresponding to the backside trenches.
In one of the illustrative embodiments, the step of further processing the image sensor wafer to form the plurality of image sensors further comprises the steps of forming an oxide layer over the antireflective layer, attaching a temporary carrier wafer to a backside surface of the oxide layer, removing the substrate, forming photosensitive elements of the pixel arrays in the sensor layer, forming frontside trenches in a frontside surface of the sensor layer, forming frontside field isolation implant regions corresponding to the frontside trenches, filling the frontside trenches, forming frontside well isolation implant regions corresponding to the frontside trenches, forming at least one dielectric layer on the frontside surface of the sensor layer, attaching a handle wafer to a frontside surface of said at least one dielectric layer, removing the temporary carrier wafer, and separating the image sensor wafer into the plurality of image sensors.
In accordance with another aspect of the invention, a backside illuminated image sensor comprises a sensor layer implementing a plurality of photosensitive elements of a pixel array, an oxide layer adjacent a backside surface of the sensor layer, and at least one dielectric layer adjacent a frontside surface of the sensor layer. The sensor layer further comprises a plurality of backside trenches formed in the backside surface of the sensor layer and arranged to provide isolation between respective pairs of the photosensitive elements. The backside trenches have corresponding backside field isolation implant regions formed in the sensor layer.
A backside illuminated image sensor in accordance with the invention may be advantageously implemented in a digital camera or other type of imaging device, and provides improved performance in such a device without significantly increasing image sensor die size or cost.
The above and other objects, features, and advantages of the present invention will become more apparent when taken in conjunction with the following description and drawings wherein identical reference numerals have been used, where possible, to designate identical features that are common to the figures, and wherein:
The present invention will be illustrated herein in conjunction with particular embodiments of digital cameras, backside illuminated image sensors, and processing techniques for forming such image sensors. It should be understood, however, that these illustrative arrangements are presented by way of example only, and should not be viewed as limiting the scope of the invention in any way. Those skilled in the art will recognize that the disclosed arrangements can be adapted in a straightforward manner for use with a wide variety of other types of imaging devices and image sensors.
Although shown as separate elements in the embodiment of
The image sensor 14 is assumed in the present embodiment to be a CMOS image sensor, although other types of image sensors may be used in implementing the invention. More particularly, the image sensor 14 comprises a backside illuminated image sensor that is formed in a manner to be described below in conjunction with
The image sensor 14 will typically be implemented as a color image sensor having an associated CFA pattern. Examples of CFA patterns that may be used with the image sensor 14 include those described in the above-cited U.S. Patent Application Publication No. 2007/0024931, although other CFA patterns may be used in other embodiments of the invention. As another example, a conventional Bayer pattern may be used, as disclosed in U.S. Pat. No. 3,971,065, entitled “Color Imaging Array,” which is incorporated by reference herein.
The processor 16 may comprise, for example, a microprocessor, a central processing unit (CPU), an application-specific integrated circuit (ASIC), a digital signal processor (DSP), or other processing device, or combinations of multiple such devices. Various elements of the imaging stage 12 and the image sensor 14 may be controlled by timing signals or other signals supplied from the processor 16.
The memory 18 may comprise any type of memory, such as, for example, random access memory (RAM), read-only memory (ROM), Flash memory, disk-based memory, removable memory, or other types of storage elements, in any combination.
Functionality associated with sampling and readout of the pixel array and the processing of corresponding image data may be implemented at least in part in the form of software that is stored in memory 18 and executed by processor 16.
A given image captured by the image sensor 14 may be stored by the processor 16 in memory 18 and presented on display 20. The display 20 is typically an active matrix color liquid crystal display (LCD), although other types of displays may be used. The additional I/O elements 22 may comprise, for example, various on-screen controls, buttons or other user interfaces, network interfaces, memory card interfaces, etc.
Additional details regarding the operation of a digital camera of the type shown in
It is to be appreciated that the digital camera as shown in
The image sensor 14 may be fabricated on a silicon substrate or other type of substrate. In a typical CMOS image sensor, each pixel of the pixel array includes a photodiode and associated circuitry for measuring the light level at that pixel. Such circuitry may comprise, for example, transfer gates, reset transistors, select transistors, output transistors, and other elements, configured in a well-known conventional manner.
As indicated previously, an excessive carrier loss problem can arise in conventional backside illuminated image sensors, due to carrier recombination prior to collection as well as crosstalk between adjacent photodiodes. One possible approach to addressing this problem is to utilize a low-doped epitaxial layer for the sensor layer in which the photodiodes are formed, so as to extend the depletion regions associated with the respective photodiodes and thereby reduce carrier recombination. However, we have discovered that such an approach can lead to increased “dark” current and degradations in quantum efficiency. Techniques for addressing the carrier loss problem without increasing dark current or degrading quantum efficiency will now be described with reference to
The techniques illustrated in
The portions of the image sensor wafers 200 and 210 as shown in
The image sensor wafer 200 or 210 also has a frontside and a backside. With reference to
It should be noted that terms such as “on” or “over” when used in conjunction with layers of an image sensor wafer or corresponding image sensor are intended to be construed broadly, and therefore should not be interpreted to preclude the presence of one or more intervening layers or other intervening image sensor features or elements. Thus, a given layer that is described herein as being formed on or formed over another layer may be separated from the latter layer by one or more additional layers.
Referring now to
For the remaining description of
In the steps illustrated in
As shown in
The alignment marks 300 may comprise polysilicon. Advantageous techniques for forming polysilicon alignment marks of this type in a backside illuminated image sensor are disclosed in the above-cited U.S. Patent Application Kodak Docket No. 94870, although a wide variety of other techniques may be used to form alignment marks 300.
Backside trenches 400 are then formed in the backside surface 206B of the sensor layer 206, as illustrated in
The backside trenches 400 and their associated field isolation implant regions 402 serve to dielectrically isolate the backside of each pixel of the pixel array, which results in less carrier recombination and reduced crosstalk in the completed structure shown in
The backside trenches 400 may be arranged so as to appear as a grid in a top-down plan view of the pixel array area of a given image sensor. In such an arrangement, each photodiode may be located in one of the grid positions so as to be substantially surrounded by backside trenches.
A liner oxide layer may be formed within the backside trenches 400. Typically the liner oxide will have a thickness of about 50 to 150 Angstroms. The field isolation implant can be done before or after the formation of the liner oxide layer.
The dopant used for the field isolation implant is an n-type dopant, such as arsenic or phosphorus, if the pixel array is based on p-type metal-oxide-semiconductor (PMOS) circuitry, while a p-type dopant such as boron or indium would be used if the pixel array is based on n-type metal-oxide-semiconductor (NMOS) circuitry. Typical concentration ranges for the field isolation implant are from about 5×1012 to 5×1013 atoms/cm3.
Referring now to
Antireflective layers are then formed over the filled backside trenches of the sensor layer 206, as illustrated in
The downward pointing arrows in
Like the field isolation implant of
The dopant used for the well isolation implant, like those used for the other implants previously described, will be an n-type dopant for a PMOS pixel array or a p-type dopant for an NMOS pixel array. Suitable concentrations for the well isolation implant are from about 5×1011 to 5×1013 atoms/cm3.
Any remaining portions of the photoresist 700 are then stripped, and an oxide layer 800 is deposited over the antireflective nitride layer 602 as illustrated in
The backside temporary carrier wafer 900 may comprise, for example, a type of wafer commonly referred to as a handle wafer. The temporary carrier wafer may be attached to the image sensor wafer using epoxy or another suitable adhesive.
Although the temporary carrier wafer is shown as a P− wafer in this embodiment, this is by way of example only, and other types of dopings may be used. Also, the sensor layer may use dopings other than those illustrated in the figure. For example, the sensor layer as illustrated in
As illustrated in
The frontside trenches 1102 and their associated implant regions may be formed using techniques similar to those described above for formation of the backside trenches 400 and their associated implant regions.
The dielectric layer 1106 in this embodiment comprises multiple layers of dielectric material and may include, for example, an interlayer dielectric (ILD) and an intermetal dielectric (IMD) that separates multiple levels of metallization. Various image sensor features such as interconnects, gates or other circuitry elements may be formed within the dielectric layer 1106 using conventional techniques. Although only a single dielectric layer 1106 is shown in the diagram of
An oxide layer 1200 is deposited over the dielectric layer 1106 and metal conductors 1108, and then planarized using a CMP operation.
The color filter elements and associated microlenses are aligned with the alignment marks 300, so as to provide accurate alignment between the photodiodes of the sensor layer and the corresponding color filter elements of the CFA.
The resulting processed image sensor wafer is then diced into a plurality of image sensors configured for backside illumination, one of which is the image sensor 14 in digital camera 10. The wafer dicing operation will be described in greater detail below in conjunction with
In an alternative embodiment, a second temporary carrier wafer may be used in place of the handle wafer 1300. The second temporary carrier wafer, like the first temporary carrier wafer 900, may be attached using epoxy or another suitable adhesive. After attachment of the second temporary carrier wafer, a transparent cover sheet comprising transparent covers overlying respective ones of the CFAs may be attached to the backside surface of the image sensor wafer prior to removing the second temporary carrier wafer. Each such glass cover may comprise a central cavity arranged over its corresponding CFA and further comprise peripheral supports secured to the backside surface of the oxide layer 800 via epoxy. The transparent cover sheet may be formed of glass or another transparent material. Such a cover sheet may be attached to the wafer as a single sheet which is divided into separate covers when the image sensors are diced from the wafer. Further details regarding the use of such a temporary carrier wafer and transparent cover sheet may be found in the above-cited U.S. Patent Application Kodak Docket No. 94872. However, it is to be appreciated that use of such elements and associated processing operations is not a requirement of the present invention.
Other illustrative operations that may be performed in a given embodiment of the invention include, for example, the formation of redistribution layer (RDL) conductors, the formation of a passivation layer, and formation of contact metallizations.
As indicated above, the processing operations illustrated in
The above-described illustrative embodiments advantageously provide an improved processing arrangement for forming a backside illuminated image sensor. For example, the process described in conjunction with
The invention has been described in detail with particular reference to certain illustrative embodiments thereof, but it will be understood that variations and modifications can be effected within the scope of the invention as set forth in the appended claims. For example, the invention can be implemented in other types of image sensors and digital imaging devices, using alternative materials, wafers, layers, process steps, etc. Thus, various process parameters such as layer thicknesses and dopant concentrations described in conjunction with the illustrative embodiments can be varied in alternative embodiments. These and other alternative embodiments will be readily apparent to those skilled in the art.
10 digital camera
12 imaging stage
14 backside illuminated image sensor
22 input/output (I/O) elements
200 silicon-on-insulator (SOI) wafer
204 buried oxide (BOX) layer
206 sensor layer
206B sensor layer backside surface
206F sensor layer frontside surface
210 epitaxial wafer
214 sensor layer
220 pad oxide layer
222 pad nitride layer
300 alignment marks
400 backside trench
402 field isolation implant region
500 trench fill material
600 antireflective oxide layer
602 antireflective nitride layer
604 backside passivation implant region
704 backside well isolation implant region
800 backside oxide layer
900 backside temporary carrier wafer
1100 photosensitive elements
1102 frontside trench
1104 frontside well isolation implant region
1106 dielectric layer
1108 last metal layer conductor
1200 oxide layer
1300 frontside handle wafer
1500 image sensor wafer
1502 image sensors
1504 dicing lines
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8119435||Nov 5, 2010||Feb 21, 2012||Omnivision Technologies, Inc.||Wafer level processing for backside illuminated image sensors|
|US8350952||Jun 4, 2008||Jan 8, 2013||Omnivision Technologies, Inc.||Image sensors with improved angle response|
|US8389377||Apr 2, 2010||Mar 5, 2013||Taiwan Semiconductor Manufacturing Company, Ltd.||Sensor element isolation in a backside illuminated image sensor|
|US8552516 *||Jul 2, 2010||Oct 8, 2013||Kabushiki Kaisha Toshiba||Solid state image capture device and method for manufacturing same|
|US8847344||May 30, 2012||Sep 30, 2014||STMicroelectronics (Croles 2) SAS||Process for fabricating a backside-illuminated imaging device and corresponding device|
|US8896712||Jul 20, 2007||Nov 25, 2014||Omnivision Technologies, Inc.||Determining and correcting for imaging device motion during an exposure|
|US8975668 *||Sep 14, 2012||Mar 10, 2015||Intevac, Inc.||Backside-thinned image sensor using Al2 O3 surface passivation|
|US20110084350 *||Apr 14, 2011||Kabushiki Kaisha Toshiba||Solid state image capture device and method for manufacturing same|
|US20130105928 *||Sep 14, 2012||May 2, 2013||Intevac, Inc.||BACKSIDE-THINNED IMAGE SENSOR USING Al2O3 SURFACE PASSIVATION|
|CN102214664A *||Aug 11, 2010||Oct 12, 2011||台湾积体电路制造股份有限公司||Semiconductor device and manufacturing method thereof|
|U.S. Classification||257/291, 257/E31.001, 438/72, 257/E21.001|
|International Classification||H01L31/00, H01L21/00|
|Cooperative Classification||H01L27/14687, H01L27/14632, H01L27/1463, H01L27/1464|
|European Classification||H01L27/146A12, H01L27/146A14, H01L27/146V4|
|Jul 9, 2008||AS||Assignment|
Owner name: EASTMAN KODAK COMPANY, NEW YORK
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BRADY, FREDERICK T.;REEL/FRAME:021211/0479
Effective date: 20080709