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Publication numberUS20100026543 A1
Publication typeApplication
Application numberUS 12/487,723
Publication dateFeb 4, 2010
Filing dateJun 19, 2009
Priority dateAug 1, 2008
Also published asCN101640538A
Publication number12487723, 487723, US 2010/0026543 A1, US 2010/026543 A1, US 20100026543 A1, US 20100026543A1, US 2010026543 A1, US 2010026543A1, US-A1-20100026543, US-A1-2010026543, US2010/0026543A1, US2010/026543A1, US20100026543 A1, US20100026543A1, US2010026543 A1, US2010026543A1
InventorsChih-Hou TSAI, Wei-Ping Wang
Original AssigneeAli Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Analog to digital converter
US 20100026543 A1
Abstract
An analog to digital converter having an input stage amplifier array, an input stage voltage divider array, a comparator array and an encoder. The input stage amplifier array calculates and amplifies the difference between an input signal and a plurality of reference signals to generate a plurality of amplified differences. The input stage voltage divider array averages every two adjacent amplified differences to generate a plurality of average signals. The comparator array compares the average signals with a threshold value and outputs the compared results to the encoder for digital data representing the value of the input signal.
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Claims(6)
1. An analog to digital converter, comprising:
an input stage amplifier array, calculating and amplifying differences between an input signal and a plurality of reference signals to generate a plurality of amplified differences;
an input stage voltage divider array, averaging every two adjacent amplified differences to generate a plurality of average signals;
a comparator array, comparing the average signals with a threshold value to generate a plurality of compared results; and
an encoder, transforming the compared results to digital data to label the value of the input signal.
2. The analog to digital converter as claimed in claim 1, wherein the encoder further comprises:
an output stage voltage divider array, averaging every two adjacent compared results to generate a plurality of average compared results; and
a latch array, receiving the average compared results and outputting the digital data.
3. An analog to digital converter, comprising:
an input stage amplifier array, calculating and amplifying differences between an input signal and a plurality of reference signals to generate a plurality of amplified differences;
an input stage voltage divider array, averaging every two adjacent amplified differences to generate a plurality of average signals;
an intermediate stage amplifier array, amplifying the average signals to generate a plurality of intermediate amplified signals;
an intermediate stage voltage divider array, averaging every two adjacent intermediate amplified signals to generate a plurality of intermediate average signals to be coupled to a comparator array;
the comparator array, comparing the received signals with a threshold value to output a plurality of compared results; and
an encoder, transforming the compared results to digital data to label the value of the input signal.
4. The analog to digital converter as claimed in claim 3, wherein the encoder further comprises:
an output stage voltage divider array, averaging every two adjacent compared results to generate a plurality of average compared results; and
a latch array, receiving the average compared results and outputting the digital data.
5. An analog to digital converter, comprising:
an input stage amplifier array, calculating and amplifying differences between an input signal and a plurality of reference signals to generate a plurality of amplified differences;
an intermediate stage amplifier array, amplifying the amplified differences to generate a plurality of intermediate amplified signals;
an intermediate stage voltage divider array, averaging every two adjacent intermediate amplified signals to generate a plurality of intermediate average signals to be coupled to a comparator array;
the comparator array, comparing the received signals with a threshold value to output a plurality of compared results; and
an encoder, transforming the compared results to digital data to label the value of the input signal.
6. The analog to digital converter as claimed in claim 5, wherein the encoder further comprises:
an output stage voltage divider array, averaging every two adjacent compared results to generate a plurality of average compared results; and
a latch array, receiving the average compared results and outputting the digital data.
Description
    CROSS REFERENCE TO RELATED APPLICATIONS
  • [0001]
    This Application claims priority of China Patent Application No. 200810131308.4, filed on Aug. 1, 2008, the entirety of which is incorporated by reference herein.
  • BACKGROUND OF THE INVENTION
  • [0002]
    1. Field of the Invention
  • [0003]
    The present invention relates to analog to digital converters (ADCs), and in particular relates to flash ADCs.
  • [0004]
    2. Description of the Related Art
  • [0005]
    FIG. 1 illustrates a conventional flash ADC. The input stage comprises an amplifier array 102 comprising amplifiers A1, A2, A3, and A4. The comparator array 104 comprises comparators C1, C2, C3 and C4. The latch array 106 comprises latches L1, L2, L3, and L4. In additional to an input signal, Vin, the amplifiers A1, A2, A3, and A4 further receive reference voltage values V1, V2, V3, and V4, respectively. The progressively increasing, or decreasing reference voltage values V1, V2, V3, and V4 may be provided by a voltage ladder (not shown in the figure).
  • [0006]
    The amplifier array 102 calculates and amplifies the differences between the input signal Vin and the reference voltage values V1, V2, V3 and V4, and outputs amplified differences ad1, ad2, ad3 and ad4. The comparator array 104 compares the amplified differences ad1, ad2, ad3 and ad4 with a threshold value (such as 0 volt) to output compared results cr1, cr2, cr3 and cr4. The latch array 106 works as an encoder, transforming the compared results cr1, cr2, cr3 and cr4 to digital data D1, D2, D3, D4 to label the value of the analog input signal Vin.
  • [0007]
    The conventional flash ADC comprises a large number of amplifiers (A1, A2, A3 and A4) and a large number of comparators (C1, C2, C3 and C4). The conventional flash ADC may malfunction because of defects, such as noise defects or offset defects, of the amplifiers (A1, A2, A3 and A4) and comparators (C1, C2, C3 and C4).
  • BRIEF SUMMARY OF THE INVENTION
  • [0008]
    The invention discloses analog to digital converters (ADCs). An exemplary embodiment of the ADC comprises an input stage amplifier array, an input stage voltage divider array, a comparator array and an encoder. The input stage amplifier array calculates and amplifies differences between an input signal and a plurality of reference signals to generate a plurality of amplified differences. The input stage voltage divider array averages every two adjacent amplified differences to generate a plurality of average signals. The comparator array compares the average signals with a threshold value to generate a plurality of compared results. The encoder transforms the compared results to digital data to label the value of the input signal.
  • [0009]
    In another exemplary embodiment of the invention, the ADC comprises an input stage amplifier array, an input stage voltage divider array, an intermediate stage amplifier array, an intermediate stage voltage divider array, a comparator array and an encoder. The input stage amplifier array calculates and amplifies differences between an input signal and a plurality of reference signals to generate a plurality of amplified differences. The input stage voltage divider array averages every two adjacent amplified differences to generate a plurality of average signals. The intermediate stage amplifier array, amplifies the average signals to generate a plurality of intermediate amplified signals. The intermediate stage voltage divider array averages every two adjacent intermediate amplified signals to generate a plurality of intermediate average signals to be coupled to the comparator array. The comparator array compares the received signals with a threshold value to output a plurality of compared results. The encoder transforms the compared results to digital data to label the value of the input signal.
  • [0010]
    In another exemplary embodiment of the invention, the ADC comprises an input stage amplifier array, an intermediate stage amplifier array, an intermediate stage voltage divider array, a comparator array and an encoder. The input stage amplifier array calculates and amplifies differences between an input signal and a plurality of reference signals to generate a plurality of amplified differences. The intermediate stage amplifier array amplifies the amplified differences to generate a plurality of intermediate amplified signals. The intermediate stage voltage divider array averages every two adjacent intermediate amplified signals to generate a plurality of intermediate average signals to be coupled to the comparator array. The comparator array compares the received signals with a threshold value to output a plurality of compared results. The encoder transforms the compared results to digital data to label the value of the input signal.
  • [0011]
    A detailed description is given in the following embodiments with reference to the accompanying drawings.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0012]
    The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
  • [0013]
    FIG. 1 illustrates a conventional flash ADC;
  • [0014]
    FIG. 2 illustrates an embodiment of the ADC of the invention;
  • [0015]
    FIG. 3 illustrates another embodiment of the ADC of the invention;
  • [0016]
    FIG. 4 illustrates another embodiment of the ADC of the invention; and
  • [0017]
    FIG. 5 illustrates an exemplary circuit of the amplifiers A1 and A2, and the voltage divider vdi1.
  • DETAILED DESCRIPTION OF THE INVENTION
  • [0018]
    The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
  • [0019]
    FIG. 2 illustrates an embodiment of the analog to digital converter (ADC) of the invention. The ADC comprises an input stage amplifier array 202, an input stage voltage divider array 204, a comparator array 206 and an encoder 208. As shown in FIG. 2, the encoder 208 may be realized by an array of latches. The input stage amplifier array 202 comprises a plurality of amplifiers A1, A2, A3, and A4, calculating and amplifying differences between an input signal Vin and a plurality of reference signals V1, V2, V3, and V4 to generate amplified differences ad1, ad2, ad3, and ad4. The reference signals V1, V2, V3, and V4 may be progressively increasing or decreasing voltage values outputted from a voltage ladder (not shown in the figure). The input stage voltage divider array 204 comprises voltage dividers vdi1, vdi2, and vdi3. Each voltage divider (vdi1, vdi2, and vdi3) may comprise two equivalent resistors that are coupled in series. The voltage dividers vdi1, vdi2 and vdi3 are inserted between the output terminals of the amplifiers A1, A2, A3, and A4 to average the adjacent amplified differences to generate average signals vo1<1>, vo1<2>, and vo1<3>. For example, the voltage divider vdi1 averages the amplified differences ad1 and ad2 to generate the average signal vo1<1>; and the voltage divider vdi2 averages the amplified differences ad2 and ad3 to generate the average signal vo1<2> and so on.
  • [0020]
    The comparator array 206 comprises comparators C1, C2, and C3, comparing the average signals vo1<1>, vo1<2> and vo1<3> with a threshold value (such as 0 volt) to generate compared results cr1, cr2 and cr3. The latch array 208 transforms the compared results cr1, cr2 and cr3 to digital data D1, D2 and D3 to label the input signal Vin. The latch array 208 (comprising latches L1, L2, and L3 . . . ) may be replaced by other circuits having an encoding function.
  • [0021]
    The ADC of FIG. 2 has a much better performance than the conventional ADC of FIG. 1. The following compares the digital data D2 of FIGS. 1 and 2. In FIG. 1, the digital signal D2 is usually critically damaged by the noise and offset defects of the amplifier A2. In FIG. 2, however, the voltage divider vdi2 counteracts the noise and offset defects of the amplifiers A2 and A3, and improves the quality of the digital signal D2.
  • [0022]
    FIG. 3 illustrates another embodiment of the ADC of the invention. Compared with FIG. 2, the ADC of FIG. 3 further comprises an output stage voltage divider array 302 coupled between the comparator array 206 and the latch array 208. The output stage voltage divider array comprises voltage dividers vdo1, vdo2 and vdo3. The voltage dividers vdo1, vdo2 and vdo3 are inserted between the output terminals of the comparators C1, C2, and C3 to average the adjacent compared results and generate average compared results vo2<1>, vo2<2> and vo2<3>. For example, the voltage divider vdo2 averages the adjacent compared results cr1 and cr2 to generate the average compared result vo2<2>; and the voltage divider vdo3 averages the adjacent compared results cr2 and cr3 to generate the average compared result vo2<3>, and so on.
  • [0023]
    The following takes the digital data D2 as an example. In FIG. 3, the voltage dividers vdi1 vdi2, and vdo2 counteracts the noise and offset defects of the amplifiers A1, A2 and A3 and the comparators C1 and C2. Thus, the quality of the digital signal D2 is dramatically improved.
  • [0024]
    FIG. 4 illustrates another embodiment of the ADC of the invention. Compared with FIG. 2, the ADC of FIG. 4 further comprises an intermediate amplifier array 402 and an intermediate stage voltage divider array 404 coupled between the input stage voltage divider array 204 and the comparator array 206. The intermediate stage amplifier array 402 comprises amplifiers B1, B2, and B3, amplifying the average values vo1<1>, vo1<2>, and vo1<3> to generate intermediate amplified signals vo3<1>, vo3<2>, and vo3<3>. The intermediate stage voltage divider array 404 comprises voltage dividers vdb1, vdb2, and vdb3. Each voltage divider may comprise two equivalent resistors that are coupled in series. The voltage dividers vdb1, vdb2, and vdb3 are inserted between the output terminals of the amplifiers B1, B2 and B3 to average the adjacent amplified differences and generate intermediate average signals vo4<1>, vo4<2> and vo4<3>. For example, the voltage divider vdb2 averages the intermediate amplified signals vo3<1> and vo3<2> to generate the intermediate average signal vo4<2>; and the voltage divider vdb3 averages the intermediate amplified signals vo3<2> and vo3<3> to generate the intermediate average signal vo4<3> and so on.
  • [0025]
    The following takes the digital data D2 as an example. In FIG. 4, the voltage dividers vdi1 vdi2, and vdb2 counteracts the noise and offset defects of the amplifiers A1, A2, A3, B1 and B2. Thus, the quality of the digital signal D2 is dramatically improved.
  • [0026]
    Another exemplary embodiment of the ADC integrates the output stage voltage divider array (302 of FIG. 3) into the ADC of FIG. 4, wherein the output stage voltage divider array 302 is coupled between the comparator array 206 and the latch array 208.
  • [0027]
    Another exemplary embodiment of the ADC comprises more than one intermediate stage (each intermediate stage comprises an intermediate stage amplifier array 402 and an intermediate stage voltage divider array 404 as shown in FIG. 4) between the input stage voltage divider array 204 and the comparator array 206.
  • [0028]
    Some exemplary embodiments of the invention may take the aforementioned input stage voltage divider array 204 and output stage voltage divider array 302 as optional components. For example, an ADC comprising only the intermediate stage voltage divider array 404 but neither of the input stage voltage divider array 204 and the output stage voltage divider array 302 is in the scope of our invention.
  • [0029]
    Some exemplary embodiments of the invention may take the input stage voltage divider array 204 and intermediate stage voltage divider array 404 as optional components. For example, an ADC comprising only the output stage voltage divider array 302 but neither of the input stage voltage divider array 204 and the intermediate stage voltage divider array 404 is in the scope of our invention.
  • [0030]
    ADCs comprising any of the aforementioned voltage divider arrays 204, 302 and 404 are in the scope of our invention.
  • [0031]
    FIG. 5 illustrates an exemplary circuit of the amplifiers A1 and A2, and the voltage divider vdi1. The voltage divider vdi1 comprises resistors R1A, R1B, R1C and R1D. The amplifier A1 comprises a pair of transistors M1 and M2 (forming a differential pair) and a pair of resistors R0A and R0B. The amplifier A1 has a gain G, wherein
  • [0000]
    G = ad 1 V in - V 1 = g m 0 B k = - N N C k - 1 1 - ( k γ ) 2 1 - ( k γ ) 2 2 , Formula ( 1 )
  • [0000]
    where gm0 is the maximum transconductance of the differential pair. When the resistors R0A and R0B are of the same resistance R0 and the resistors R1A, R1B, R1C and R1D follow the following equation, R1A=R1B=R1C=R1D=R1/2, the values of B and C of Formula (1) are:
  • [0000]
    B = R 1 2 ( 1 + 2 R 0 R 1 1 + 4 R 0 R 1 - 1 ) ; C = 2 R 0 R 1 1 + 2 R 0 R 1 + 1 + 4 R 0 R 1 .
  • [0000]
    When the reference signals for adjacent amplifiers follow the equation, V1−V2=V2−V3=V3−V4= . . . =VR, and the overdrive voltage of the differential pair is VOVD, the value γ of Formula (1) follows the following equation,
  • [0000]
    γ = V 1 - V 2 2 V OVD = V R 2 V OVD .
  • [0000]
    Furthermore, the value N of the Formula (1) is 1/γ, indicating the number of working amplifiers of the circuit of FIG. 4.
  • [0032]
    For example, when the resistance R0 is 2KΩ, the resistance R1 is 200Ω and the overdrive voltage VOVD is 100 mV, the voltage value VR is 7.8 mV, and the maximum transconductance of the differential pair gm0 is 2 mA/V, and the gain G of the amplifier A1 is 3.9. When the consecutive amplifier B1 has an offset defect of 30 mV, it involves the offset of the amplifier A1 by 7.7 mV (30 mV/3.9).
  • [0033]
    If the voltage divider vdi1 is coupled between the amplifiers A1 and A4 rather than between the amplifiers A1 and A2, the value γ is 3 times larger than the aforementioned one
  • [0000]
    γ = V 1 - V 4 2 V OVD = 3 V R 2 V OVD .
  • [0000]
    In this case, the gain G of the amplifier A1 is 3.2. The 30 mV offset defect of the amplifier B1 involves the offset of the amplifier A1 by 9.4 mV (30 mV/3.2), which is worse than the aforementioned case. Thus, the ADCs of the invention, which insert voltage dividers between the adjacent outputs of an amplifier array, have a much better performance than the ADCs which try to solve the amplifier defects by coupling the amplifiers that are far apart from each other.
  • [0034]
    While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Patent Citations
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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US8165666Aug 24, 2011Apr 24, 2012Topera, Inc.System and method for reconstructing cardiac activation information
US8594777Apr 3, 2012Nov 26, 2013The Reagents Of The University Of CaliforniaSystem and method for reconstructing cardiac activation information
US9295399Jun 20, 2013Mar 29, 2016Intermountain Invention Management, LlcAtrial fibrillation treatment systems and methods
US20120193995 *Aug 2, 2012Sony CorporationVoltage generation circuit, resonance circuit, communication apparatus, communication system, wireless charging system, power supply apparatus, and electronic apparatus
Classifications
U.S. Classification341/155
International ClassificationH03M1/12
Cooperative ClassificationH03M1/361, H03M1/0646
European ClassificationH03M1/06M7S1
Legal Events
DateCodeEventDescription
Jun 19, 2009ASAssignment
Owner name: ALI CORPORATION,TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TSAI, CHIH-HOU;WANG, WEI-PING;REEL/FRAME:022848/0622
Effective date: 20090314