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Publication numberUS20100044850 A1
Publication typeApplication
Application numberUS 12/405,043
Publication dateFeb 25, 2010
Filing dateMar 16, 2009
Priority dateAug 21, 2008
Also published asCN101656234A, CN101656234B, CN101656238A, CN101656238B, US8237250, US20100044843
Publication number12405043, 405043, US 2010/0044850 A1, US 2010/044850 A1, US 20100044850 A1, US 20100044850A1, US 2010044850 A1, US 2010044850A1, US-A1-20100044850, US-A1-2010044850, US2010/0044850A1, US2010/044850A1, US20100044850 A1, US20100044850A1, US2010044850 A1, US2010044850A1
InventorsChun-Hung Lin, Pao-Huei Chang Chien, Ping-Cheng Hu, Wei-Lun Cheng
Original AssigneeAdvanced Semiconductor Engineering, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Advanced quad flat non-leaded package structure and manufacturing method thereof
US 20100044850 A1
Abstract
An advanced quad flat non-leaded package structure includes a carrier, a chip and a molding compound. The carrier includes a die pad and a plurality of leads. The die pad has a central portion, a peripheral portion disposed around the central portion and a plurality of connecting portions connecting the central portion and the peripheral portion. The central portion, the peripheral portion, and the connecting portions define at least two hollow regions. The leads are disposed around the die pad. The chip is located within the central portion of the die pad and electrically connected to the leads via a plurality of wires. The molding compound encapsulates the chip, the wires, inner leads and a portion of the carrier.
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Claims(15)
1. An advanced quad flat non-leaded package structure, comprising:
a carrier, having an upper surface, wherein the carrier comprises:
a die pad, having a central portion, a peripheral portion and a plurality of connecting portions, wherein the peripheral portion is disposed around the central portion, the connecting portions connect the central portion and the peripheral portion, the connecting portions are separated from one another, and the central portion, the peripheral portion, and the connecting portions define at least two hollow regions; and
a plurality of leads, disposed around the die pad, wherein each of the leads includes an inner lead disposed over the upper surface and an outer lead disposed over the lower surface; and
a chip, disposed on the upper surface of the carrier and located within the central portion of the die pad, wherein the chip is electrically connected to the inner leads via a plurality of wires; and
a molding compound, encapsulating the chip, the wires, the inner leads, and a portion of the carrier.
2. The advanced quad flat non-leaded package structure as claimed in claim 1, wherein the peripheral portion of the die pad functions as a ground ring, wherein the peripheral portion of the die pad is electrically connected to the chip via the wires.
3. The advanced quad flat non-leaded package structure as claimed in claim 2, wherein the carrier further comprises at least a power ring, wherein the power ring is disposed between the leads and the peripheral portion of the die pad and electrically connected to the chip via wires, and the power ring is electrically isolated from the ground ring.
4. The advanced quad flat non-leaded package structure as claimed in claim 1, further comprises an adhesive layer disposed between the chip and the central portion of the die pad.
5. The advanced quad flat non-leaded package structure as claimed in claim 1, wherein the central portion of the die pad has a polygonal shape.
6. The advanced quad flat non-leaded package structure as claimed in claim 5, wherein the peripheral portion is connected to at least a side of the central portion through the connecting portions.
7. The advanced quad flat non-leaded package structure as claimed in claim 5, wherein the peripheral portion is connected to at least a corner of the central portion through the connecting portions.
8. The advanced quad flat non-leaded package structure as claimed in claim 1, wherein a material of the leads comprises gold or palladium.
9. The advanced quad flat non-leaded package structure as claimed in claim 1, wherein a distance between any two adjacent leads is greater than or equal to 400 micrometers.
10. The advanced quad flat non-leaded package structure as claimed in claim 1, wherein a bottom surface of the central portion is coplanar with that of the peripheral portion, an upper surface of the central portion is not coplanar with that of the peripheral portion.
11. The advanced quad flat non-leaded package structure as claimed in claim 1, wherein a distance between an edge of the chip and an edge of the central portion is greater than or equal to 300 micrometers.
12. A manufacturing method of an advanced quad flat non-leaded package structure, comprising:
providing a carrier having a first patterned metal layer formed on an upper surface of the carrier, and a second patterned metal layer formed on a lower surface of the carrier, wherein the carrier includes at least an accommodating cavity and a plurality of first openings;
providing a chip, wherein the chip is disposed on a central portion of the accommodating cavity and electrically connected to the first patterned metal layer of the carrier via a plurality of wires;
forming a molding compound to encapsulate the chip, the wires, the first patterned metal layer of the carrier, and fill the accommodating cavity and the first openings; and
performing an etching process to the lower surface of the carrier using the second patterned metal layer as a mask, so that the carrier is etched through to expose the molding compound filled inside the first openings and simultaneously form a plurality of second openings and a plurality of third openings.
13. The manufacturing method of the advanced quad flat non-leaded package structure as claimed in claim 12, wherein the carrier is defined into a plurality of leads and a die pad by the second openings following the etching process.
14. The manufacturing method of the advanced quad flat non-leaded package structure as claimed in claim 13, wherein the die pad is simultaneously defined into the central portion, a peripheral portion and a plurality of connecting portions by the third openings.
15. The manufacturing method of the advanced quad flat non-leaded package structure as claimed in claim 12, wherein before the chip is provided, the method further comprises forming an adhesive layer on the central portion of the accommodating cavity.
Description
CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of U.S.A. provisional application Ser. No. 61/090,879, filed on Aug. 21, 2008. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a package structure and a manufacturing method thereof. More particularly, the present invention relates to an advanced quad flat non-leaded (a-QFN) package structure and manufacturing method thereof.

2. Description of Related Art

A quad flat package (QFP) can be divided as I-type (QFI), J-type (QFJ) and non-lead-type (QFN) packages, according to the shape of the lead of leadframes. Since the QFN package structure has relatively shorter signal traces and a faster speed for signal transmission, it has become one popular choice for the package structures with low pin count, and is suitable for the chip package with high-frequency (for example, radio frequency bandwidth) transmission.

In general, in the manufacturing process of the QFN package structure, a plurality of chips is disposed on the leadframe and is electrically connected to the leadframe by means of a plurality of bonding wires. Then, a molding compound is formed to encapsulate the leadframe, the chips and the bonding wires. Finally, a plurality of QFN packages structure is formed through a singulation process.

SUMMARY OF THE INVENTION

The present invention is directed to an advanced quad flat non-leaded package structure and a manufacturing method thereof having reduced of the die pad exposure area to lower the risk of delamination.

In order to achieve the above object, the present invention provides an advanced quad flat non-leaded package structure. The advanced quad flat non-leaded package structure includes a carrier, a chip and a molding compound. The carrier has an upper surface and a lower surface opposite to the upper surface. The carrier includes a die pad and a plurality of leads. The die pad has a central portion, a peripheral portion and a plurality of connecting portions. The peripheral portion is disposed around the central portion. The connecting portions connect the central portion and the peripheral portion. The connecting portions are separated from on another. The peripheral portion, the connecting portions and the central portion define at least two hollow regions. The leads are disposed around the die pad, wherein each of the leads includes an inner lead disposed over the upper surface and an outer lead disposed over the lower surface. The chip is disposed on the upper surface of the carrier and located within the central portion of the die pad, wherein the chip is electrically connected to the inner leads via a plurality of wires. The molding compound encapsulates the chip, the wires, the inner leads and a portion of the carrier.

According to an embodiment of the present invention, the peripheral portion of the die pad functions as a ground ring, wherein the peripheral portion of the die pad is electrically connected to the chip via the wires.

According to an embodiment of the present invention, the carrier further includes at least a power ring, wherein the power ring is disposed between the leads and the peripheral portion of the die pad and electrically connected to the chip via wires, and the power ring is electrically isolated from the ground ring.

According to an embodiment of the present invention, the advanced quad flat non-leaded package structure further includes an adhesive layer disposed between the chip and the central portion of the die pad.

According to an embodiment of the present invention, the central portion of the die pad has a polygonal shape.

According to an embodiment of the present invention, the peripheral portion is connected to at least a side of the central portion through the connecting portions.

According to an embodiment of the present invention, the peripheral portion is connected to at least a corner of the central portion through the connecting portions.

According to an embodiment of the present invention, a material of the leads comprises gold or palladium.

According to an embodiment of the present invention, a distance between any two adjacent leads is greater than or equal to 400 micrometers.

According to an embodiment of the present invention, the bottom surface of the central portion is coplanar with the bottom surface of the peripheral portion, while the upper surface of the central portion is not coplanar with the upper surface of the peripheral portion.

According to an embodiment of the present invention, a distance between the edge of the chip and the edge of the central portion is greater than or equal to 300 micrometers.

The present invention further provides a manufacturing method of an advanced quad flat non-leaded package structure, which includes the following steps. First, a carrier having a first patterned metal layer formed on an upper surface of the carrier, and a second patterned metal layer formed on a lower surface of the carrier is provided. The carrier includes at least an accommodating cavity and a plurality of first opening. Next, a chip is provided. The chip is disposed on the central portion of the accommodating cavity and electrically connected to the first patterned metal layer of the carrier via a plurality of wires. Then, a molding compound is formed to encapsulate the chip, the wires, the first patterned metal layer of the carrier, and fill the accommodating cavity and the first openings. After that, an etching process is performed to the lower surface of the carrier using the second patterned metal layer as a mask, so as to the carrier is etched through to expose the molding filled inside the first openings and simultaneously form a plurality of second openings and a plurality of third openings.

According to an embodiment of the present invention, the carrier is defined into a plurality of leads and a die pad by the second openings following the etching process.

According to an embodiment of the present invention, the die pad is simultaneously defined into a central portion, a peripheral portion and a plurality of connecting portions by the third openings.

According to an embodiment of the present invention, before the chip is provided, the manufacturing method of an advanced quad flat non-leaded package structure further includes forming an adhesive layer on the central portion of the accommodating cavity.

Based on the above, according to the present invention, there are several hollow regions located in the die pad of the carrier, and the molding compound is exposed by the hollow regions. Hence, the contact area of the molding compound and the die pad is decreased and the peeling issue between the molding compound and the die pad due to uneven stress between heterogeneous materials can be alleviated. On the other hand, the chip located on the central portion of the die pad is encapsulated and protected by the molding compound.

In order to make the above and other features and advantages of the present invention more comprehensible, several embodiments accompanied with figures are described in detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1A is a back-side view illustrating an advanced quad flat non-leaded package structure according to an embodiment of the present invention.

FIG. 1B is a cross-sectional view of the structure depicted in FIG. 1A along a line I-I′.

FIG. 1C is a cross-sectional view of the structure depicted in FIG. 1A along a line II-II′.

FIG. 2 is a back-side view illustrating an advanced quad flat non-leaded package structure according to another embodiment of the present invention.

FIGS. 3A through 3I are schematic cross-sectional views illustrating a manufacturing method of an advanced quad flat non-leaded package structure according to an embodiment of the present invention. Herein, the sub-diagrams (a) for FIG. 3H is schematic cross-sectional views depicted in the process for FIG. 1A along the line I-I′. The sub-diagrams (b) for FIG. 3H is schematic cross-sectional views depicted in the process for FIG. 1A along the line II-II′.

DESCRIPTION OF THE EMBODIMENTS

Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

FIG. 1A is a back-side view illustrating an advanced quad flat non-leaded package structure according to an embodiment of the present invention. FIG. 1B is a cross-sectional view of the structure depicted in FIG. 1A along a line I-I′. FIG. 1C is a cross-sectional view of the structure depicted in FIG. 1A along a line II-II′. Referring to FIGS. 1A, 1B and 1C, in the present embodiment, an advanced quad flat non-leaded (a-QFN) package structure 100 includes a carrier 200, a chip 300 and a molding compound 500.

The carrier 200 in the present embodiment is, for example, a leadframe. In detail, the carrier 200 has an upper surface 210 a and a lower surface 210 b opposite to the upper surface 210 a. The carrier 200 includes a die pad 220 and a plurality of leads 230, wherein the die pad 220 has a central portion 222, a peripheral portion 224 and a plurality of connecting portions 226. In FIG. 1A, four of the connecting portions 226 are schematically depicted. However, the die pad 220 may include one or more connecting portions 226, and the number of the connecting portion(s) 226 is not limited by the examples herein. The peripheral portion 224 surrounds the central portion 222. The connecting portions 226 connect the central portion 222 and the peripheral portion 224. Since the connecting portion 226 are separated from one another, four hollow regions S are defined by the peripheral portion 224, the connecting portions 226 and the central portion 222. The number of the hollow regions S is not limited by the examples herein, but is determined by the number of the connecting portion(s) 226 present in the carrier 200.

In more details, the central portion 222 of the die pad 220 in the present embodiment has a rectangular shape. The bottom surface 222 b of the central portion 222 is coplanar with the bottom surface 224 b of the peripheral portion 224, and the upper surface 222 a of the central portion 222 is not coplanar with the upper surface 224 a of the peripheral portion 224. As shown in FIG. 1C, the upper surface 224 a of the peripheral portion 224 is higher than the upper surface 222 a of the central portion 222. However, the central portion 222 of the die pad 220 may be in a polygonal shape. The connecting portion 226 is arranged at either a side or a corner of the central portion 222. Specifically, the connecting portions 226 in the present embodiment connect four sides of the central portion 222 with the peripheral portion 224. It should be noted that the location, the arrangement or the amount of the connecting portions 226 can be adjusted depending on the requirements of molding processes. In another embodiment according to the present invention, the die pad 220 only has two connecting portions 226, and the peripheral portion 224 is connected to two corners of the central portion 222 through the connecting portions 226, as shown in FIG. 2.

Referring to FIGS. 1A and 1B, the leads 230 are disposed around the die pad 220, wherein each of the leads 230 includes an inner lead 232 and an outer lead 234. For instance, the leads 230 can be arranged along both sides of the die pad 220 or arranged around the die pad 220. The arrangement of the leads 230 can be, for example, an array, multiple column or rows, or arranged in the ring shape. The arrangement of the leads 230 can be customized according to client's request or product requests. The material of the leads 230 comprises gold or palladium, for example.

Further, the distance between any two adjacent leads 230 is greater than or equal to 400 micrometers.

The chip 300 is disposed in the central portion 222 of the die pad 220 and on the upper surface 210 a of the carrier 200. The chip 300 is electrically connected to the inner leads 232 and the peripheral portion 224 via a plurality of wires 400. Further, a distance d between the edge of the chip 300 and the edge of the central portion 222 is greater than or equal to 300 micrometers.

The molding compound 500 encapsulates the chip 300, the wires 400, the inner leads 232, a portion of the die pad 220. In other words, the outer leads 234 and the bottom surface of the die pad 220 is not covered by the molding compound 500. Further, the molding compound 500 is exposed by the hollow regions S of the die pad 220 and the gaps between the leads 230. Due to the hollow regions S of the die pad 220, delamination between the molding compound 500 and the die pad 220 is decreased. A material of the molding compound 500 is, for example, epoxy resin or other applicable polymer material.

Furthermore, in the present embodiment, for the a-QFN package structure 100, the peripheral portion 224 of the die pad 220 may function as a ground ring, for example. Also, the carrier 200 may further include at least a power ring 240. The power ring 240 is disposed between the leads 230 and the peripheral portion 224 of the die pad 220 and electrically connected to the chip 300 via the wires 400. The power ring 240 is electrically isolated from the ground ring 224.

Moreover, the a-QFN package structure 100 in the present embodiment further includes an adhesive layer 600. The adhesive layer 600 is disposed between the chip 300 and the central portion 222 of the die pad 220 for fixing the chip 300 to the central portion 222.

In brief the a-QFN package structure 100/100 a in the present embodiment has at least two hollow regions S located between the peripheral portion 224 and the central portion 222 of the die pad 220, and the molding compound 500 is exposed by hollow regions S. Hence, the peeling issue between the molding compound 500 and the die pad 220 due to metal oxidation or uneven stress can be relieved.

The process for manufacturing the a-QFN package structure 100 of the present invention is accordingly provided below for elaborating the process for manufacturing the a-QFN package structure 100 as indicated in FIGS. 3A through 3I.

FIGS. 3A through 3I are schematic cross-sectional views illustrating a manufacturing method of an advanced quad flat non-leaded package structure according to an embodiment of the present invention. Herein, the sub-diagrams (a) for FIG. 3H is schematic cross-sectional views depicted in the process for FIG. 1A along the line I-I′. The sub-diagrams (b) for FIG. 3H is schematic cross-sectional views depicted in the process for FIG. 1A along the line II-II′. For the convenience of description, the power rings are omitted in the present embodiment.

As shown in FIG. 3A, a substrate 210 having the upper surface 210 a and the lower surface 210 b is provided. A material of the substrate 210 is, for example, copper, copper alloy, or other applicable metal materials. Next, still referring to the FIG. 3A, a first patterned photoresist layer 214 a is formed on the upper surface 210 a of the substrate 210 and a second patterned photoresist layer 214 b is formed on the lower surface 212 b of the substrate 210.

Next, referring to the FIG. 3B, a first metal layer 216 a is formed on the exposed portion of the upper surface 210 a of the substrate 210 and a second metal layer 216 b is formed on the exposed portion of the lower surface 210 b of the substrate 210. In the present embodiment, a method of forming the first metal layer 216 a and the second metal layer 216 b is, for example, plating.

Next, referring to the FIG. 3C, the first patterned photoresist layer 214 a is removed to form the first patterned metal layer 218 a on the upper surface 210 a of the substrate 210.

Next, referring to the FIG. 3D, a portion of the substrate 210 is removed by performing an etching process using the first patterned metal layer 218 a as an etching mask, so as to form at least an accommodating cavity 220 a and a plurality of first openings S1. Then, the second patterned photoresist layer 214 b is removed to form the second patterned metal layer 218 b on the lower surface 210 b of the substrate 210. The individual portions of the first patterned metal layer 218 a separated from one another by the first openings S1 will subsequently be formed into a plurality of inner leads 232. The pattern of the first patterned metal layer 218 a and that of the second patterned metal layer 218 b are not the same or are not symmetrical. At this stage, the carrier 200 is roughly formed.

Next, referring to the FIG. 3E, a chip 300 is provided to a central portion 222 of each of the accommodating cavities 220 a and an adhesive layer 600 is formed between the chip 300 and the central portion 222 of each accommodating cavity 220 a. The adhesive layer 600 disposed between the chip 300 and the central portion 222 of the accommodating cavities 220 a can help fixing the chip 300 to the central portion 222.

Next, referring to the FIG. 3F, the chips 300 are electrically connected to the to-be-formed inner leads 232 via the wires 400.

Next, referring to the FIG. 3G, a molding compound 500 is formed to encapsulate the chips 300, the wires 400, the to-be-formed inner leads 232, and fill the accommodating cavity 220 a and the first openings S1.

Then, referring to the FIGS. 3H (a) and 3H (b), an etching process is performed to the exposed lower surface 210 b (as shown in FIG. 3G) of the carrier 200 using the second patterned metal layer 218 b as a mask, so as to etch through the exposed substrate 210 (i.e. the leadframe). Therefore, the molding compound 500 inside the first openings S1 is exposed and a plurality of second openings S2 and a plurality of third openings S3 are formed simultaneously.

Specifically, due to the formation of the second openings S2, the substrate 210 is etched through, and the inner leads 232 and outer leads 234 are defined. The inner leads 232 are physically and electrically separated from one another by the first openings S1. The outer leads 234 are physically and electrically separated from one another by the second openings S2. The third openings S3 define the substrate 210 within each accommodating cavity 220 a to form the die pad 220 having the central portion 222, the peripheral portion 224 surrounding the central portion 222 and a plurality of connecting portions 226. The connecting portions 226 are separated from one another by the third openings S3.

In more detail, the central portion 222 of the die pad 220 is surrounded by the peripheral portion 224 and the connecting portions 226 connect the central portion 222 and the peripheral portion 224. As shown in FIG. 1C, the bottom surface 222 b of the central portion 222 is coplanar with the bottom surfaces 224 b/226 b of the peripheral portion 224 and the connecting portions 226, and the upper surface 222 a of the central portion 222 is coplanar with the upper surfaces 226 a of the connecting portions 226, but is not coplanar with the upper surface 224 a of the peripheral portion 224. A distance d between the edge of the chip 300 and the edge of the central portion 222 is greater than or equal to 300 micrometers.

After that, referring to the FIG. 3I, a singulation process is performed by a sawing process. The singulation process may optionally further include a punch process. The purpose of the singulation is to fully cut through the carrier 200 and the molding compound 500, so as to obtain a plurality of individual a-QFN package structure 100. In FIG. 3I, only two of the a-QFN package structure 100 are schematically depicted.

Briefly, the second opening and the third opening on are formed simultaneously by the etching process employed to the lower surface of the substrate. The molding compound is exposed through the second opening and the third opening. Furthermore, owning to the formation of the openings, the contact area between the leadframe (die pad) and the molding compound is decreased, thus avoiding delamination and improving both the manufacturing quality and the production yield.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US8115285 *Aug 15, 2008Feb 14, 2012Advanced Semiconductor Engineering, Inc.Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof
US8203201 *Mar 26, 2010Jun 19, 2012Stats Chippac Ltd.Integrated circuit packaging system with leads and method of manufacture thereof
US8241956 *Mar 8, 2010Aug 14, 2012Stats Chippac, Ltd.Semiconductor device and method of forming wafer level multi-row etched lead package
US8492883 *Aug 15, 2008Jul 23, 2013Advanced Semiconductor Engineering, Inc.Semiconductor package having a cavity structure
US8546903 *Oct 7, 2010Oct 1, 2013Texas Instruments IncorporatedIonic isolation ring
US8575742 *Apr 6, 2009Nov 5, 2013Amkor Technology, Inc.Semiconductor device with increased I/O leadframe including power bars
US8623711 *Dec 15, 2011Jan 7, 2014Stats Chippac Ltd.Integrated circuit packaging system with package-on-package and method of manufacture thereof
US8629567Dec 15, 2011Jan 14, 2014Stats Chippac Ltd.Integrated circuit packaging system with contacts and method of manufacture thereof
US8669654 *Aug 3, 2011Mar 11, 2014Stats Chippac Ltd.Integrated circuit packaging system with die paddle and method of manufacture thereof
US20090230523 *Aug 15, 2008Sep 17, 2009Pao-Huei Chang ChienAdvanced quad flat no lead chip package having a cavity structure and manufacturing methods thereof
US20110215449 *Mar 8, 2010Sep 8, 2011Stats Chippac, Ltd.Semiconductor Device and Method of Forming Wafer Level Multi-Row Etched Lead Package
US20110233753 *Mar 26, 2010Sep 29, 2011Zigmund Ramirez CamachoIntegrated circuit packaging system with leads and method of manufacture thereof
US20120032315 *Aug 3, 2011Feb 9, 2012Byung Tai DoIntegrated circuit packaging system with die paddle and method of manufacture thereof
US20120086098 *Oct 7, 2010Apr 12, 2012Texas Instruments IncorporatedIonic isolation ring
US20120104585 *Oct 28, 2011May 3, 2012Emmanuel EspirituIntegrated circuit packaging system with lead frame and method of manufacture thereof
US20130252377 *May 19, 2013Sep 26, 2013Advanced Analogic Technologies (Hong Kong) LimitedProcess For Fabricating Multi-Die Semiconductor Package With One Or More Embedded Die Pads
Legal Events
DateCodeEventDescription
Mar 16, 2009ASAssignment
Owner name: ADVANCED SEMICONDUCTOR ENGINEERING, INC.,TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LIN, CHUN-HUNG;CHANG-CHIEN, PAO-HUEI;HU, PING-CHENG AND OTHERS;US-ASSIGNMENT DATABASE UPDATED:20100225;REEL/FRAME:22405/293
Effective date: 20090310
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LIN, CHUN-HUNG;CHANG-CHIEN, PAO-HUEI;HU, PING-CHENG;AND OTHERS;REEL/FRAME:022405/0293