US20100124801A1 - Electronic package structure and method - Google Patents

Electronic package structure and method Download PDF

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Publication number
US20100124801A1
US20100124801A1 US12/693,719 US69371910A US2010124801A1 US 20100124801 A1 US20100124801 A1 US 20100124801A1 US 69371910 A US69371910 A US 69371910A US 2010124801 A1 US2010124801 A1 US 2010124801A1
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United States
Prior art keywords
bonding
conductive strip
lead
die
electronic package
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Abandoned
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US12/693,719
Inventor
Yu-Lin Yang
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Richtek Technology Corp
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Richtek Technology Corp
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Priority to US12/693,719 priority Critical patent/US20100124801A1/en
Publication of US20100124801A1 publication Critical patent/US20100124801A1/en
Abandoned legal-status Critical Current

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    • H01L23/495Lead-frames or other flat leads
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Definitions

  • the present invention is related generally to integrated circuit (IC) products and, more particularly, to an electronic package structure and method.
  • dice are cut from wafers by a dicing process, then each die is attached to a package substrate or a chip carrier of a leadframe, the inputs/outputs of the die are electrically connected to leads of the leadframe by a bonding process, and finally, plastic, ceramic or metal is used to encapsulate the die except that the outer leads of the leadframe are left exposed outside the package for connecting to other electronic components.
  • This process is called electronic package method. With the protection of the electronic package, the IC components in the die may avoid damages from external environment or forces.
  • wire bonding For an electronic package, there are three popular bonding processes, wire bonding, tape automatic bonding (TAB) and flip-chip bonding, among which the wire bonding is the most often used.
  • the wire bonding process uses a bonder to bond one end of a wire to a bonding pad on a die and the other end to a lead of a leadframe.
  • the commonly used wires include aluminum wires, gold wires, silver wires and so on.
  • the thickness of a single wire or the number of wires will be proportional to the current to be carried. The greater the current to be carried, the larger the thickness of a single wire or the number of wires is.
  • An object of the present invention is to provide an electronic package structure for high current applications.
  • Another object of the present invention is to provide a stronger electronic package structure.
  • Still another object of the present invention is to provide a low-cost electronic package structure and method.
  • an electronic package structure comprises a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead.
  • a conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires.
  • the bonding of the conductive strip may be carried out by a surface mounting technology (SMT).
  • SMT surface mounting technology
  • the conductive strip is applied with a bonding material thereon and then bonded to a bump on a die.
  • the bonding material is spotted or printed on a chip carrier and a lead, and then the conductive strip is bonded to the chip carrier and the lead.
  • SMT process requires lower cost than wire bonding processes.
  • a conductive strip may be bonded to more than two dice or leads to save more bonding wires.
  • a conductive strip is stronger than a bonding wire, and thus lowers the possibility of being broken.
  • a conductive strip may easily replace bonding wires to carry greater current no matter in single-chip packages and multi-chip packages.
  • inventive method can be used together with conventional wire bonding processes, in which convention bonding wires are for small current conducting, and conductive strips are for greater current conducting.
  • FIG. 1 shows a first embodiment according to the present invention
  • FIG. 2 shows a second embodiment according to the present invention
  • FIG. 3 shows a third embodiment according to the present invention
  • FIG. 4 shows a fourth embodiment according to the present invention
  • FIG. 5 shows a fifth embodiment according to the present invention
  • FIG. 6 shows a sixth embodiment according to the present invention
  • FIG. 7 is a schematic view showing a conductive strip bonded to two dice.
  • FIG. 8 is a schematic view showing a conductive strip bonded to a lead and a chip carrier.
  • FIG. 1 shows a first embodiment according to the present invention, which uses a conductive strip for a multi-chip package.
  • Dice 16 and 18 are attached on two portions of a chip carrier 12 , a supporting frame 14 supports the chip carrier 12 , and a plurality of leads 10 surrounds the chip carrier 12 .
  • Bonding pads 162 and 182 are on the dice 16 and 18 and electrically connected to the circuits in the dice 16 and 18 , respectively.
  • a conductive strip 20 is bonded to the bonding pads 162 and 182 and thus electrically connects the dice 16 and 18 to each other.
  • FIG. 2 shows a second embodiment according to the present invention, in which dice 22 , 24 and 26 are attached on three portions of a chip carrier 12 and have bonding pads 222 , 242 and 262 thereon, respectively, and a conductive strip 28 is bonded to the bonding pads 222 , 242 and 262 to electrically connect the dice 22 , 24 and 26 to each other.
  • FIG. 3 shows a third embodiment according to the present invention, which uses a bonding wire and a conductive strip for an electronic package.
  • a chip carrier 12 carries dice 30 , 32 , 34 and 36 on its four portions respectively, and a conductive strip 38 is bonded to the bonding pads 322 , 342 and 362 on the dice 32 , 34 and 36 respectively.
  • the conductive strip 38 is of a triangle shape to avoid the die 30 .
  • a bonding wire 40 is bonded by a conventional wire bonding process to the bonding pad 302 of the die 30 and the bonding pad 324 of the die 32 .
  • FIG. 4 shows a fourth embodiment according to the present invention, which has dice 42 and 44 attached on a chip carrier 12 of a leadframe, a conductive strip 46 bonded to a lead 10 of the leadframe and a bonding pad 422 on the die 42 , and another conductive strip 48 bonded to a bonding pad 442 on the die 44 and another lead 48 of the leadframe.
  • FIG. 5 shows a fifth embodiment according to the present invention, which uses conductive strips for a single-chip package.
  • a die 50 is attached on a chip carrier 12 of a leadframe, a bonding wire 52 is bonded to a bonding pad 502 on the die 50 and a lead 10 of the leadframe, a bonding wire 54 is bonded to another bonding pad 502 on the die 50 and the chip carrier 12 , and a conductive strip 56 is bonded to another lead 10 of the leadframe and the chip carrier 12 .
  • FIG. 6 shows a sixth embodiment according to the present invention, in which a bonding wire 62 is bonded to a bonding pad 582 on a die 58 and a lead 10 of a leadframe, another bonding wire 60 is bonded to another bonding pad 582 on the die 58 and a chip carrier 12 of the leadframe, and a conductive strip 64 is bonded to two neighboring leads 10 of the leadframe.
  • the portions of a chip carrier for dice to be attached thereon may be electrically connected to each other, for example in the case of a metal chip carrier; or they may be electrically insulated from each other, for example in the case of a ceramic or plastic chip carrier.
  • a conductive strip for electronic package structure and method according to the present invention may have various sizes and shapes based on their applications and may be bonded to several dice.
  • the dice to be bonded by a conductive strip in an electronic package structure and method according to the present invention are attached on a same chip carrier, dice attached on different chip carriers may be bonded by a conductive strip in some applications according to the present invention.
  • the conductive strip used in an electronic package structure and method according to the present invention is a metal, such as copper, silver and lead.
  • FIG. 7 is a schematic view showing a conductive strip bonded to two dice in an electronic package method according to the present invention.
  • solder paste is generally used as a bonding material, and screen printing, needle spotting or dispensing is used to apply the bonding material to predetermined locations.
  • the components to be bonded are disposed on the solder paste at those locations, and then heat treatment or UV light is applied to harden the solder paste so as to bond the components.
  • bumps 662 and 682 are grown on dice 66 and 68 in advance. Bonding material such as solder paste is applied on a conductive strip 70 , and then the conductive strip 70 is disposed on the bumps 662 and 682 with the bonding material therebetween. After heat treatment, the bonding material, the conductive strip 70 and the bumps 662 and 682 are eutectically solidified, and thus the conductive strip 70 and the bumps 662 and 682 are bonded together.
  • FIG. 8 is a schematic view showing a conductive strip bonded to a lead and a chip carrier in an electronic package method according to the present invention.
  • Bonding material 76 is applied on a lead 72 and a chip carrier 74 at predetermined locations by spotting or dispensing, and then the conductive strip 70 is disposed on the lead 72 and the chip carrier 74 with the bonding material 76 therebetween. After heat treatment, the bonding material, the conductive strip 70 , the lead 72 and the chip carrier 74 are eutectically solidified. In addition, printing may be used instead, to apply the bonding material 76 on the predetermined locations.
  • the bonding material 76 may be other than solder, for example conductive glue or silver glue.

Abstract

An electronic package structure and method use a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead. A conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires. The bonding of the conductive strip may be carried out by an SMT process, and thus requires lower cost than wire bonding processes. A conductive strip may be bonded to more than two dice or leads to save more bonding wires. A conductive strip is stronger than a bonding wire, and thus lowers the possibility of being broken.

Description

    RELATED APPLICATIONS
  • This application is a Divisional patent application of co-pending application Ser. No. 12/068,773, filed on 12 Feb. 2008. The entire disclosure of the prior application Ser. No. 12/068,773, from which an oath or declaration is supplied, is considered a part of the disclosure of the accompanying Divisional application and is hereby incorporated by reference.
  • FIELD OF THE INVENTION
  • The present invention is related generally to integrated circuit (IC) products and, more particularly, to an electronic package structure and method.
  • BACKGROUND OF THE INVENTION
  • In a typical semiconductor process, dice are cut from wafers by a dicing process, then each die is attached to a package substrate or a chip carrier of a leadframe, the inputs/outputs of the die are electrically connected to leads of the leadframe by a bonding process, and finally, plastic, ceramic or metal is used to encapsulate the die except that the outer leads of the leadframe are left exposed outside the package for connecting to other electronic components. This process is called electronic package method. With the protection of the electronic package, the IC components in the die may avoid damages from external environment or forces.
  • For an electronic package, there are three popular bonding processes, wire bonding, tape automatic bonding (TAB) and flip-chip bonding, among which the wire bonding is the most often used. The wire bonding process uses a bonder to bond one end of a wire to a bonding pad on a die and the other end to a lead of a leadframe. The commonly used wires include aluminum wires, gold wires, silver wires and so on. The thickness of a single wire or the number of wires will be proportional to the current to be carried. The greater the current to be carried, the larger the thickness of a single wire or the number of wires is. For instance, for power input and output of a power management chip, sometimes more than five bonding wires are bonded to a bonding pad of the chip because great current will flow therethrough. Such high current applications result in high cost and low yield packages. In some circumstances, for example, if non-uniform contact resistance is present between several wires bonded on a same bonding pad, or some of the bonding wires are broken, there will be a single one among the bonding wires carrying the high current and thus being broken.
  • SUMMARY OF THE INVENTION
  • An object of the present invention is to provide an electronic package structure for high current applications.
  • Another object of the present invention is to provide a stronger electronic package structure.
  • Still another object of the present invention is to provide a low-cost electronic package structure and method.
  • According to the present invention, an electronic package structure comprises a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead.
  • A conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires.
  • The bonding of the conductive strip may be carried out by a surface mounting technology (SMT). Preferably, the conductive strip is applied with a bonding material thereon and then bonded to a bump on a die. Alternatively, the bonding material is spotted or printed on a chip carrier and a lead, and then the conductive strip is bonded to the chip carrier and the lead. SMT process requires lower cost than wire bonding processes.
  • A conductive strip may be bonded to more than two dice or leads to save more bonding wires.
  • A conductive strip is stronger than a bonding wire, and thus lowers the possibility of being broken.
  • A conductive strip may easily replace bonding wires to carry greater current no matter in single-chip packages and multi-chip packages.
  • The inventive method can be used together with conventional wire bonding processes, in which convention bonding wires are for small current conducting, and conductive strips are for greater current conducting.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 shows a first embodiment according to the present invention;
  • FIG. 2 shows a second embodiment according to the present invention;
  • FIG. 3 shows a third embodiment according to the present invention;
  • FIG. 4 shows a fourth embodiment according to the present invention;
  • FIG. 5 shows a fifth embodiment according to the present invention;
  • FIG. 6 shows a sixth embodiment according to the present invention;
  • FIG. 7 is a schematic view showing a conductive strip bonded to two dice; and
  • FIG. 8 is a schematic view showing a conductive strip bonded to a lead and a chip carrier.
  • DETAILED DESCRIPTION OF THE INVENTION
  • FIG. 1 shows a first embodiment according to the present invention, which uses a conductive strip for a multi-chip package. Dice 16 and 18 are attached on two portions of a chip carrier 12, a supporting frame 14 supports the chip carrier 12, and a plurality of leads 10 surrounds the chip carrier 12. Bonding pads 162 and 182 are on the dice 16 and 18 and electrically connected to the circuits in the dice 16 and 18, respectively. A conductive strip 20 is bonded to the bonding pads 162 and 182 and thus electrically connects the dice 16 and 18 to each other.
  • FIG. 2 shows a second embodiment according to the present invention, in which dice 22, 24 and 26 are attached on three portions of a chip carrier 12 and have bonding pads 222, 242 and 262 thereon, respectively, and a conductive strip 28 is bonded to the bonding pads 222, 242 and 262 to electrically connect the dice 22, 24 and 26 to each other.
  • FIG. 3 shows a third embodiment according to the present invention, which uses a bonding wire and a conductive strip for an electronic package. A chip carrier 12 carries dice 30, 32, 34 and 36 on its four portions respectively, and a conductive strip 38 is bonded to the bonding pads 322, 342 and 362 on the dice 32, 34 and 36 respectively. The conductive strip 38 is of a triangle shape to avoid the die 30. A bonding wire 40 is bonded by a conventional wire bonding process to the bonding pad 302 of the die 30 and the bonding pad 324 of the die 32.
  • FIG. 4 shows a fourth embodiment according to the present invention, which has dice 42 and 44 attached on a chip carrier 12 of a leadframe, a conductive strip 46 bonded to a lead 10 of the leadframe and a bonding pad 422 on the die 42, and another conductive strip 48 bonded to a bonding pad 442 on the die 44 and another lead 48 of the leadframe.
  • FIG. 5 shows a fifth embodiment according to the present invention, which uses conductive strips for a single-chip package. A die 50 is attached on a chip carrier 12 of a leadframe, a bonding wire 52 is bonded to a bonding pad 502 on the die 50 and a lead 10 of the leadframe, a bonding wire 54 is bonded to another bonding pad 502 on the die 50 and the chip carrier 12, and a conductive strip 56 is bonded to another lead 10 of the leadframe and the chip carrier 12.
  • FIG. 6 shows a sixth embodiment according to the present invention, in which a bonding wire 62 is bonded to a bonding pad 582 on a die 58 and a lead 10 of a leadframe, another bonding wire 60 is bonded to another bonding pad 582 on the die 58 and a chip carrier 12 of the leadframe, and a conductive strip 64 is bonded to two neighboring leads 10 of the leadframe.
  • The portions of a chip carrier for dice to be attached thereon may be electrically connected to each other, for example in the case of a metal chip carrier; or they may be electrically insulated from each other, for example in the case of a ceramic or plastic chip carrier.
  • As shown in the above embodiments, a conductive strip for electronic package structure and method according to the present invention may have various sizes and shapes based on their applications and may be bonded to several dice. In addition, in the above embodiments, although it is shown that the dice to be bonded by a conductive strip in an electronic package structure and method according to the present invention are attached on a same chip carrier, dice attached on different chip carriers may be bonded by a conductive strip in some applications according to the present invention.
  • Preferably, the conductive strip used in an electronic package structure and method according to the present invention is a metal, such as copper, silver and lead.
  • FIG. 7 is a schematic view showing a conductive strip bonded to two dice in an electronic package method according to the present invention. In a typical SMT process, solder paste is generally used as a bonding material, and screen printing, needle spotting or dispensing is used to apply the bonding material to predetermined locations. The components to be bonded are disposed on the solder paste at those locations, and then heat treatment or UV light is applied to harden the solder paste so as to bond the components. In this embodiment, bumps 662 and 682 are grown on dice 66 and 68 in advance. Bonding material such as solder paste is applied on a conductive strip 70, and then the conductive strip 70 is disposed on the bumps 662 and 682 with the bonding material therebetween. After heat treatment, the bonding material, the conductive strip 70 and the bumps 662 and 682 are eutectically solidified, and thus the conductive strip 70 and the bumps 662 and 682 are bonded together.
  • FIG. 8 is a schematic view showing a conductive strip bonded to a lead and a chip carrier in an electronic package method according to the present invention. Bonding material 76 is applied on a lead 72 and a chip carrier 74 at predetermined locations by spotting or dispensing, and then the conductive strip 70 is disposed on the lead 72 and the chip carrier 74 with the bonding material 76 therebetween. After heat treatment, the bonding material, the conductive strip 70, the lead 72 and the chip carrier 74 are eutectically solidified. In addition, printing may be used instead, to apply the bonding material 76 on the predetermined locations. The bonding material 76 may be other than solder, for example conductive glue or silver glue.
  • While the present invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope thereof as set forth in the appended claims.

Claims (5)

1. An electronic package method comprising the steps of:
providing a die having a bonding pad thereon and a lead of a leadframe; and
bonding a conductive strip to the bonding pad and the lead.
2. The electronic package method of claim 1, further comprising the step of attaching the die on a chip carrier of the leadframe.
3. The electronic package method of claim 1, wherein the step of bonding a conductive strip to the bonding pad and the lead comprises the steps of:
applying a bonding material on the conductive strip, or on the bonding pad and the lead;
disposing the conductive strip on the bonding pad and the lead with the bonding material therebetween; and
heat treatment for bonding the conductive strip to the bonding pad and the lead with the bonding material.
4. The electronic package method of claim 3, wherein the bonding pad has a bump thereon, and the conductive strip is bonded thereon.
5. The electronic package method of claim 1, wherein the step of applying a bonding material on the conductive strip, or on the bonding pad and the lead comprises the step of printing or spotting the bonding material on the conductive strip, or on the bonding pad and the lead.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200836315A (en) * 2007-02-16 2008-09-01 Richtek Techohnology Corp Electronic package structure and method thereof
US7898067B2 (en) * 2008-10-31 2011-03-01 Fairchild Semiconductor Corporaton Pre-molded, clip-bonded multi-die semiconductor package
CA3035966A1 (en) * 2016-09-06 2018-03-15 The Regents Of The University Of California Formulations of hydroxypyridonate actinide/lanthanide decorporation agents

Citations (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3387365A (en) * 1965-09-28 1968-06-11 John P. Stelmak Method of making electrical connections to a miniature electronic component
US3738560A (en) * 1970-12-08 1973-06-12 Kulicke & Soffa Ind Inc Semiconductor die bonder
US4411719A (en) * 1980-02-07 1983-10-25 Westinghouse Electric Corp. Apparatus and method for tape bonding and testing of integrated circuit chips
US4722060A (en) * 1984-03-22 1988-01-26 Thomson Components-Mostek Corporation Integrated-circuit leadframe adapted for a simultaneous bonding operation
US4935803A (en) * 1988-09-09 1990-06-19 Motorola, Inc. Self-centering electrode for power devices
US5173766A (en) * 1990-06-25 1992-12-22 Lsi Logic Corporation Semiconductor device package and method of making such a package
US5248895A (en) * 1991-01-21 1993-09-28 Kabushiki Kaisha Toshiba Semiconductor apparatus having resin encapsulated tab tape connections
US5296737A (en) * 1990-09-06 1994-03-22 Hitachi, Ltd. Semiconductor device with a plurality of face to face chips
US5329158A (en) * 1990-03-23 1994-07-12 Motorola Inc. Surface mountable semiconductor device having self loaded solder joints
US5349238A (en) * 1991-09-25 1994-09-20 Sony Corporation Semiconductor device
US5449951A (en) * 1992-01-17 1995-09-12 Olin Corporation Lead frames with improved adhesion to a polymer
US5498901A (en) * 1994-08-23 1996-03-12 National Semiconductor Corporation Lead frame having layered conductive planes
US5646831A (en) * 1995-12-28 1997-07-08 Vlsi Technology, Inc. Electrically enhanced power quad flat pack arrangement
US5742009A (en) * 1995-10-12 1998-04-21 Vlsi Technology Corporation Printed circuit board layout to minimize the clock delay caused by mismatch in length of metal lines and enhance the thermal performance of microeletronics packages via condution through the package leads
US5889317A (en) * 1997-04-09 1999-03-30 Sitron Precision Co., Ltd. Leadframe for integrated circuit package
US5994767A (en) * 1997-04-09 1999-11-30 Sitron Precision Co., Ltd. Leadframe for integrated circuit package and method of manufacturing the same
US6066888A (en) * 1997-02-17 2000-05-23 Seiko Epson Corporation Tape carrier and tape carrier device using the same
US6242281B1 (en) * 1998-06-10 2001-06-05 Asat, Limited Saw-singulated leadless plastic chip carrier
US6258622B1 (en) * 1999-06-07 2001-07-10 Apack Technologies Inc. Flip clip bonding leadframe-type packaging method for integrated circuit device and a device formed by the packaging method
US6336269B1 (en) * 1993-11-16 2002-01-08 Benjamin N. Eldridge Method of fabricating an interconnection element
US6528868B1 (en) * 1998-02-21 2003-03-04 Robert Bosch Gmbh Lead frame device and method for producing the same
US20040135237A1 (en) * 2001-04-18 2004-07-15 Norihide Funato Semiconductor device and method of manufacturing the same
US6812554B2 (en) * 1999-02-17 2004-11-02 Renesas Technology Corp. Semiconductor device and a method of manufacturing the same
US6856007B2 (en) * 2001-08-28 2005-02-15 Tessera, Inc. High-frequency chip packages
US6921967B2 (en) * 2003-09-24 2005-07-26 Amkor Technology, Inc. Reinforced die pad support structure
US7176506B2 (en) * 2001-08-28 2007-02-13 Tessera, Inc. High frequency chip packages with connecting elements
US20080128903A1 (en) * 2006-10-31 2008-06-05 Sanyo Electric Co., Ltd. Semiconductor module, method for manufacturing semiconductor modules and mobile device
US7411293B2 (en) * 2005-09-27 2008-08-12 Kingston Technology Corporation Flash memory card
US20080197507A1 (en) * 2007-02-16 2008-08-21 Yu-Lin Yang Electronic package structure and method
US20080197464A1 (en) * 2005-02-23 2008-08-21 Nxp B.V. Integrated Circuit Device Package with an Additional Contact Pad, a Lead Frame and an Electronic Device
US7435619B2 (en) * 2006-02-14 2008-10-14 Stats Chippac Ltd. Method of fabricating a 3-D package stacking system
US20080265384A1 (en) * 2005-02-23 2008-10-30 Nxp B.V. Integrated Circuit Package Device With Improved Bond Pad Connections, a Lead-Frame and an Electronic Device
US7456088B2 (en) * 2006-01-04 2008-11-25 Stats Chippac Ltd. Integrated circuit package system including stacked die
US7645634B2 (en) * 2005-06-20 2010-01-12 Stats Chippac Ltd. Method of fabricating module having stacked chip scale semiconductor packages
US7692295B2 (en) * 2006-03-31 2010-04-06 Intel Corporation Single package wireless communication device
US7741567B2 (en) * 2008-05-19 2010-06-22 Texas Instruments Incorporated Integrated circuit package having integrated faraday shield
US7750482B2 (en) * 2006-02-09 2010-07-06 Stats Chippac Ltd. Integrated circuit package system including zero fillet resin
US7763963B2 (en) * 2005-05-04 2010-07-27 Stats Chippac Ltd. Stacked package semiconductor module having packages stacked in a cavity in the module substrate
US7772696B2 (en) * 2007-08-30 2010-08-10 Nvidia Corporation IC package having IC-to-PCB interconnects on the top and bottom of the package substrate
US7786575B2 (en) * 2006-09-15 2010-08-31 Stats Chippac Ltd. Stacked die semiconductor device having circuit tape
US7795727B2 (en) * 2006-04-05 2010-09-14 Infineon Technologies Ag Semiconductor module having discrete components and method for producing the same
US7855100B2 (en) * 2005-03-31 2010-12-21 Stats Chippac Ltd. Integrated circuit package system with an encapsulant cavity and method of fabrication thereof
US7936054B2 (en) * 2007-12-13 2011-05-03 Fairchild Korea Semiconductor Ltd. Multi-chip package
US20110115069A1 (en) * 2009-11-13 2011-05-19 Serene Seoh Hian Teh Electronic device including a packaging substrate and an electrical conductor within a via and a process of forming the same

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL296629A (en) * 1963-08-13
US3757175A (en) * 1971-01-06 1973-09-04 Soo Kim Chang Tor chips mounted on a single substrate composite integrated circuits with coplnaar connections to semiconduc
US4251852A (en) * 1979-06-18 1981-02-17 International Business Machines Corporation Integrated circuit package
US4512509A (en) * 1983-02-25 1985-04-23 At&T Technologies, Inc. Technique for bonding a chip carrier to a metallized substrate
US4647959A (en) * 1985-05-20 1987-03-03 Tektronix, Inc. Integrated circuit package, and method of forming an integrated circuit package
JPH074995B2 (en) * 1986-05-20 1995-01-25 株式会社東芝 IC card and method of manufacturing the same
FR2599893B1 (en) * 1986-05-23 1996-08-02 Ricoh Kk METHOD FOR MOUNTING AN ELECTRONIC MODULE ON A SUBSTRATE AND INTEGRATED CIRCUIT CARD
US4783695A (en) * 1986-09-26 1988-11-08 General Electric Company Multichip integrated circuit packaging configuration and method
US4766479A (en) * 1986-10-14 1988-08-23 Hughes Aircraft Company Low resistance electrical interconnection for synchronous rectifiers
US4744008A (en) * 1986-11-18 1988-05-10 International Business Machines Corporation Flexible film chip carrier with decoupling capacitors
JP2579937B2 (en) * 1987-04-15 1997-02-12 株式会社東芝 Electronic circuit device and method of manufacturing the same
US5084753A (en) * 1989-01-23 1992-01-28 Analog Devices, Inc. Packaging for multiple chips on a single leadframe
US5241456A (en) * 1990-07-02 1993-08-31 General Electric Company Compact high density interconnect structure
US5091769A (en) * 1991-03-27 1992-02-25 Eichelberger Charles W Configuration for testing and burn-in of integrated circuit chips
US5225633A (en) * 1991-10-04 1993-07-06 The United States Of America As Represented By The Secretary Of The Air Force Bridge chip interconnect system
JP2501266B2 (en) * 1991-11-15 1996-05-29 株式会社東芝 Semiconductor module
US6407434B1 (en) * 1994-11-02 2002-06-18 Lsi Logic Corporation Hexagonal architecture
WO1996036071A2 (en) * 1995-05-12 1996-11-14 Philips Electronics N.V. Method of manufacturing a semiconductor device suitable for surface mounting
KR0148082B1 (en) * 1995-08-16 1998-08-01 김광호 Stack semiconductor package and package socket
US6130116A (en) * 1996-12-13 2000-10-10 Tessera, Inc. Method of encapsulating a microelectronic assembly utilizing a barrier
US6159765A (en) * 1998-03-06 2000-12-12 Microchip Technology, Incorporated Integrated circuit package having interchip bonding and method therefor
SG93192A1 (en) * 1999-01-28 2002-12-17 United Microelectronics Corp Face-to-face multi chip package
JP3560488B2 (en) * 1999-01-29 2004-09-02 ユナイテッド マイクロエレクトロニクス コープ Chip scale package for multichip
US6396148B1 (en) * 2000-02-10 2002-05-28 Epic Technologies, Inc. Electroless metal connection structures and methods
US6429536B1 (en) * 2000-07-12 2002-08-06 Advanced Semiconductor Engineering, Inc. Semiconductor device
DE10142117A1 (en) * 2001-08-30 2003-03-27 Infineon Technologies Ag Electronic component with at least two stacked semiconductor chips and method for its production
US20040152242A1 (en) * 2003-01-30 2004-08-05 Wong Chun Kit Device package utilizing interconnect strips to make connections between package and die
DE10317018A1 (en) * 2003-04-11 2004-11-18 Infineon Technologies Ag Multichip module with several semiconductor chips and printed circuit board with several components
JP4426955B2 (en) * 2004-11-30 2010-03-03 株式会社ルネサステクノロジ Semiconductor device
US7649245B2 (en) * 2005-05-04 2010-01-19 Sun Microsystems, Inc. Structures and methods for a flexible bridge that enables high-bandwidth communication
US7834464B2 (en) * 2007-10-09 2010-11-16 Infineon Technologies Ag Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device

Patent Citations (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3387365A (en) * 1965-09-28 1968-06-11 John P. Stelmak Method of making electrical connections to a miniature electronic component
US3738560A (en) * 1970-12-08 1973-06-12 Kulicke & Soffa Ind Inc Semiconductor die bonder
US4411719A (en) * 1980-02-07 1983-10-25 Westinghouse Electric Corp. Apparatus and method for tape bonding and testing of integrated circuit chips
US4722060A (en) * 1984-03-22 1988-01-26 Thomson Components-Mostek Corporation Integrated-circuit leadframe adapted for a simultaneous bonding operation
US4935803A (en) * 1988-09-09 1990-06-19 Motorola, Inc. Self-centering electrode for power devices
US5329158A (en) * 1990-03-23 1994-07-12 Motorola Inc. Surface mountable semiconductor device having self loaded solder joints
US5173766A (en) * 1990-06-25 1992-12-22 Lsi Logic Corporation Semiconductor device package and method of making such a package
US5296737A (en) * 1990-09-06 1994-03-22 Hitachi, Ltd. Semiconductor device with a plurality of face to face chips
US5248895A (en) * 1991-01-21 1993-09-28 Kabushiki Kaisha Toshiba Semiconductor apparatus having resin encapsulated tab tape connections
US5349238A (en) * 1991-09-25 1994-09-20 Sony Corporation Semiconductor device
US5449951A (en) * 1992-01-17 1995-09-12 Olin Corporation Lead frames with improved adhesion to a polymer
US6336269B1 (en) * 1993-11-16 2002-01-08 Benjamin N. Eldridge Method of fabricating an interconnection element
US5498901A (en) * 1994-08-23 1996-03-12 National Semiconductor Corporation Lead frame having layered conductive planes
US5742009A (en) * 1995-10-12 1998-04-21 Vlsi Technology Corporation Printed circuit board layout to minimize the clock delay caused by mismatch in length of metal lines and enhance the thermal performance of microeletronics packages via condution through the package leads
US5646831A (en) * 1995-12-28 1997-07-08 Vlsi Technology, Inc. Electrically enhanced power quad flat pack arrangement
US6066888A (en) * 1997-02-17 2000-05-23 Seiko Epson Corporation Tape carrier and tape carrier device using the same
US5994767A (en) * 1997-04-09 1999-11-30 Sitron Precision Co., Ltd. Leadframe for integrated circuit package and method of manufacturing the same
US5889317A (en) * 1997-04-09 1999-03-30 Sitron Precision Co., Ltd. Leadframe for integrated circuit package
US6528868B1 (en) * 1998-02-21 2003-03-04 Robert Bosch Gmbh Lead frame device and method for producing the same
US6242281B1 (en) * 1998-06-10 2001-06-05 Asat, Limited Saw-singulated leadless plastic chip carrier
US20010030355A1 (en) * 1998-06-10 2001-10-18 Mclellan Neil Saw-singulated leadless plastic chip carrier
US20020056856A1 (en) * 1998-06-10 2002-05-16 Mclellan Neil Saw singulated leadless plastic chip carrier
US20030102537A1 (en) * 1998-06-10 2003-06-05 Mclellan Neil Saw singulated leadless plastic chip carrier
US6812554B2 (en) * 1999-02-17 2004-11-02 Renesas Technology Corp. Semiconductor device and a method of manufacturing the same
US6258622B1 (en) * 1999-06-07 2001-07-10 Apack Technologies Inc. Flip clip bonding leadframe-type packaging method for integrated circuit device and a device formed by the packaging method
US20040135237A1 (en) * 2001-04-18 2004-07-15 Norihide Funato Semiconductor device and method of manufacturing the same
US6856007B2 (en) * 2001-08-28 2005-02-15 Tessera, Inc. High-frequency chip packages
US7176506B2 (en) * 2001-08-28 2007-02-13 Tessera, Inc. High frequency chip packages with connecting elements
US6921967B2 (en) * 2003-09-24 2005-07-26 Amkor Technology, Inc. Reinforced die pad support structure
US20080197464A1 (en) * 2005-02-23 2008-08-21 Nxp B.V. Integrated Circuit Device Package with an Additional Contact Pad, a Lead Frame and an Electronic Device
US7671474B2 (en) * 2005-02-23 2010-03-02 Nxp B.V. Integrated circuit package device with improved bond pad connections, a lead-frame and an electronic device
US20080265384A1 (en) * 2005-02-23 2008-10-30 Nxp B.V. Integrated Circuit Package Device With Improved Bond Pad Connections, a Lead-Frame and an Electronic Device
US7855100B2 (en) * 2005-03-31 2010-12-21 Stats Chippac Ltd. Integrated circuit package system with an encapsulant cavity and method of fabrication thereof
US7915084B2 (en) * 2005-05-04 2011-03-29 Stats Chippac Ltd. Method for making a stacked package semiconductor module having packages stacked in a cavity in the module substrate
US7763963B2 (en) * 2005-05-04 2010-07-27 Stats Chippac Ltd. Stacked package semiconductor module having packages stacked in a cavity in the module substrate
US7645634B2 (en) * 2005-06-20 2010-01-12 Stats Chippac Ltd. Method of fabricating module having stacked chip scale semiconductor packages
US7659610B2 (en) * 2005-09-27 2010-02-09 Kingston Technology Corporation Flash memory card
US7411293B2 (en) * 2005-09-27 2008-08-12 Kingston Technology Corporation Flash memory card
US7456088B2 (en) * 2006-01-04 2008-11-25 Stats Chippac Ltd. Integrated circuit package system including stacked die
US7652376B2 (en) * 2006-01-04 2010-01-26 Stats Chippac Ltd. Integrated circuit package system including stacked die
US7750482B2 (en) * 2006-02-09 2010-07-06 Stats Chippac Ltd. Integrated circuit package system including zero fillet resin
US7435619B2 (en) * 2006-02-14 2008-10-14 Stats Chippac Ltd. Method of fabricating a 3-D package stacking system
US7692295B2 (en) * 2006-03-31 2010-04-06 Intel Corporation Single package wireless communication device
US7795727B2 (en) * 2006-04-05 2010-09-14 Infineon Technologies Ag Semiconductor module having discrete components and method for producing the same
US7786575B2 (en) * 2006-09-15 2010-08-31 Stats Chippac Ltd. Stacked die semiconductor device having circuit tape
US20080128903A1 (en) * 2006-10-31 2008-06-05 Sanyo Electric Co., Ltd. Semiconductor module, method for manufacturing semiconductor modules and mobile device
US20100129962A1 (en) * 2007-02-16 2010-05-27 Richtek Technology Corp. Electronic package structure and method
US20100123255A1 (en) * 2007-02-16 2010-05-20 Richtek Technology Corp. Electronic package structure and method
US20080197507A1 (en) * 2007-02-16 2008-08-21 Yu-Lin Yang Electronic package structure and method
US7960213B2 (en) * 2007-02-16 2011-06-14 Richtek Technology Corp. Electronic package structure and method
US8097952B2 (en) * 2007-02-16 2012-01-17 Richtek Technology Corp. Electronic package structure having conductive strip and method
US7772696B2 (en) * 2007-08-30 2010-08-10 Nvidia Corporation IC package having IC-to-PCB interconnects on the top and bottom of the package substrate
US7936054B2 (en) * 2007-12-13 2011-05-03 Fairchild Korea Semiconductor Ltd. Multi-chip package
US7741567B2 (en) * 2008-05-19 2010-06-22 Texas Instruments Incorporated Integrated circuit package having integrated faraday shield
US20110115069A1 (en) * 2009-11-13 2011-05-19 Serene Seoh Hian Teh Electronic device including a packaging substrate and an electrical conductor within a via and a process of forming the same

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US20100129962A1 (en) 2010-05-27
US20080197507A1 (en) 2008-08-21
US8097952B2 (en) 2012-01-17
TW200836315A (en) 2008-09-01
US20100123255A1 (en) 2010-05-20
US7960213B2 (en) 2011-06-14

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