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Publication numberUS20100163829 A1
Publication typeApplication
Application numberUS 12/472,386
Publication dateJul 1, 2010
Filing dateMay 27, 2009
Priority dateDec 30, 2008
Also published asUS8124954
Publication number12472386, 472386, US 2010/0163829 A1, US 2010/163829 A1, US 20100163829 A1, US 20100163829A1, US 2010163829 A1, US 2010163829A1, US-A1-20100163829, US-A1-2010163829, US2010/0163829A1, US2010/163829A1, US20100163829 A1, US20100163829A1, US2010163829 A1, US2010163829A1
InventorsChing-Chiun Wang, Cha-Hsin Lin
Original AssigneeIndustrial Technology Research Institute
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Conductive bridging random access memory device and method of manufacturing the same
US 20100163829 A1
Abstract
A conductive bridging random access memory (CBRAM) device and a method of manufacturing the same are provided. The CBRAM device includes a first electrode layer, a dielectric layer, a solid electrolyte layer, a second electrode layer and a metal layer. The solid electrolyte layer is located on the first electrode layer. The second electrode layer is located on the solid electrolyte layer. The metal layer is located near the solid electrolyte layer. The dielectric layer is located between the solid electrolyte layer and the metal layer. Since the metal layer is disposed near the solid electrolyte layer in the CBRAM device, it can generate a positive electric field during an erase operation, so as to accelerate a break of mutually connected metal filaments.
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Claims(30)
1. A conductive bridging random access memory (CBRAM) device, comprising:
a first electrode layer;
a solid electrolyte layer, disposed on the first electrode layer;
a second electrode layer, disposed on the solid electrolyte layer;
a metal layer, disposed near the solid electrolyte layer; and
a dielectric layer, disposed between the solid electrolyte layer and the metal layer.
2. The CBRAM device as claimed in claim 1, wherein the dielectric layer has a groove.
3. The CBRAM device as claimed in claim 2, wherein the solid electrolyte layer is located in the groove.
4. The CBRAM device as claimed in claim 2, wherein the solid electrolyte layer covers an inter surface of the groove.
5. The CBRAM device as claimed in claim 1, wherein the metal layer and the first electrode layer are electrically connected.
6. The CBRAM device as claimed in claim 1, wherein the metal layer further comprises at least a tip facing to the solid electrolyte layer.
7. The CBRAM device as claimed in claim 1, wherein the metal layer is a single-side structure.
8. The CBRAM device as claimed in claim 1, wherein the metal layer is a double-side structure.
9. The CBRAM device as claimed in claim 1, wherein a material of the metal layer comprises a conductive metal composite material or a metal material.
10. The CBRAM device as claimed in claim 1, wherein a material of the first electrode layer comprises an inert metal.
11. The CBRAM device as claimed in claim 10, wherein the inert metal comprises Pt, W, TiN or Ni.
12. The CBRAM device as claimed in claim 1, wherein a material of the dielectric layer comprises SiO2, SiN or PMMA.
13. The CBRAM device as claimed in claim 1, wherein a material of the solid electrolyte layer comprises a chalcogenide or Ag2S, Cu2S, Ta2O5, W2O3 or SiO2.
14. The CBRAM device as claimed in claim 13, wherein the chalcogenide comprises Ge—Se or Ge—S.
15. The CBRAM device as claimed in claim 1, wherein a material of the second electrode layer comprises Ag or Cu.
16. A method for manufacturing a CBRAM device, comprising:
forming a dielectric layer on a first electrode layer;
performing a series of processes including exposure, development and etching to form at least a first groove in the dielectric layer;
filling a metal layer in the first groove;
performing the series of processes including exposure, development and etching to form a second groove in the dielectric layer near the first groove, wherein the second groove exposes a part of a surface of the first electrode layer;
depositing a solid electrolyte layer in the second groove; and
depositing a second electrode layer on the solid electrolyte layer.
17. The method for manufacturing a CBRAM device as claimed in claim 16, wherein forming the first groove comprises exposing the surface of the first electrode layer from the first groove.
18. The method for manufacturing a CBRAM device as claimed in claim 17, wherein depositing the solid electrolyte layer comprises conformally depositing the solid electrolyte layer on the dielectric layer, an inner wall of the second groove and the surface of the first electrode layer.
19. The method for manufacturing a CBRAM device as claimed in claim 16, wherein an etching process of the series of processes to form the first groove and the second groove comprises a dry etching or a wet etching.
20. The method for manufacturing a CBRAM device as claimed in claim 16, further comprising removing the solid electrolyte layer and the second electrode layer outside the second groove after depositing the second electrode layer.
21. The method for manufacturing a CBRAM device as claimed in claim 20, wherein a method for removing the solid electrolyte layer and the second electrode layer outside the second groove comprises a dry etching or a wet etching.
22. The method for manufacturing a CBRAM device as claimed in claim 16, wherein steps of filling the metal layer in the first groove comprise:
depositing the metal layer on the dielectric layer and the surface of the first electrode layer; and
removing the metal layer on a surface the dielectric layer by a chemical-mechanical polishing (CMP) method.
23. The method for manufacturing a CBRAM device as claimed in claim 16, wherein when the metal layer is a double-side structure, the step of forming the second groove comprises forming the second groove in the dielectric layer in the middle of the double-side structure.
24. The method for manufacturing a CBRAM device as claimed in claim 16, wherein a material of the metal layer is a conductive metal composite material or a metal material.
25. The method for manufacturing a CBRAM device as claimed in claim 16, wherein a material of the first electrode layer comprises an inert metal.
26. The method for manufacturing a CBRAM device as claimed in claim 25, wherein the inert metal comprises Pt, W, TiN or Ni.
27. The method for manufacturing a CBRAM device as claimed in claim 16, wherein a material of the dielectric layer comprises SiO2, SiN or PMMA.
28. The method for manufacturing a CBRAM device as claimed in claim 16, wherein a material of the solid electrolyte layer comprises a chalcogenide or Ag2S, Cu2S, Ta2O5, W2O3 or SiO2.
29. The method for manufacturing a CBRAM device as claimed in claim 28, wherein the chalcogenide comprises Ge—Se or Ge—S.
30. The method for manufacturing a CBRAM device as claimed in claim 16, wherein a material of the second electrode layer comprises Ag or Cu.
Description
    CROSS-REFERENCE TO RELATED APPLICATION
  • [0001]
    This application claims the priority benefit of Taiwan application serial no. 97151426, filed on Dec. 30, 2008. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of specification.
  • BACKGROUND OF THE INVENTION
  • [0002]
    1. Field of the Invention
  • [0003]
    The present invention relates to a conductive bridging random access memory (CBRAM) device and a method of manufacturing the same.
  • [0004]
    2. Description of Related Art
  • [0005]
    A CBRAM applies a non-volatile memory technique by which data accessing is performed according to a resistance variation. The CBRAM is belonged to a resistive random access memory (RRAM). A device structure of the CBRAM can be regarded as an electrolyzer composed of a metal anode (Ag or Cu), an inert cathode (Ni, W or Pt) and a solid electrolyte filled there between. A material of the solid electrolyte is glass-state chalcogenide or glass oxide. After a tiny voltage is applied between the anode and the cathode, an oxidation reaction is occurred at the anode, so that the metal on the surface of the anode releases electrons, and is dissolved into the electrolyte in an ion state. Due to an electrical migration, the metal ions are migrated towards the cathode. Finally, a reduction reaction is occurred on the surface of the cathode to precipitate conductive metal atoms and further form filaments, so as to decrease a whole resistance of the electrolyte to complete a write operation. Conversely, during an erase operation, the voltage is inversely applied to the electrodes, so that the filaments formed by the conductive metal atoms in the electrolyte are removed, and the resistance is gradually increased back to an initial state.
  • [0006]
    Regarding an oxide variable resistor having a bi-stable resistance switching, a low resistance path thereof (the filament) is a key to determine the resistance switching, and the metal filament is the low resistance path in the CBRAM. After an endurance test of the high-low resistance state conversion is performed to the device for tens of thousands of times, cycling times of the device and a switching time of the high-low resistance state conversion are probably reduced due to a quantity and distribution range of the filaments in the solid electrolyte.
  • SUMMARY OF THE INVENTION
  • [0007]
    The present invention provides a CBRAM device including a first electrode layer, a dielectric layer, a solid electrolyte layer, a second electrode layer and a metal layer. The solid electrolyte layer is located on the first electrode layer. The second electrode layer is located on the solid electrolyte layer. The metal layer is located near the solid electrolyte layer. The dielectric layer is located between the solid electrolyte layer and the metal layer.
  • [0008]
    The present invention provides a method for manufacturing a CBRAM device. The method includes following steps. First, a dielectric layer is formed on a first electrode layer, and then a series of processes including exposure, development and etching is performed to form at least a first groove in the dielectric layer. Next, a metal layer is filled in the first groove, and then another series of processes including exposure, development and etching is performed to form a second groove in the dielectric layer near the first groove, and the second groove exposes a part of a surface of the first electrode layer. Next, a solid electrolyte layer is deposited in the second groove, and finally a second electrode layer is deposited on the solid electrolyte layer.
  • [0009]
    In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures is described in detail below.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0010]
    The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
  • [0011]
    FIG. 1 is a cross-sectional view of a CBRAM device according to an embodiment of the present invention.
  • [0012]
    FIG. 2 is a cross-sectional view of another CBRAM device according to an embodiment of the present invention.
  • [0013]
    FIG. 3 is a top view of an embodiment of a metal layer of FIG. 2.
  • [0014]
    FIG. 4 is a top view of another embodiment of a metal layer of FIG. 2.
  • [0015]
    FIG. 5 is a partially amplified diagram of FIG. 1 or FIG. 2.
  • [0016]
    FIG. 6A to FIG. 6F are schematic diagrams illustrating a process flow of a CBRAM device according to another embodiment of the present invention.
  • DESCRIPTION OF EMBODIMENTS
  • [0017]
    FIG. 1 is a cross-sectional view of a CBRAM device according to an embodiment of the present invention.
  • [0018]
    Referring to FIG. 1, the CBRAM device 100 of the present embodiment includes a first electrode layer 102, a dielectric layer 110, a solid electrolyte layer 104, a second electrode layer 106 and a metal layer 108, wherein a material of the first electrode layer 102 is, for example, an inert metal such as platinum (Pt), tungsten (W), titanium nitride (TiN) or nickel (Ni). The solid electrolyte layer 104 is located on the first electrode layer 102, and a material of the solid electrolyte layer 104 includes chalcogenide such as germanium selenium compound (Ge—Se) or germanium sulphur compound (Ge—S), or Ag2S, Cu2S, Ta2O5, W2O3 or SiO2. The second electrode layer 106 is disposed on the solid electrolyte layer 104, and a material of the second electrode layer 106 includes Ag or Cu. The metal layer 108 can be a single-side structure located aside the sold electrolyte layer 104, and a material of the metal layer 108 can be a conductive metal composite material or a metal material. Moreover, in FIG. 1, the metal layer 108 and the first electrode layer 102 are electrically connected. The dielectric layer 110 is disposed between the solid electrolyte layer 104 and the metal layer 108, and a material of the dielectric layer 110 is, for example, SiO2, SiN or polymethyl methacrylate (PMMA).
  • [0019]
    In FIG. 1, the dielectric layer 110 may have a groove 112, and the solid electrolyte layer 104 is located in the groove 112.
  • [0020]
    During an erase operation of the CBRAM device 100 of FIG. 1, since a positive voltage is applied to the first electrode layer 102, the metal layer 108 connected to the first electrode layer 102 may generate a positive electric field which can repels metal ions dispersed in the solid electrolyte layer 104, so that mutually connected metal filaments therein are easy to be broken, and an efficiency for the device being switched from a low to a high resistance state is increased, by which an endurance of the device can be improved, and a switching time can be reduced. Moreover, the metal layer 108 can also be coupled to an external circuit, so as to generate the positive electric field during the erase operation of the CBRAM device 100.
  • [0021]
    FIG. 2 is a cross-sectional view of another CBRAM device according to an embodiment of the present invention, wherein elements in FIG. 2 that are the same or similar to the elements of FIG. 1 are represented by the same or similar reference numerals.
  • [0022]
    Referring to FIG. 2, a difference between the CBRAM device 200 and the CBRAM device 100 of FIG. 1 is that the metal layer 108 is a double-side structure, and the solid electrolyte layer 104 covers an inner surface of the groove 112 according to a contour of the groove 112. The second electrode layer 106 can be partially disposed in the groove 112 according to a shape of the solid electrolyte layer 104.
  • [0023]
    FIG. 3 and FIG. 4 are top views of two embodiments of the metal layer 108 of FIG. 2. A metal layer 108 a of FIG. 3 is a rectangular block-shape structure, and a metal layer 108 b of FIG. 4 is a slightly curved ear-shape structure.
  • [0024]
    Moreover, the shape of the metal layer 108 of FIG. 1 or FIG. 2 has different variations, as shown in FIG. 5. FIG. 5 is a partially amplified diagram of FIG. 1 or FIG. 2. The metal layer 108 of FIG. 5 further includes a tip 500 facing to the solid electrolyte layer 104, which is used for enhancing an effect of the electric field.
  • [0025]
    FIG. 6A to FIG. 6F are schematic diagrams illustrating a process flow of a CBRAM device according to another embodiment of the present invention.
  • [0026]
    Referring to FIG. 6A, a dielectric layer 602 is first formed on a first electrode layer 600. As described above, the material of the first electrode layer 600 is, for example, an inert metal such as Pt, W, TiN or Ni. The material of the dielectric layer 602 is, for example, SiO2, SiN or PMMA.
  • [0027]
    Next, referring to FIG. 6B, a series of processes including exposure, development and etching is performed to form a first groove 604 in the dielectric layer 602, and the groove 604 exposes a surface 606 of the first electrode layer 600. The etching process in the series of processes to form the first groove 604 is, for example, a dry etching or a wet etching. Moreover, in the present embodiment, two first grooves 604 are illustrated, though the present invention is not limited thereto, and a single or more than two grooves can also be formed.
  • [0028]
    Next, referring to FIG. 6C, a metal layer 608 used for generating the electric field is filled in the first groove 604, and steps of filling the first groove 604 can be described as follows. First, the metal layer 608 is deposited on the dielectric layer 602 and on the surface 606 of the first electrode layer 600. Next, the metal layer 608 on the surface of the dielectric layer 602 is removed by a chemical-mechanical polishing (CMP) method, for example. The material of the metal layer 608 can be a conductive metal composite material or a metal material.
  • [0029]
    Next, referring to FIG. 6D, another series of processes including exposure, development and etching are performed to form a second groove 610 in the dielectric layer 602 near the first groove 604, and the second groove 610 exposes the surface 606 of the first electrode layer 600. In the present embodiment, a size of the second groove 610 is greater than that of the first groove 604. Moreover, the metal layer 608 of the present embodiment has a double-side structure, so that the groove 610 can be formed in the middle of the double-side structure.
  • [0030]
    Moreover, a width “w” of the dielectric layer 602 between the second groove 610 and the first groove 604 is the smaller the better, so that the metal layer 608 in the first groove 604 may have a relatively obvious electric field effect. The method of forming the second groove 610 can be a dry etching or a wet etching.
  • [0031]
    Furthermore, referring to FIG. 6E, a solid electrolyte layer 612 is conformally deposited on the dielectric layer 602, the inner wall of the second groove 610 and the surface 606 of the first electrode layer 600, and a material thereof is, for example, chalcogenide such as Ge—Se or Ge—S, or Ag2S, Cu2S, Ta2O5, W2O3 or SiO2, etc. Next, a second electrode layer 614 is deposited on the solid electrolyte layer 612, and a material of the second electrode layer 614 includes Ag or Cu, etc.
  • [0032]
    Next, referring to FIG. 6F, the solid electrolyte layer 612 and the second electrode layer 614 outside the second groove 610 can be removed, though as long as the solid electrolyte layer 612 is not contacted to the metal layer 608, a part of the solid electrolyte layer 612 and the second electrode layer 614 can still be remained on the dielectric layer 602 outside the second groove 610. The method of removing the solid electrolyte layer 612 and the second electrode layer 614 is, for example, a dry etching or a wet etching.
  • [0033]
    In summary, the metal layer that can generate the external electric field is added to the original CBRAM device, so that when the positive voltage is applied to the first electrode layer during the erase operation, the metal layer connected to the first electrode layer can generate a positive electric field, which can repels the metal ions dispersed in the solid electrolyte layer, so as to accelerate a break of the mutually connected metal filaments. Therefore, an efficiency for the device being converted from a low to a high resistance state is increased, and accordingly an endurance of the device can be improved, and a switching time can be reduced.
  • [0034]
    It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
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Classifications
U.S. Classification257/3, 257/E47.005, 438/104, 257/E21.461, 257/E47.001, 29/25.03, 438/102, 438/478, 257/E21.068
International ClassificationH01L21/06, H01L47/00, H01L21/36
Cooperative ClassificationY10T29/417, H01L45/1273, H01L45/1233, H01L45/085, H01L45/143, H01L45/146, H01L45/142
European ClassificationH01L45/12D4B, H01L45/12D6, H01L45/08M
Legal Events
DateCodeEventDescription
Jun 8, 2009ASAssignment
Owner name: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE,TAIWAN
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Effective date: 20090520
Owner name: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WANG, CHING-CHIUN;LIN, CHA-HSIN;REEL/FRAME:022797/0184
Effective date: 20090520
Aug 28, 2015FPAYFee payment
Year of fee payment: 4