Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20100258921 A1
Publication typeApplication
Application numberUS 12/550,655
Publication dateOct 14, 2010
Filing dateAug 31, 2009
Priority dateApr 10, 2009
Also published asCN101859713A, CN101859713B, CN101859734A, CN101859734B, CN101859740A, CN101859740B, US8106492, US8124447, US20100258920, US20100258934
Publication number12550655, 550655, US 2010/0258921 A1, US 2010/258921 A1, US 20100258921 A1, US 20100258921A1, US 2010258921 A1, US 2010258921A1, US-A1-20100258921, US-A1-2010258921, US2010/0258921A1, US2010/258921A1, US20100258921 A1, US20100258921A1, US2010258921 A1, US2010258921A1
InventorsPao-Huei Chang Chien, Ping-Cheng Hu, Po-Shing Chiang, Wei-Lun Cheng
Original AssigneeAdvanced Semiconductor Engineering, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Advanced quad flat-leaded package structure and manufacturing method thereof
US 20100258921 A1
Abstract
The advanced quad flat non-leaded package structure includes a carrier, a chip, a plurality of wires, and a molding compound. The carrier includes a die pad and a plurality of leads. The inner leads of the leads electively have a plurality of locking grooves for enhancing the adhesion between the inner leads and the surrounding molding compound.
Images(13)
Previous page
Next page
Claims(19)
1. An advanced quad flat non-leaded package structure, comprising:
a carrier having a die pad, and a plurality of leads disposed around the die pad, wherein each of the plurality of the leads includes an inner lead and an outer lead and each inner lead includes at least one locking groove;
a chip, disposed on an upper surface of the carrier and located within the die pad;
a plurality of wires, disposed between the chip and the inner leads; and
a package body, encapsulating the chip on the die pad, the wires and the inner leads and filling the locking grooves.
2. The advanced quad flat non-leaded package structure as claimed in claim 1, wherein a cross-sectional shape of the inner lead is a circle and the at least one locking groove is disposed at at least one point of a circumference of the circle.
3. The advanced quad flat non-leaded package structure as claimed in claim 2, wherein each inner lead includes four locking grooves disposed at four points of a circumference of the circle.
4. The advanced quad flat non-leaded package structure as claimed in claim 1, wherein a cross-sectional shape of the inner lead is a polygon and the at least one locking groove is disposed at at least one side of the polygon.
5. The advanced quad flat non-leaded package structure as claimed in claim 4, wherein the cross-sectional shape of the inner lead is a tetragon and each inner lead includes four locking grooves disposed at four sides of the tetragon.
6. The advanced quad flat non-leaded package structure as claimed in claim 1, wherein the carrier further comprises at least a ground ring located on the die pad and electrically connected to the chip through the wire.
7. The advanced quad flat non-leaded package structure as claimed in claim 1, further comprising an adhesive layer disposed between the chip and the die pad.
8. The advanced quad flat non-leaded package structure of claim 1, further comprising:
a first metal coating disposed on surfaces of the inner leads; and
a second metal coating disposed on surfaces of the outer leads and on a lower surface of the die pad.
9. The advanced quad flat non-leaded package structure of claim 8, wherein the first metal coating on each inner lead has at least one recess corresponding to the at least one locking groove.
10. The advanced quad flat non-leaded package structure as claimed in claim 9, wherein a dimension of the recess ranges from about 10 microns to about 50 microns.
11. The advanced quad flat non-leaded package structure as claimed in claim 9, wherein, and a ratio of a dimension of the first metal coating on each inner lead to that of the recess ranges from about 20/1 to about 4/1.
12. The advanced quad flat non-leaded package structure as claimed in claim 8, wherein a material of the first or second metal coating comprises nickel, gold or palladium.
13. The advanced quad flat non-leaded package structure as claimed in claim 1, wherein a cross-sectional area of the locking groove at a top surface of the inner lead is larger than that of the locking groove at a lower portion of the inner lead.
14. A manufacturing method of an advanced quad flat non-leaded package structure, comprising:
providing a metal carrier having an upper surface and a lower surface, wherein the metal carrier has at least an accommodating cavity and a plurality of inner leads defined by a plurality of openings existing there-between, the inner leads are disposed around the accommodating cavity, and the inner leads have a plurality of locking grooves, and wherein the metal carrier further includes a first metal layer disposed on the upper surface of the metal carrier and a second metal layer disposed on the lower surface of the metal carrier;
providing a chip to the accommodating cavity of the metal carrier;
forming a plurality of wires between the chip and the inner leads;
forming a package body over the metal carrier to encapsulate the chip, the wires, the inner leads, and filling the accommodating cavity, the openings and the locking grooves of the inner leads; and
performing a first etching process using the second metal layer on the lower surface of the metal carrier as an etching mask to etch through the metal carrier until the package body filled inside the openings is exposed, so as to form a plurality of leads and a die pad.
15. The manufacturing method as claimed in claim 14, wherein the step of providing the metal carrier comprises:
forming a first patterned photoresist layer having a plurality of patterns on the upper surface of the metal carrier, wherein each of the plurality of the patterns has at least one indentation;
performing a second etching process to the upper surface of the metal carrier, using the first patterned photoresist layer as an etching mask, to form a plurality of inner lead portions and each of the plurality of the inner lead portions has at least one groove; and
removing the first patterned photoresist layer.
16. The manufacturing method as claimed in claim 15, further comprising forming the first metal layer directly on upper surfaces of the plurality of the inner lead portions of the metal carrier, and forming the second metal layer directly on the lower surface of the metal carrier, wherein the first metal layer formed on each of the plurality of the inner lead portions has at least one recess.
17. The manufacturing method as claimed in claim 14, wherein the first and second metal layers are formed by plating.
18. The manufacturing method as claimed in claim 14, wherein the step of providing the metal carrier comprises:
forming a first patterned photoresist layer on the upper surface of the metal carrier and a second patterned photoresist layer on the lower surface of the metal carrier;
forming the first metal layer directly on the upper surface of the metal carrier that is exposed by the first patterned photoresist layer, and forming the second metal layer directly on the lower surface of the metal carrier that is exposed by the second patterned photoresist layer, wherein the first metal layer includes a plurality of metal patterns, and each of the plurality of the metal patterns has at least one recess;
removing the first and second patterned photoresist layers; and
performing a third etching process to the upper surface of the metal carrier, using the first metal layer as an etching mask, to form the plurality of the inner leads and each of the plurality of the inner leads has at least one locking groove.
19. The manufacturing method as claimed in claim 14, further comprising forming an adhesive layer within the accommodating cavity before the chip is provided.
Description
    CROSS-REFERENCE TO RELATED APPLICATION
  • [0001]
    This application claims the priority benefit of U.S. Provisional Application Ser. No. 61/168,220, filed on Apr. 10, 2009. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
  • BACKGROUND OF THE INVENTION
  • [0002]
    1. Field of the Invention
  • [0003]
    The present invention generally relates to a package structure and a manufacturing method thereof. More particularly, the present invention relates to an advanced quad flat non-leaded (a-QFN) package structure and a manufacturing method thereof.
  • [0004]
    2. Description of Related Art
  • [0005]
    Quad flat package (QFP) family includes I-type (QFI), J-type (QFJ) and non-lead-type (QFN) packages, characterized by the shape of the leads of leadframes. Among them, the QFN package structures offer a variety of advantages, including reduced lead inductance, small-sized footprint, thinner profile and faster speeds for signal transmission. Thus, the QFN package has become one popular choice for the package structures and is suitable for the chip package with high-frequency (for example, radio frequency bandwidth) transmission.
  • [0006]
    For the QFN package structure, the die pad and surrounding contact terminals (lead pads) are fabricated from a planar lead-frame substrate. The QFN package structure generally is soldered to the printed circuit board (PCB) through the surface mounting technology (SMT). Accordingly, the contact terminals/pads of the QFN package structure need to be designed to fit well within the packaging process capabilities, as well as promote good long term joint reliability.
  • SUMMARY OF THE INVENTION
  • [0007]
    The present invention is directed to an advanced quad flat non-leaded package structure and a manufacturing method thereof, which can help lessen lead fall-off concerns and enhance the product reliability.
  • [0008]
    The present invention provides an advanced quad flat non-leaded package structure having a carrier, a chip disposed on the carrier, a plurality of wires and a molding compound. The carrier includes a die pad and a plurality of leads, and the leads include a plurality of inner leads and a plurality of outer leads exposed by the molding compound. The inner lead includes at least one locking groove, which is capable of increasing adhesion between the inner lead and the surrounding molding compound. The wires are disposed between the chip and the inner leads. The molding compound encapsulates the chip, the die pad, the wires, the inner leads and filling the locking groove.
  • [0009]
    According to embodiments of the present invention, the shape of the inner lead may be designed to promote the locking or wedging capability of the inner leads with the surrounding molding compound. The inner lead may further include the locking groove(s), as long as the locking groove can enhance the locking capability toward the molding compound as well. The inner lead or the locking groove can be designed to have cross-sectional views of any geometric shapes. Similarly, the number or the arrangement of the locking groove(s) can be adjusted depending on the product requirements.
  • [0010]
    The present invention further provides a manufacturing method of an advanced quad flat non-leaded package structure. A substrate having an upper surface and a lower surface is provided, and the substrate includes at least an accommodating cavity and a plurality of inner leads defined by a plurality of openings there-between. The inner leads are disposed around the accommodating cavity, and the inner leads have a plurality of locking grooves. The substrate further includes a first metal layer disposed on the patterned substrate and a second metal layer disposed on the lower surface of the substrate. Followed by providing a chip to the accommodating cavity of the substrate and forming a plurality of wires between the chip and the inner leads, a molding compound is formed over the substrate to encapsulate the chip, the wires, the inner leads, and filling the accommodating cavity, the openings and the locking grooves of the inner leads. Afterwards, an etching process using the second metal layer as an etching mask is performed to etch through the substrate, until the molding compound filled inside the openings is exposed, so as to form a plurality of leads and a die pad.
  • [0011]
    According to embodiments of the present invention, the inner leads can be fabricated by plating the first metal layer and then patterning the substrate using the first metal layer as the mask. Alternatively, the inner leads can be fabricated by patterning the substrate and then forming the first metal layer on the patterned substrate by plating.
  • [0012]
    In order to make the above and other features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0013]
    The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
  • [0014]
    FIGS. 1A through 1G are schematic cross-sectional views illustrating a manufacturing method of an advanced quad flat non-leaded (a-QFN) package structure according to an embodiment of the present invention.
  • [0015]
    FIGS. 1C′-1C′″ show schematic, enlarged views of one exemplary inner lead of the a-QFN package structure.
  • [0016]
    FIG. 1A′ show a schematic, enlarged top view regarding part of the photoresist pattern for the exemplary inner lead of FIG. 2D.
  • [0017]
    FIG. 1B′ show a schematic, enlarged top view regarding part of the resultant metal pattern following FIG. 1A′.
  • [0018]
    FIGS. 2A-2F are schematic top views illustrating designs of the inner leads and the locking grooves of the present invention.
  • [0019]
    FIG. 3A shows a schematic bottom view illustrating an advanced quad flat non-leaded (a-QFN) package structure according to an embodiment of the present invention.
  • [0020]
    FIG. 3B is a schematic cross-sectional view along a line I-I′ of the a-QFN package structure depicted in FIG. 3A.
  • [0021]
    FIGS. 4A through 4D are schematic views illustrating a manufacturing method of an advanced quad flat non-leaded package structure according to another embodiment of the present invention.
  • DESCRIPTION OF THE EMBODIMENTS
  • [0022]
    Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the descriptions to refer to the same or like parts.
  • [0023]
    FIGS. 1A through 1G are schematic cross-sectional views illustrating a manufacturing method of an advanced quad flat non-leaded package structure according to an embodiment of the present invention.
  • [0024]
    As shown in FIG. 1A, a substrate 110 having the upper surface 110 a and the lower surface 110 b is provided. The material of the substrate 110 can be, for example, copper, a copper alloy, or other applicable metal materials. Next, still referring to the FIG. 1A, a first patterned photoresist layer 114 a is formed on the upper surface 110 a of the substrate 110, and a second patterned photoresist layer 114 b is formed on the lower surface 110 b of the substrate 110. Basically, the patterns of the first patterned photoresist layer 114 a are mostly symmetric to those of the second patterned photoresist layer 114 b, except for the location(s) of the to-be-formed die pad(s).
  • [0025]
    Next, referring to the FIG. 1B, using the first/second photoresist layers 114 a/114 b as masks, a first/second metal layers 116 a/116 b is respectively formed on the exposed portions of the upper surface 110 a of the substrate 110 or the exposed portions of the lower surface 110 b of the substrate 110. In the present embodiment, the first metal layer 116 a and the second metal layer 116 b may be formed by, for example, plating. The material of the first metal layer 116 a and/or the second metal layer 116 b may comprise nickel, gold or palladium, for example. The first or second metal layer 116 a/116 b described herein may be composed of various groups of unconnected patterns or a continuous layer, depending on the pattern designs of the first or second patterned photoresist layer 114 a/114 b.
  • [0026]
    As shown in FIG. 1B, the first metal layer 116 a includes a plurality of first metal portions 115 a and at least a second metal portion 115 b. The first metal portions 115 a subsequently will be formed as inner leads 130, while the second metal portion 115 b will subsequently be formed as a ground ring 124 of the die pad 120 (as shown in FIG. 1D). Similarly, the second metal layer 116 b includes a plurality of third metal portions 117 a and at least a fourth metal portion 117 b. The third metal portions 117 a correspond to the subsequently to-be-formed inner leads 130, while the second metal portion 117 b corresponds to the subsequently to-be-formed die pad 120.
  • [0027]
    Next, referring to the FIG. 1C, after removing the first and second photoresist layers 214 a/214 b, an etching process is performed to the upper surface 110 a of the substrate 110 by using the first metal layer 116 a as an etching mask, so as to remove portions of the substrate 110 and form at least an accommodating cavity 120 a and a plurality of first openings S1. The etching process can be a wet etching process, for example. So far, the carrier 100 is roughly formed following the formation of the first metal layer 116 a, the second metal layer 116 b and patterning the substrate 110.
  • [0028]
    The accommodating cavities 120 a has a central portion 122 and a peripheral portion 124 disposed around the central portion 122. Defined by the openings S1, a plurality of individual inner leads 130, also separate from the peripheral portion 124, is formed. The inner leads 130 are disposed surrounding the peripheral portion 124. The inner leads 130 may be arranged in rows, columns or arrays. The peripheral portion 124 can function as the ground ring.
  • [0029]
    In details, due to the pattern designs of the first photoresist layer 114 a and/or the first metal layer 116 a, the resultant inner leads 130 may be designed to posses locking grooves 132. FIG. 1C′ shows an enlarged, top view of one exemplary inner lead of the a-QFN package structure, while FIG. 1C″ is a cross-sectional view of FIG. 1C′ along the line A-A′ and FIG. 1C′″ is a cross-sectional view of FIG. 1C′ along the line B-B′. Taking the square inner lead 130 of FIG. 1C′ as an example, the locking grooves 132 may be rectangle trenches at two opposite sides of the inner lead 130.
  • [0030]
    In principle, the locking grooves are optional, depending on the shapes of the inner leads. The inner lead 130 can be a 3-D block or post with a cross-sectional view of any geometric shapes, in order to promote the locking or wedging capability of the inner leads 130 with the surrounding molding compound. As long as the locking grooves 132 of the inner leads 130 can promote the locking or wedging capability of the inner leads 130 with the molding compound, the locking grooves 132 can be a gutter or concavity with a cross-sectional view of any geometric shapes. Similarly, the shape designs of the locking grooves 132 should match or balance with the shape designs of the inner leads 130.
  • [0031]
    For example, the exemplary designs of the inner leads 130 and the locking grooves 132 are shown in FIG. 2A-2F. The exemplary cross-sectional views of the locking grooves 132 can be arched (as shown in FIG. 2A), semicircular, elliptical, oval, circular, T-shaped (FIG. 2C), square (FIG. 2B), rectangular (FIG. 2D), polygonal (triangular, tetragonal, pentagonal, hexagonal . . . etc.) or a combination thereof, for example. The exemplary cross-sectional views of the inner leads 130 can be circular (as shown in FIGS. 2A-2C), arched, oval, elliptical, square (FIG. 2D), polygonal (e.g. hexagonal as shown in FIG. 2E) or a combination thereof (e.g. FIG. 2F), for example.
  • [0032]
    For example, considering the exemplary cross-sectional views of the inner leads being circular or hexagonal, the locking capability of the circular inner leads should be weaker than that of the hexagonal inner leads, and the circular inner leads may be further designed to have locking grooves to enhance the locking capability. However, either the existence or the arrangements of the locking grooves should be calculated together with the shapes of the inner leads as a whole for optimizing locking capability. In addition, the existence of the locking grooves will decrease the effective contact area(s) of the inner lead(s), which must be taken into consideration. In this case, it is necessary to balance the designs of the inner leads and the locking grooves.
  • [0033]
    In this embodiment, during the etching process of FIG. 1C, the inner lead 130 and the locking grooves 132 (if needed, depending on the design) are formed simultaneously. The etching rate, selectivity of the etching process can be finely tuned for optimal performances, so as to control the dimension or the profile of the grooves and optimize the shapes of the lead patterns. However, according to the other embodiment, the inner lead 130 and the locking grooves 132 may be formed sequentially by two etching process steps.
  • [0034]
    If considering the inner lead shown in FIG. 2D as an example, the photoresist pattern of the first photoresist layer 114 a is shown in FIG. 1A′ and the resultant metal pattern of the plated first metal layer 116 a is shown in FIG. 1B′. The plated first metal layer 116 a (on top of the inner lead 130) has two recesses 116 c corresponding to the underlying locking grooves 132. Taking FIG. 1B′ as an example, for the plated first metal layer 116 a, the dimension d of the recess may range from 10 microns to 50 microns, while the dimension D of the metal pattern (on top of the inner lead) may range from 150 microns to 250 microns. In addition, the pitch between inner leads may range from 150 microns to 250 microns, and the dimension ratio D/d ranges from about 20:1 to 4:1.
  • [0035]
    Next, referring to the FIG. 1D, at least a chip 150 is attached to the central portion 122 of each accommodating cavity 110 a with an adhesive layer 140 in-between.
  • [0036]
    Next, referring to the FIG. 1E, a plurality of wires 160 are provided between the chip 150, the ground ring 124 and the inner leads 130. In other words, the chip 150 is electrically connected to the ground ring 124 and the inner leads 130 through the wires 160.
  • [0037]
    Next, referring to the FIG. 1F, a molding compound 180 is formed to encapsulate the chip 150, the wires 160, the inner leads 130, the ground ring 124, and fill the accommodating cavities 120 a and the first openings S1. Although the molding compound is described herein, any suitable package body can be used.
  • [0038]
    Then, referring to the FIG. 1G, using the second metal layer 116 b as an etching mask, an etching process is performed toward the lower surface 110 b of the carrier 100 to remove a portion of the substrate 110, so that the carrier 100 is etched through to expose the molding compound 180 filled inside the first openings S1 and simultaneously form a plurality of second openings S2. Owning to the formation of the second openings S2, a plurality of outer leads 136 is defined and the inner leads 130 are electrically isolated from one another. That is, after the etching process, a plurality of leads or contact terminals 138, each consisting of one inner lead 130 and the corresponding outer lead 136, is formed. Besides, the etching process further defines at least a die pad 120 of the carrier 100. The die pad 120 is surrounded by the leads 138 and isolated from the leads 138 through the second openings S2. On the whole, the leads 138 are electrically isolated from one another through this etching process. Basically, although the patterns of the second metal layer 116 b correspond to or are mostly symmetric (except for the location of the to-be-formed die pad) to those of the first metal layer 116 a, the patterns of the second metal layer 116 b can be designed to match the cross-sectional shapes of the inner leads without the locking grooves. If considering the inner lead shown in FIG. 2D as an example, the shape of the corresponding outer lead can be simply square.
  • [0039]
    In detail, in the present embodiment, the first etching process (FIG. 1C) is performed toward the upper surface 110 a of the carrier 100 using the first patterned metal layer 116 a as an etching mask, so as to form the inner leads 130 and simultaneously form the locking grooves 132 (optional). Consequently, binding between the inner leads 130 (along with the locking grooves 132) and the surrounding molding compound 180 can be enhanced, so that the contact terminals 138 will not fall off during the surface mounting processing and the product reliability can be greatly improved. For the a-QFN package structure 10 in the present embodiment, the fall-off issues of the contact terminals 138 can be lessened and the mold locking capability can be of the contact terminals (or leads) can be enhanced.
  • [0040]
    FIG. 3A is a schematic bottom view illustrating an advanced quad flat non-leaded (a-QFN) package structure according to an embodiment of the present invention. FIG. 3B is a schematic cross-sectional view along a line I-I′ of the a-QFN package structure depicted in FIG. 3A, while one of the inner lead of the a-QFN package structure is shown in an enlarged 3-D view on the right. Referring to FIGS. 2A and 2B, in the present embodiment, an advanced quad flat non-leaded ( a-QFN ) package structure 20 includes a carrier 200, a chip 250, and a plurality of wires 260.
  • [0041]
    The carrier 200 in the present embodiment is, for example, a metal carrier or a leadframe. In detail, the carrier 200 includes a die pad 220 and a plurality of contact terminals (leads) 238. The leads 238 include a plurality of inner leads 230 and a plurality of outer leads 236. In FIG. 3A, only two or three columns/rows of the contact terminals 238 are schematically depicted. Specifically, the leads 238 are disposed around the die pad 220, and the material of the leads 238 may comprise nickel, gold or palladium, for example. The inner leads and the outer leads are defined by the molding compound; that is, the portions of the leads that are encapsulated by the molding compound are defined as the inner leads, while the outer leads are the exposed portions of the leads.
  • [0042]
    In more details, the contact terminal 238 in the present embodiment has a rectangular shape. As shown in the enlarged view at the right, the inner lead 230 has at least two rectangular locking grooves 232 at two opposite sides, for example. However, the locking grooves 232 can be arranged at four sides. In the present embodiment, the arrangement or the shape of the inner leads 230 and/or the locking grooves 232 are merely exemplificative. As a result of the etching profiles, the locking groove 232 gradually becomes shallower (from the top surface of the inner lead toward the lower portion of the inner lead). That is, the cross-sectional area of the locking groove 232 gradually decreases (from the top surface of the inner lead toward the lower portion of the inner lead). Due to the shape designs of the leads and the optional locking grooves, the binding between the leads and the molding compound is significantly increased.
  • [0043]
    In addition, the a-QFN package structure 20 in the present embodiment further includes a molding compound 280. The molding compound 280 encapsulates the chip 250, the wires 260, the inner leads 230 and fills the gaps between the inner leads 230, while the outer leads 236 and the bottom surface of the die pad 220 are exposed. A material of the molding compound 280 is, for example, epoxy resins or other applicable polymer material.
  • [0044]
    Further, in the present embodiment, to meet the electrical integration design requirement of the a-QFN package structure 20, the carrier 200 further includes at least a ground ring 224. The ground ring 224 is disposed between the leads 238 and the die pad 220 and electrically connected to the chip 250 through wires 260. As the ground ring 224 is connected to the die pad 220, the die pad together with the ground ring may function as the ground plane.
  • [0045]
    It should be noted that the position, the arrangement and the amount of the leads 238, relative to the ground ring 224 and the die pad 220 as shown in FIGS. 3A and 3B are merely exemplificative and should not be construed as limitations to the present invention.
  • [0046]
    FIGS. 4A through 4D are schematic views illustrating a manufacturing method of an advanced quad flat non-leaded (a-QFN) package structure according to another embodiment of the present invention. FIGS. 4A & 4D are shown in top views illustrating the lead portions, while FIGS. 4B-4C are shown in cross-sectional views.
  • [0047]
    As shown in FIG. 4A, a substrate 410 having the upper surface 410 a is provided. Next, a first patterned photoresist layer 414 a is formed on the upper surface 410 a of the substrate 410. The first patterned photoresist layer 414 a includes a plurality of hexagonal patterns 413 a and each hexagonal pattern 413 a includes two recesses 413 c at two opposite sides. For example, the dimension d of the recess may range from 10 microns to 50 microns, while the dimension D of the hexagonal pattern 413 a may range from 150 microns to 250 microns. The distance (i.e. the pitch) between the hexagonal patterns 413 a may range from 150 microns to 250 microns, and the dimension ratio D/d ranges from about 20:1 to 4:1.
  • [0048]
    Next, referring to the FIG. 4B, using the first photoresist layer 414 a as an etching mask, an etching process is performed to the upper surface 410 a of the substrate 410 to pattern the substrate 410, so that at least an accommodating cavity 420 a and a plurality of first openings S1 are formed. The etching process can be a wet etching process, for example. The accommodating cavity 420 a has a central portion 422 and a peripheral portion 424 around the central portion 422. Defined by the openings S1, a plurality of individual inner lead portions 430′ is formed. The inner lead portions 430+ are disposed surrounding the peripheral portion 424. The peripheral portion 424 can function as the ground ring.
  • [0049]
    In FIG. 4C, the remained first photoresist layer 414 a is removed and a second patterned photoresist layer 414 c is formed on the upper surface 410 a of the substrate 410 and a third patterned photoresist layer 414 b is formed on the lower surface 410 b of the substrate 410. The patterns of the first patterned photoresist layer 414 a are complementary to those of the second patterned photoresist layer 414 c. Later, using the second or third patterned photoresist layer 414 c/414 b as masks, the first metal layer 416 a and the second metal layer 416 b are respectively formed on the upper surface 410 a and lower surface 410 b by, for example, plating. The material of the first metal layer 416 a and/or the second metal layer 416 b may comprise nickel, gold or palladium, for example. As the patterns of the second patterned photoresist layer 414 c are complementary to those of the first patterned photoresist layer 414 a, the first metal layer 416 a is formed directly on the inner lead portions 430′, so as to form the inner leads 430. The first or second metal layer 416 a/416 b described herein may be composed of various groups of unconnected patterns or a continuous layer, depending on the pattern designs of the second or third patterned photoresist layer 414 c/414 b.
  • [0050]
    As shown in FIG. 4D, the first metal layer 416 a formed on the inner lead portions 430′ includes a plurality of hexagonal metal patterns 415 a with two recesses 415 c. The inner lead 430 has a hexagonal cross-sectional shape with two semi-circular locking grooves 432 disposed at two opposite sides of the hexagon. The locking groove 432 gradually becomes shallower (from the top surface of the inner lead toward the lower portion of the inner lead). That is, the dimension of the locking groove 432 at the lower portion of the inner lead is smaller than d or even approaching zero. However, the cross-sectional shape of the inner leads and/or the locking grooves can be any geometric shapes and should not be limited by the embodiments described herein. As the second and third patterned photoresist layers 414 c/414 b are removed, the first openings S1 are exposed. The following process steps are similar to the steps described in FIGS. 1D-1G and will not be described in details herein. In brief, followed by die-attaching, wire-bonding and forming the molding compound, an etching process is performed to the lower surface of the substrate using the second metal layer 416 b as the etching mask, so as to etch through the substrate 410 and isolate the inner leads 430.
  • [0051]
    For the a-QFN package structures according to the above embodiments, the patterns of the inner leads can be fabricated by plating the first metal layer and then patterning the substrate using the first metal layer as the mask, or by patterning the substrate and then plating the first metal layer thereon. For the previous approach, only one photomask is required, while the later approach requires two photomasks. However, as the first metal layer is formed after the etching process, the metal layer is less damaged.
  • [0052]
    The a-QFN package structures in the present embodiments are designed to have better locking capability (i.e. stronger adhesion between the inner leads and the molding compound) to solve the fall-off problems and improve the product reliability.
  • [0053]
    It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US5656550 *Mar 5, 1996Aug 12, 1997Fujitsu LimitedMethod of producing a semicondutor device having a lead portion with outer connecting terminal
US6551859 *Feb 22, 2001Apr 22, 2003National Semiconductor CorporationChip scale and land grid array semiconductor packages
US6812552 *Apr 29, 2002Nov 2, 2004Advanced Interconnect Technologies LimitedPartially patterned lead frames and methods of making and using the same in semiconductor packaging
US20050006737 *Aug 10, 2004Jan 13, 2005Shafidul IslamPartially patterned lead frames and methods of making and using the same in semiconductor packaging
US20080258278 *Oct 24, 2007Oct 23, 2008Mary Jean RamosPartially patterned lead frames and methods of making and using the same in semiconductor packaging
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US8106492Aug 31, 2009Jan 31, 2012Advanced Semiconductor Engineering, Inc.Semiconductor package and manufacturing method thereof
US8115285 *Aug 15, 2008Feb 14, 2012Advanced Semiconductor Engineering, Inc.Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof
US8120152Aug 15, 2008Feb 21, 2012Advanced Semiconductor Engineering, Inc.Advanced quad flat no lead chip package having marking and corner lead features and manufacturing methods thereof
US8124447Aug 26, 2009Feb 28, 2012Advanced Semiconductor Engineering, Inc.Manufacturing method of advanced quad flat non-leaded package
US8237250Apr 17, 2009Aug 7, 2012Advanced Semiconductor Engineering, Inc.Advanced quad flat non-leaded package structure and manufacturing method thereof
US8241965 *Aug 18, 2010Aug 14, 2012Stats Chippac Ltd.Integrated circuit packaging system with pad connection and method of manufacture thereof
US8309401 *Feb 18, 2011Nov 13, 2012Chipmos Technologies Inc.Method of manufacturing non-leaded package structure
US8338924 *Oct 6, 2011Dec 25, 2012Qpl LimitedSubstrate for integrated circuit package with selective exposure of bonding compound and method of making thereof
US8357998 *Jan 13, 2010Jan 22, 2013Advanced Semiconductor Engineering, Inc.Wirebonded semiconductor package
US8476746 *Aug 17, 2010Jul 2, 2013Kun Yuan Technology Co., Ltd.Package structure enhancing molding compound bondability
US8492883Aug 15, 2008Jul 23, 2013Advanced Semiconductor Engineering, Inc.Semiconductor package having a cavity structure
US8669654 *Aug 3, 2011Mar 11, 2014Stats Chippac Ltd.Integrated circuit packaging system with die paddle and method of manufacture thereof
US8749074 *Nov 30, 2009Jun 10, 2014Micron Technology, Inc.Package including an interposer having at least one topological feature
US8999763Jun 9, 2014Apr 7, 2015Micron Technology, Inc.Package including an interposer having at least one topological feature
US9209115 *Apr 24, 2014Dec 8, 2015Jiangsu Changjiang Electronics Technology Co., Ltd.Quad flat no-lead (QFN) packaging structure and method for manufacturing the same
US9209117 *May 28, 2014Dec 8, 2015Jiangsu Changjiang Electronics Technology Co., Ltd.No-exposed-pad quad flat no-lead (QFN) packaging structure and method for manufacturing the same
US9324584 *Dec 14, 2012Apr 26, 2016Stats Chippac Ltd.Integrated circuit packaging system with transferable trace lead frame
US9570381Apr 2, 2015Feb 14, 2017Advanced Semiconductor Engineering, Inc.Semiconductor packages and related manufacturing methods
US9627303 *Dec 2, 2013Apr 18, 2017Jiangsu Changjiang Electronics Technology Co., LtdEtching-before-packaging three-dimensional system-level metal circuit board structure inversely provided with chip, and technological method
US9633985 *Jan 8, 2014Apr 25, 2017Jiangsu Changjiang Electronics Technology Co., LtdFirst-etched and later-packaged three-dimensional system-in-package normal chip stack package structure and processing method thereof
US9640413 *Dec 2, 2013May 2, 2017Jiangsu Changjiang Electronics Technology Co., LtdEtching-before-packaging horizontal chip 3D system-level metal circuit board structure and technique thereof
US20090230526 *Aug 15, 2008Sep 17, 2009Chien-Wen ChenAdvanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof
US20100200969 *Jan 13, 2010Aug 12, 2010Advanced Semiconductor Engineering, Inc.Semiconductor package and method of manufacturing the same
US20110079886 *Aug 18, 2010Apr 7, 2011Henry Descalzo BathanIntegrated circuit packaging system with pad connection and method of manufacture thereof
US20110127659 *Nov 30, 2009Jun 2, 2011Steven EskildsenPackage including an interposer having at least one topological feature
US20110266662 *Aug 17, 2010Nov 3, 2011Kun Yuan Technology Co., Ltd.Leadframe enhancing molding compound bondability and package structure thereof
US20120032315 *Aug 3, 2011Feb 9, 2012Byung Tai DoIntegrated circuit packaging system with die paddle and method of manufacture thereof
US20120119342 *Nov 11, 2010May 17, 2012Mediatek Inc.Advanced quad flat non-leaded package structure and manufacturing method thereof
US20120146199 *Oct 6, 2011Jun 14, 2012Qpl LimitedSubstrate for integrated circuit package with selective exposure of bonding compound and method of making thereof
US20120153449 *Feb 18, 2011Jun 21, 2012Chipmos Technologies Inc.Non-leaded package structure and manufacturing method thereof
US20140264795 *May 28, 2014Sep 18, 2014Jiangsu Changjiang Electronics Technology Co., Ltd.No-exposed-pad quad flat no-lead (qfn) packaging structure and method for manufacturing the same
US20140319664 *Apr 24, 2014Oct 30, 2014Jiangsu Changjiang Electronics Technology Co., Ltd.Quad flat no-lead (qfn) packaging structure and method for manufacturing the same
US20160028001 *Oct 7, 2015Jan 28, 2016Allegro Microsystems, LlcPackaging for an electronic device
US20160351476 *Dec 16, 2015Dec 1, 2016Stmicroelectronics S.R.L.Process for manufacturing a surface-mount semiconductor device, and corresponding semiconductor device
US20160351482 *Dec 2, 2013Dec 1, 2016Jiangsu Changjiang Electronics Technology Co., LtdEtching-before-packaging three-dimensional system-level metal circuit board structure inversely provided with chip, and technological method
WO2013022477A2 *Aug 10, 2012Feb 14, 2013Eoplex LimitedLead carrier with multi-material print formed package components
WO2013022477A3 *Aug 10, 2012May 16, 2013Eoplex LimitedLead carrier with multi-material print formed package components
Legal Events
DateCodeEventDescription
Aug 31, 2009ASAssignment
Owner name: ADVANCED SEMICONDUCTOR ENGINEERING, INC., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHANG CHIEN, PAO-HUEI;HU, PING-CHENG;CHIANG, PO-SHING;AND OTHERS;REEL/FRAME:023162/0378
Effective date: 20090825