US20110049712A1 - Wafer Level Stacked Die Packaging - Google Patents

Wafer Level Stacked Die Packaging Download PDF

Info

Publication number
US20110049712A1
US20110049712A1 US12/896,186 US89618610A US2011049712A1 US 20110049712 A1 US20110049712 A1 US 20110049712A1 US 89618610 A US89618610 A US 89618610A US 2011049712 A1 US2011049712 A1 US 2011049712A1
Authority
US
United States
Prior art keywords
die
adhesive
stacked
package
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/896,186
Inventor
Thomas M. Goida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Analog Devices Inc
Original Assignee
Analog Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Analog Devices Inc filed Critical Analog Devices Inc
Priority to US12/896,186 priority Critical patent/US20110049712A1/en
Assigned to ANALOG DEVICES, INC. reassignment ANALOG DEVICES, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GOIDA, THOMAS M.
Publication of US20110049712A1 publication Critical patent/US20110049712A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92Specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/274Manufacturing methods by blanket deposition of the material of the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201Structure
    • H01L2224/32012Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83194Lateral distribution of the layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855Hardening the adhesive by curing, i.e. thermosetting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83856Pre-cured adhesive, i.e. B-stage adhesive
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/0651Wire or wire-like electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06575Auxiliary carrier between devices, the carrier having no electrical connection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01023Vanadium [V]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/162Disposition
    • H01L2924/16235Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Definitions

  • the present invention relates to stacked microelectronic devices and methods of manufacturing the same.
  • Stacked die packaging typically comes in any of three forms: pyramid configuration, inverted pyramid configuration and same size die configuration.
  • a pyramid configuration the top die is smaller than the bottom die. The opposite is true in the inverted pyramid configuration.
  • the dies can be the same size.
  • an adhesive is typically applied to attach the top and bottom die together.
  • spacers are made from several different types of materials that include silicon and polymer based pre-defined tapes. Electrical connections are provided by bonding electrodes on the dies to wires for connection to the base.
  • a stacked die package includes at least two microelectronic semiconductor dies, one affixed on top of the other.
  • An adhesive wall atop the bottom die outlines an air gap between a bottom and top die.
  • the adhesive wall is in the shape of a rectangle and forms a perimeter about a hollow area centrally disposed above the die.
  • the adhesive wall may be C-shaped, V-shaped, H-shaped or X-shaped to name a few configurations.
  • the top die is affixed on the adhesive wall to create the stacked dies.
  • the adhesive wall provides a thickness between the dies in a ratio of at least 1:1 with the width of the wall.
  • the stacked dies are mounted on a base. Wire bonds connect atop surface of each of the dies to the base.
  • the stacked die package can be encased within a non-conductive material molded over the first and second semiconductor dies.
  • the package may further include conductive balls attached to a bottom surface of the base for facilitating electrical connections.
  • a pattern of adhesive pads is deposited on the active surface of a semiconductor wafer.
  • the possible adhesive patterns are an array of rings of adhesive or an array of geometrically shaped solid blocks of adhesive.
  • the wafer is thereafter singulated to separate it into individual first semiconductor dies, each die having an adhesive pad thereon.
  • a rear surface of each first semiconductor die can be attached to a base.
  • Wire bonding may be performed between the first semiconductor die and its respective base.
  • a second semiconductor die is attached atop the adhesive pad onto the first semiconductor die to form a stacked die package. Wire bonding may be further performed to electrically attach the second semiconductor die to the base.
  • Overmolding the first and second semiconductor die stacks with non-conductive materials encases the individual packages.
  • the wafer may be backgrinded before the deposit of a pattern of adhesive.
  • the method may further include partially curing the adhesive before singulating the wafer.
  • FIGS. 1A and 1B are plan views of an intermediate semiconductor product in accordance with embodiments of the invention.
  • FIG. 2 is a schematic plan view of the product of FIG. 1A after singulation into individual dies.
  • FIG. 3 is a schematic side elevational view of a single die after attachment to a base.
  • FIG. 4 is a schematic side elevational view of the die of FIG. 3 after wire bonding.
  • FIG. 5 is a schematic side elevational view of the die of FIG. 4 after attachment of the top die.
  • FIG. 6 is a schematic elevational view of the stacked dies of FIG. 5 after wire bonding of the top die.
  • FIG. 7 is a schematic side elevational view of the stacked dies of FIG. 6 after overmolding.
  • FIG. 8 is a schematic side elevational view of the stacked dies of FIG. 7 after ball attachment.
  • FIG. 9 is a flowchart diagram of an embodiment of the invention of a method for making stacked dies.
  • a starting material may be a semiconductor wafer as is well known in the art.
  • the typical semiconductor wafer is made from silicon.
  • An array of microelectronic circuits is formed on the semiconductor wafer.
  • the array of circuits is formed in rows and columns of individual microelectronic circuits.
  • the semiconductor wafer includes an active surface onto which wire connections can be made and a rear surface for mounting. When thickness is an issue, a backgrinding process may be performed on the wafer bearing the circuits to make it and, thus, the resulting dies thinner.
  • adhesive pads 11 a , 11 b are deposited 100 onto the active surface of the semiconductor wafer wherein each adhesive pad 11 a , 11 b is aligned with one of the individual microelectronic circuits.
  • the adhesive pad 11 a , 11 b is an amount of adhesive having a thickness such that it will advantageously act as a spacer between a bottom die and top die of a package.
  • the adhesive pads may be applied to the wafer in any of a number of methods. Such methods include screen printing or photolithography.
  • the adhesive material may be selected from any of a number of adhesives suitable for use in making microelectronic components. Such adhesives may include, for example, polyimide or BCB (benzocyclobutene).
  • the thickness of the adhesive to be used as a spacer depends upon the geometrical features of the silicon die for a given packaging application. For a stacked die in which the smaller die is placed on top, a smaller thickness spacer is acceptable, for example, in the range of 5 to 20 microns. In an embodiment in which a larger die is placed on top of the smaller die to form a stacked package the thickness of the adhesive may be, for example, between 50 and 75 microns. Such a thick adhesive pad may be more suitable for application through a screen printing method.
  • the method and products of the present invention may be used with any thickness adhesive pad that can be used to produce a useable device.
  • the adhesive pads 11 a are rings of adhesive.
  • the adhesive forms a wall that leaves a hollow area 13 centrally disposed above each die as shown in FIG. 1A .
  • This hollowed out central portion 13 leaves an air gap that will thus not stress the bottom die in a manner normally associated with the adhesive.
  • Spacers based on organic material can induce thermomechanical shear stress on the top side of the bottom silicon die in a stacked die package. The magnitude of this shear stress will depend on the material properties, geometry of the spacer and interface adhesion area. This shear stress has potential to cause delamination and/or cracking in die passivation and/or inner layer structures inside the silicon die.
  • the adhesive rings reduce the adhesion area and are thus designed to reduce these shear stresses.
  • the adhesive acts as a wall that forms the perimeter about the hollow central portion.
  • the ring of adhesive is in the shape of a rectangle. It is contemplated that in specific embodiments, a minimal aspect ratio for thickness (height) of the wall to width of the wall should be 1 to 1.
  • the actual aspect ratio of the adhesive wall will depend upon the geometrical features of the bottom die and type of application.
  • Such walls may be used to create pads in shapes other than a ring that still create an air gap and derive similar advantages of reduced stress. Such shapes are innumerable including C-shaped, H-shaped, V shaped or X-shaped among others.
  • the adhesive pads 11 b are geometrically shaped as solid blocks of adhesive.
  • the shape shown in FIG. 1B is that of a rectangular block of adhesive. Certainly, an oval or other shapes may be used as well.
  • each adhesive pad is oriented over a microelectronic circuit but within boundaries set by bond pads 15 for use along the periphery of a die.
  • the bond pads 15 for the microelectronic circuit are exposed and accessible outside the periphery of the adhesive pad.
  • the method of manufacture continues with the step of partially curing 102 the adhesive to bring it to its B-stage.
  • B-stage is an intermediate stage in a thermosetting resin reaction in which the plastic remains in a soft state.
  • the intermediate semiconductor product is then ready for singulation.
  • the singulation process 104 typically involves sawing the wafer into individual dies 20 as shown in FIG. 2 .
  • Each die 20 includes a microelectronic circuit and the adhesive pad 11 a , 11 b that had been deposited thereon.
  • the individual dies may then be picked and placed onto a base 30 .
  • a suitable pickup nozzle is used to accommodate the circuit with adhesive pad thereon.
  • a snap cure or low temperature curing adhesive 32 on the base 30 attaches 106 the bottom of the die 20 to the base.
  • the base 30 may be a substrate or lead frame or other suitable base for supporting a stacked die package.
  • the snap cure or low temperature curing adhesive 32 may then be cured without fully curing the adhesive pad 11 a , 11 b on the die 20 .
  • the curing may take place at a lower temperature than will cure the adhesive pad or the curing can take place in a short time span such that the adhesive pad does not cure.
  • Standard die attach materials such as ABLESTIK 84-1 are cured at temperatures well below full cure for adhesives such as polyimide or BCB.
  • a die attach material might be cured at temperatures between 125° C. and 150° C. for approximately one hour.
  • the BCB or polyimide used for the adhesive pad may, on the other hand, cure at over 300° C. for more than 30 minutes to an hour.
  • the adhesive attaching the die to the base is cured without curing the adhesive pad 108 .
  • the adhesive pad may remain in its B-stage during this low temperature or quick curing.
  • wire bonding 110 can be performed to connect bond pads on the bottom die to the base, as shown in FIG. 4 .
  • a top die 50 is then ready for attachment 112 above the bottom die 20 .
  • the top die 50 is placed on the adhesive pad 11 a , 11 b as shown in FIG. 5 .
  • Full curing 114 of the B-stage adhesive pad is then performed to securely attach the bottom and top dies of the stacked die package.
  • Wire bonding 116 may then be completed from the top die 50 to the base 30 as shown in FIG. 6 .
  • Overmolding 118 encases the stacked die package in a nonconductive material as shown in FIG. 7 . Overmolding may be performed, for example, using a standard transfer molding process. Depending on the type of package and base that has been used, at this point ball attachment to the bottom of the base may be performed in order to provide conductive points for accessing the microelectronics as shown in FIG. 8 .
  • an air gap 80 remains disposed between the bottom die and the top die when a wall of adhesive was used to form the adhesive pad.
  • the air gap 80 is centrally disposed. This relieves that central area of stress associated with an adhesive connection.
  • a stacked die package in accordance with the invention can be made with a smaller or larger top die with respect to the bottom die.
  • the base of the package may be a semiconductor substrate or a lead frame depending upon the desired package.
  • additional layers of dies may be included so that multiple dies are stacked using the described methods.

Abstract

A stacked die package in which an adhesive pad separates a bottom die from a top die. The pad may be in the form of a wall of adhesive about a central hollow area. The bottom die is attached to a base with a low temperature curing adhesive or a snap cure adhesive.

Description

  • The present application is a divisional application of U.S. patent application Ser. No. 11/874,083, filed Oct. 17, 2007, now issued as U.S. Pat. No. ______, the full disclosure of which is hereby incorporated by reference herein.
  • BACKGROUND OF THE INVENTION
  • The present invention relates to stacked microelectronic devices and methods of manufacturing the same.
  • Stacked die packaging typically comes in any of three forms: pyramid configuration, inverted pyramid configuration and same size die configuration. In a pyramid configuration the top die is smaller than the bottom die. The opposite is true in the inverted pyramid configuration. Alternatively, the dies can be the same size. In all stacked die configurations, an adhesive is typically applied to attach the top and bottom die together. In the case of the inverted pyramid with a larger die on top, the inclusion of a spacer is often required which introduces two separate and additional die attach steps in package assembly processes. Spacers are made from several different types of materials that include silicon and polymer based pre-defined tapes. Electrical connections are provided by bonding electrodes on the dies to wires for connection to the base.
  • SUMMARY OF THE INVENTION
  • In accordance with embodiments of the invention, a stacked die package includes at least two microelectronic semiconductor dies, one affixed on top of the other. An adhesive wall atop the bottom die outlines an air gap between a bottom and top die. In one embodiment, the adhesive wall is in the shape of a rectangle and forms a perimeter about a hollow area centrally disposed above the die. In other embodiments, the adhesive wall may be C-shaped, V-shaped, H-shaped or X-shaped to name a few configurations. The top die is affixed on the adhesive wall to create the stacked dies. In a specific embodiment, the adhesive wall provides a thickness between the dies in a ratio of at least 1:1 with the width of the wall. The stacked dies are mounted on a base. Wire bonds connect atop surface of each of the dies to the base. The stacked die package can be encased within a non-conductive material molded over the first and second semiconductor dies. The package may further include conductive balls attached to a bottom surface of the base for facilitating electrical connections.
  • In accordance with a method of manufacturing, a pattern of adhesive pads is deposited on the active surface of a semiconductor wafer. Among the possible adhesive patterns are an array of rings of adhesive or an array of geometrically shaped solid blocks of adhesive. The wafer is thereafter singulated to separate it into individual first semiconductor dies, each die having an adhesive pad thereon. A rear surface of each first semiconductor die can be attached to a base. Wire bonding may be performed between the first semiconductor die and its respective base. A second semiconductor die is attached atop the adhesive pad onto the first semiconductor die to form a stacked die package. Wire bonding may be further performed to electrically attach the second semiconductor die to the base. Overmolding the first and second semiconductor die stacks with non-conductive materials encases the individual packages. In a preferred embodiment, the wafer may be backgrinded before the deposit of a pattern of adhesive. The method may further include partially curing the adhesive before singulating the wafer.
  • Stress on the die surface of the underlying die typically imparted by the adhesive layer is reduced by using only an adhesive wall leaving an adhesive free air gap region. Application of the adhesive to the active surface of the semiconductor wafer provides for an efficient manufacturing process. Other objects and advantages of the invention will become apparent during the following description of the presently preferred embodiments of the invention taken in conjunction with the drawings.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The foregoing features of the invention will be more readily understood by reference to the following detailed description, taken with reference to the accompanying drawings, in which:
  • FIGS. 1A and 1B are plan views of an intermediate semiconductor product in accordance with embodiments of the invention.
  • FIG. 2 is a schematic plan view of the product of FIG. 1A after singulation into individual dies.
  • FIG. 3 is a schematic side elevational view of a single die after attachment to a base.
  • FIG. 4 is a schematic side elevational view of the die of FIG. 3 after wire bonding.
  • FIG. 5 is a schematic side elevational view of the die of FIG. 4 after attachment of the top die.
  • FIG. 6 is a schematic elevational view of the stacked dies of FIG. 5 after wire bonding of the top die.
  • FIG. 7 is a schematic side elevational view of the stacked dies of FIG. 6 after overmolding.
  • FIG. 8 is a schematic side elevational view of the stacked dies of FIG. 7 after ball attachment.
  • FIG. 9 is a flowchart diagram of an embodiment of the invention of a method for making stacked dies.
  • DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS
  • In order to make a stacked die package in a mass production method, a starting material may be a semiconductor wafer as is well known in the art. The typical semiconductor wafer is made from silicon. An array of microelectronic circuits is formed on the semiconductor wafer. Typically, the array of circuits is formed in rows and columns of individual microelectronic circuits. The semiconductor wafer includes an active surface onto which wire connections can be made and a rear surface for mounting. When thickness is an issue, a backgrinding process may be performed on the wafer bearing the circuits to make it and, thus, the resulting dies thinner.
  • In accordance with an aspect of the present invention as seen in FIG. 9, adhesive pads 11 a, 11 b are deposited 100 onto the active surface of the semiconductor wafer wherein each adhesive pad 11 a, 11 b is aligned with one of the individual microelectronic circuits. The adhesive pad 11 a, 11 b is an amount of adhesive having a thickness such that it will advantageously act as a spacer between a bottom die and top die of a package.
  • The adhesive pads may be applied to the wafer in any of a number of methods. Such methods include screen printing or photolithography. The adhesive material may be selected from any of a number of adhesives suitable for use in making microelectronic components. Such adhesives may include, for example, polyimide or BCB (benzocyclobutene). The thickness of the adhesive to be used as a spacer depends upon the geometrical features of the silicon die for a given packaging application. For a stacked die in which the smaller die is placed on top, a smaller thickness spacer is acceptable, for example, in the range of 5 to 20 microns. In an embodiment in which a larger die is placed on top of the smaller die to form a stacked package the thickness of the adhesive may be, for example, between 50 and 75 microns. Such a thick adhesive pad may be more suitable for application through a screen printing method. The method and products of the present invention may be used with any thickness adhesive pad that can be used to produce a useable device.
  • In accordance with one embodiment as shown in FIG. 1A, the adhesive pads 11 a, are rings of adhesive. The adhesive forms a wall that leaves a hollow area 13 centrally disposed above each die as shown in FIG. 1A. This hollowed out central portion 13 leaves an air gap that will thus not stress the bottom die in a manner normally associated with the adhesive. Spacers based on organic material can induce thermomechanical shear stress on the top side of the bottom silicon die in a stacked die package. The magnitude of this shear stress will depend on the material properties, geometry of the spacer and interface adhesion area. This shear stress has potential to cause delamination and/or cracking in die passivation and/or inner layer structures inside the silicon die. The adhesive rings reduce the adhesion area and are thus designed to reduce these shear stresses. The adhesive acts as a wall that forms the perimeter about the hollow central portion. In the embodiment of FIG. 1A, the ring of adhesive is in the shape of a rectangle. It is contemplated that in specific embodiments, a minimal aspect ratio for thickness (height) of the wall to width of the wall should be 1 to 1. The actual aspect ratio of the adhesive wall will depend upon the geometrical features of the bottom die and type of application. Such walls may be used to create pads in shapes other than a ring that still create an air gap and derive similar advantages of reduced stress. Such shapes are innumerable including C-shaped, H-shaped, V shaped or X-shaped among others.
  • In accordance with an alternative embodiment such as that shown in FIG. 1B, the adhesive pads 11 b are geometrically shaped as solid blocks of adhesive. The shape shown in FIG. 1B is that of a rectangular block of adhesive. Certainly, an oval or other shapes may be used as well.
  • In accordance with a preferred embodiment, each adhesive pad is oriented over a microelectronic circuit but within boundaries set by bond pads 15 for use along the periphery of a die. Thus, the bond pads 15 for the microelectronic circuit are exposed and accessible outside the periphery of the adhesive pad. Once the adhesive pads have been deposited, an intermediate semiconductor product has been completed for further use in the manufacturing of stacked die packaging.
  • The method of manufacture continues with the step of partially curing 102 the adhesive to bring it to its B-stage. B-stage is an intermediate stage in a thermosetting resin reaction in which the plastic remains in a soft state. The intermediate semiconductor product is then ready for singulation. The singulation process 104 typically involves sawing the wafer into individual dies 20 as shown in FIG. 2. Each die 20 includes a microelectronic circuit and the adhesive pad 11 a, 11 b that had been deposited thereon.
  • The individual dies may then be picked and placed onto a base 30. A suitable pickup nozzle is used to accommodate the circuit with adhesive pad thereon. A snap cure or low temperature curing adhesive 32 on the base 30 attaches 106 the bottom of the die 20 to the base. The base 30 may be a substrate or lead frame or other suitable base for supporting a stacked die package. The snap cure or low temperature curing adhesive 32 may then be cured without fully curing the adhesive pad 11 a, 11 b on the die 20. The curing may take place at a lower temperature than will cure the adhesive pad or the curing can take place in a short time span such that the adhesive pad does not cure. Standard die attach materials, such as ABLESTIK 84-1, are cured at temperatures well below full cure for adhesives such as polyimide or BCB. For example, a die attach material might be cured at temperatures between 125° C. and 150° C. for approximately one hour. The BCB or polyimide used for the adhesive pad may, on the other hand, cure at over 300° C. for more than 30 minutes to an hour.
  • After attaching the bottom die to the base, the adhesive attaching the die to the base is cured without curing the adhesive pad 108. Thus, the adhesive pad may remain in its B-stage during this low temperature or quick curing. At this point, wire bonding 110 can be performed to connect bond pads on the bottom die to the base, as shown in FIG. 4.
  • A top die 50 is then ready for attachment 112 above the bottom die 20. The top die 50 is placed on the adhesive pad 11 a, 11 b as shown in FIG. 5. Full curing 114 of the B-stage adhesive pad is then performed to securely attach the bottom and top dies of the stacked die package. Wire bonding 116 may then be completed from the top die 50 to the base 30 as shown in FIG. 6. Overmolding 118 encases the stacked die package in a nonconductive material as shown in FIG. 7. Overmolding may be performed, for example, using a standard transfer molding process. Depending on the type of package and base that has been used, at this point ball attachment to the bottom of the base may be performed in order to provide conductive points for accessing the microelectronics as shown in FIG. 8.
  • In accordance with embodiments of the invention, an air gap 80 remains disposed between the bottom die and the top die when a wall of adhesive was used to form the adhesive pad. In particular, when a ring of adhesive 11 a is formed the air gap 80 is centrally disposed. This relieves that central area of stress associated with an adhesive connection.
  • Of course, it should be understood that various changes and modifications to the preferred embodiments described above will be apparent to those skilled in the art. For example, a stacked die package in accordance with the invention can be made with a smaller or larger top die with respect to the bottom die. Moreover, the base of the package may be a semiconductor substrate or a lead frame depending upon the desired package. Furthermore, additional layers of dies may be included so that multiple dies are stacked using the described methods. These and other changes can be made without departing from the spirit and scope of the invention and without diminishing its attendant advantages. It is therefore intended that such changes and modifications be covered by the following claims.

Claims (17)

1. A stacked die package comprising:
a first microelectronic semiconductor die;
an adhesive pad atop the die;
a second microelectronic semiconductor die affixed atop the adhesive pad; and
a base on which the first microelectronic semiconductor die is attached by an adhesive that cures at a lower temperature than the adhesive in the adhesive pad.
2. The stacked die package of claim 1, further comprising wire bonds connected between a top surface of the first microelectronic semiconductor die and the base.
3. The stacked die package of claim 2, further comprising wire bonds connected between a top surface of the second microelectronic semiconductor die and the base.
4. The stacked die package of claim 3, further comprising nonconductive material molded over the first and second semiconductor dies.
5. The stacked die package of claim 4, further comprising conductive balls attached to a bottom surface of the base.
6. The stacked die package of claim 1, wherein the adhesive pad forms a perimeter about a hollow area centrally disposed above the die.
7. The stacked die package of claim 6, wherein the adhesive pad is in the shape of a rectangular wall.
8. The stacked die package of claim 6, wherein the adhesive pad has a width on the die and a thickness from the die to a top of the pad, wherein a ratio of the thickness to the width is at least 1:1 and the second microelectronic semiconductor die is separated from the first microelectronic semiconductor die by the wall thickness.
9. The stacked die package of claim 1, wherein the adhesive attaching the first microelectronic semiconductor die to the base comprises a low temperature curing adhesive, which cures at temperatures between 125° C. and 150° C.
10. A stacked die package comprising:
a first microelectronic semiconductor die;
an adhesive pad atop the die;
a second microelectronic semiconductor die affixed atop the adhesive pad; and
a base on which the first microelectronic semiconductor die is attached by a snap cure adhesive, which cures more quickly than the adhesive in the adhesive pad.
11. The stacked die package of claim 10, further comprising wire bonds connected between a top surface of the first microelectronic semiconductor die and the base.
12. The stacked die package of claim 11, further comprising wire bonds connected between a top surface of the second microelectronic semiconductor die and the base.
13. The stacked die package of claim 12, further comprising nonconductive material molded over the first and second semiconductor dies.
14. The stacked die package of claim 13, further comprising conductive balls attached to a bottom surface of the base.
15. The stacked die package of claim 10, wherein the adhesive pad forms a perimeter about a hollow area centrally disposed above the die.
16. The stacked die package of claim 15, wherein the adhesive pad is in the shape of a rectangular wall.
17. The stacked die package of claim 15, wherein the adhesive pad has a width on the die and a thickness from the die to a top of the wall, wherein a ratio of the thickness to the width is at least 1:1 and the second microelectronic semiconductor die is separated from the first microelectronic semiconductor die by the wall thickness.
US12/896,186 2007-10-17 2010-10-01 Wafer Level Stacked Die Packaging Abandoned US20110049712A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/896,186 US20110049712A1 (en) 2007-10-17 2010-10-01 Wafer Level Stacked Die Packaging

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/874,083 US7829379B2 (en) 2007-10-17 2007-10-17 Wafer level stacked die packaging
US12/896,186 US20110049712A1 (en) 2007-10-17 2010-10-01 Wafer Level Stacked Die Packaging

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US11/874,083 Division US7829379B2 (en) 2007-10-17 2007-10-17 Wafer level stacked die packaging

Publications (1)

Publication Number Publication Date
US20110049712A1 true US20110049712A1 (en) 2011-03-03

Family

ID=40562660

Family Applications (2)

Application Number Title Priority Date Filing Date
US11/874,083 Active 2029-02-19 US7829379B2 (en) 2007-10-17 2007-10-17 Wafer level stacked die packaging
US12/896,186 Abandoned US20110049712A1 (en) 2007-10-17 2010-10-01 Wafer Level Stacked Die Packaging

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US11/874,083 Active 2029-02-19 US7829379B2 (en) 2007-10-17 2007-10-17 Wafer level stacked die packaging

Country Status (3)

Country Link
US (2) US7829379B2 (en)
TW (1) TWI400779B (en)
WO (1) WO2009051975A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100164124A1 (en) * 2006-12-19 2010-07-01 Yong Du Method and apparatus for multi-chip packaging

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9215519B2 (en) 2010-07-30 2015-12-15 Invensense, Inc. Reduced footprint microphone system with spacer member having through-hole
US8841738B2 (en) 2012-10-01 2014-09-23 Invensense, Inc. MEMS microphone system for harsh environments
US9263377B2 (en) * 2012-11-08 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. POP structures with dams encircling air gaps and methods for forming the same
US10032662B2 (en) * 2014-10-08 2018-07-24 Taiwan Semiconductor Manufacturing Company Packaged semiconductor devices and packaging methods thereof
KR102555721B1 (en) 2018-08-20 2023-07-17 삼성전자주식회사 method for bonding flip chip
US11482979B2 (en) 2018-12-03 2022-10-25 X Display Company Technology Limited Printing components over substrate post edges
US11528808B2 (en) * 2018-12-03 2022-12-13 X Display Company Technology Limited Printing components to substrate posts
US11217499B2 (en) * 2019-06-21 2022-01-04 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same

Citations (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3851221A (en) * 1972-11-30 1974-11-26 P Beaulieu Integrated circuit package
US4103318A (en) * 1977-05-06 1978-07-25 Ford Motor Company Electronic multichip module
US4361261A (en) * 1978-11-22 1982-11-30 Kulicke & Soffa Industries, Inc. Apparatus for wire bonding
US4444349A (en) * 1981-05-04 1984-04-24 Kulicke & Soffa Industries, Inc. Wire bonding apparatus
US4567643A (en) * 1983-10-24 1986-02-04 Sintra-Alcatel Method of replacing an electronic component connected to conducting tracks on a support substrate
US4586642A (en) * 1985-05-13 1986-05-06 Kulicke And Soffa Industries Inc. Wire bond monitoring system
US4730232A (en) * 1986-06-25 1988-03-08 Westinghouse Electric Corp. High density microelectronic packaging module for high speed chips
US4763188A (en) * 1986-08-08 1988-08-09 Thomas Johnson Packaging system for multiple semiconductor devices
US4982265A (en) * 1987-06-24 1991-01-01 Hitachi, Ltd. Semiconductor integrated circuit device and method of manufacturing the same
US5025306A (en) * 1988-08-09 1991-06-18 Texas Instruments Incorporated Assembly of semiconductor chips
US5026667A (en) * 1987-12-29 1991-06-25 Analog Devices, Incorporated Producing integrated circuit chips with reduced stress effects
US5040052A (en) * 1987-12-28 1991-08-13 Texas Instruments Incorporated Compact silicon module for high density integrated circuits
US5140404A (en) * 1990-10-24 1992-08-18 Micron Technology, Inc. Semiconductor device manufactured by a method for attaching a semiconductor die to a leadframe using a thermoplastic covered carrier tape
US5172215A (en) * 1990-03-06 1992-12-15 Fuji Electric Co., Ltd. Overcurrent-limiting type semiconductor device
US5176311A (en) * 1991-03-04 1993-01-05 Kulicke And Soffa Investments, Inc. High yield clampless wire bonding method
US5177032A (en) * 1990-10-24 1993-01-05 Micron Technology, Inc. Method for attaching a semiconductor die to a leadframe using a thermoplastic covered carrier tape
US20020037631A1 (en) * 2000-09-22 2002-03-28 Kabushiki Kaisha Shinkawa Method for manufacturing semiconductor devices
US20020090753A1 (en) * 2001-01-05 2002-07-11 Advanced Semiconductor Engineering Inc. Method for fabricating stacked chip package
US20020140073A1 (en) * 2001-03-28 2002-10-03 Advanced Semiconductor Engineering, Inc. Multichip module
US20020163015A1 (en) * 2001-02-27 2002-11-07 Chippac, Inc. Plastic semiconductor package
US6492699B1 (en) * 2000-05-22 2002-12-10 Amkor Technology, Inc. Image sensor package having sealed cavity over active area
US20030189257A1 (en) * 2002-04-08 2003-10-09 Corisis David J. Multi-chip module and methods
US6649446B1 (en) * 2001-11-29 2003-11-18 Clarisay, Inc. Hermetic package for multiple contact-sensitive electronic devices and methods of manufacturing thereof
US20040056342A1 (en) * 2002-05-08 2004-03-25 Cobbley Chad A. Stacked die module and techniques for forming a stacked die module
US6759307B1 (en) * 2000-09-21 2004-07-06 Micron Technology, Inc. Method to prevent die attach adhesive contamination in stacked chips
US20050040514A1 (en) * 2003-08-22 2005-02-24 Samsung Electronics Co., Ltd. Semiconductor package with improved chip attachment and manufacturing method thereof
US6894380B2 (en) * 2001-10-10 2005-05-17 Micron Technology, Inc. Packaged stacked semiconductor die and method of preparing same
US20050177268A1 (en) * 2004-01-22 2005-08-11 Hiroyuki Morinaga Design system for delivering data, system for fabricating a semiconductor device, method of communicating writing data, method for fabricating a semiconductor device
US6933172B2 (en) * 2002-02-25 2005-08-23 Seiko Epson Corporation Semiconductor wafer with spacer and its manufacturing method, semiconductor device and its manufacturing method, and circuit substrate and electronic device
US20050224959A1 (en) * 2004-04-01 2005-10-13 Chippac, Inc Die with discrete spacers and die spacing method
US20050277268A1 (en) * 2004-06-15 2005-12-15 Sharp Kabushiki Kaisha Manufacturing method of semiconductor wafer having lid part and manufacturing method of semiconductor device
US7022418B2 (en) * 2002-01-16 2006-04-04 Micron Technology, Inc. Fabrication of stacked microelectronic devices
US7180181B2 (en) * 2003-09-04 2007-02-20 Advanced Semiconductor Engineering, Inc. Mesh shaped dam mounted on a substrate
US20070200944A1 (en) * 2005-10-28 2007-08-30 Yasuo Takeuchi Manufacturing method for a solid-state imaging apparatus, and the solid-state imaging apparatus

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63126661A (en) 1986-11-17 1988-05-30 Suzuki Motor Co Ltd Production of piston
JPS63128736A (en) 1986-11-19 1988-06-01 Olympus Optical Co Ltd Semiconductor element
JPS63244654A (en) 1987-03-31 1988-10-12 Toshiba Corp Plastic molded type integrated circuit device
JPH0456262A (en) 1990-06-25 1992-02-24 Matsushita Electron Corp Semiconductor integrated circuit device

Patent Citations (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3851221A (en) * 1972-11-30 1974-11-26 P Beaulieu Integrated circuit package
US4103318A (en) * 1977-05-06 1978-07-25 Ford Motor Company Electronic multichip module
US4361261A (en) * 1978-11-22 1982-11-30 Kulicke & Soffa Industries, Inc. Apparatus for wire bonding
US4444349A (en) * 1981-05-04 1984-04-24 Kulicke & Soffa Industries, Inc. Wire bonding apparatus
US4567643A (en) * 1983-10-24 1986-02-04 Sintra-Alcatel Method of replacing an electronic component connected to conducting tracks on a support substrate
US4586642A (en) * 1985-05-13 1986-05-06 Kulicke And Soffa Industries Inc. Wire bond monitoring system
US4730232A (en) * 1986-06-25 1988-03-08 Westinghouse Electric Corp. High density microelectronic packaging module for high speed chips
US4763188A (en) * 1986-08-08 1988-08-09 Thomas Johnson Packaging system for multiple semiconductor devices
US4982265A (en) * 1987-06-24 1991-01-01 Hitachi, Ltd. Semiconductor integrated circuit device and method of manufacturing the same
US5040052A (en) * 1987-12-28 1991-08-13 Texas Instruments Incorporated Compact silicon module for high density integrated circuits
US5026667A (en) * 1987-12-29 1991-06-25 Analog Devices, Incorporated Producing integrated circuit chips with reduced stress effects
US5025306A (en) * 1988-08-09 1991-06-18 Texas Instruments Incorporated Assembly of semiconductor chips
US5172215A (en) * 1990-03-06 1992-12-15 Fuji Electric Co., Ltd. Overcurrent-limiting type semiconductor device
US5140404A (en) * 1990-10-24 1992-08-18 Micron Technology, Inc. Semiconductor device manufactured by a method for attaching a semiconductor die to a leadframe using a thermoplastic covered carrier tape
US5177032A (en) * 1990-10-24 1993-01-05 Micron Technology, Inc. Method for attaching a semiconductor die to a leadframe using a thermoplastic covered carrier tape
US5176311A (en) * 1991-03-04 1993-01-05 Kulicke And Soffa Investments, Inc. High yield clampless wire bonding method
US6492699B1 (en) * 2000-05-22 2002-12-10 Amkor Technology, Inc. Image sensor package having sealed cavity over active area
US6759307B1 (en) * 2000-09-21 2004-07-06 Micron Technology, Inc. Method to prevent die attach adhesive contamination in stacked chips
US20020037631A1 (en) * 2000-09-22 2002-03-28 Kabushiki Kaisha Shinkawa Method for manufacturing semiconductor devices
US20020090753A1 (en) * 2001-01-05 2002-07-11 Advanced Semiconductor Engineering Inc. Method for fabricating stacked chip package
US6661083B2 (en) * 2001-02-27 2003-12-09 Chippac, Inc Plastic semiconductor package
US20020163015A1 (en) * 2001-02-27 2002-11-07 Chippac, Inc. Plastic semiconductor package
US20020140073A1 (en) * 2001-03-28 2002-10-03 Advanced Semiconductor Engineering, Inc. Multichip module
US6894380B2 (en) * 2001-10-10 2005-05-17 Micron Technology, Inc. Packaged stacked semiconductor die and method of preparing same
US6649446B1 (en) * 2001-11-29 2003-11-18 Clarisay, Inc. Hermetic package for multiple contact-sensitive electronic devices and methods of manufacturing thereof
US7022418B2 (en) * 2002-01-16 2006-04-04 Micron Technology, Inc. Fabrication of stacked microelectronic devices
US6933172B2 (en) * 2002-02-25 2005-08-23 Seiko Epson Corporation Semiconductor wafer with spacer and its manufacturing method, semiconductor device and its manufacturing method, and circuit substrate and electronic device
US20030189257A1 (en) * 2002-04-08 2003-10-09 Corisis David J. Multi-chip module and methods
US20040056342A1 (en) * 2002-05-08 2004-03-25 Cobbley Chad A. Stacked die module and techniques for forming a stacked die module
US20050040514A1 (en) * 2003-08-22 2005-02-24 Samsung Electronics Co., Ltd. Semiconductor package with improved chip attachment and manufacturing method thereof
US7180181B2 (en) * 2003-09-04 2007-02-20 Advanced Semiconductor Engineering, Inc. Mesh shaped dam mounted on a substrate
US20050177268A1 (en) * 2004-01-22 2005-08-11 Hiroyuki Morinaga Design system for delivering data, system for fabricating a semiconductor device, method of communicating writing data, method for fabricating a semiconductor device
US20050224959A1 (en) * 2004-04-01 2005-10-13 Chippac, Inc Die with discrete spacers and die spacing method
US20050277268A1 (en) * 2004-06-15 2005-12-15 Sharp Kabushiki Kaisha Manufacturing method of semiconductor wafer having lid part and manufacturing method of semiconductor device
US20070200944A1 (en) * 2005-10-28 2007-08-30 Yasuo Takeuchi Manufacturing method for a solid-state imaging apparatus, and the solid-state imaging apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100164124A1 (en) * 2006-12-19 2010-07-01 Yong Du Method and apparatus for multi-chip packaging
US8324716B2 (en) * 2006-12-19 2012-12-04 Spansion Llc Method and apparatus for multi-chip packaging

Also Published As

Publication number Publication date
WO2009051975A2 (en) 2009-04-23
US7829379B2 (en) 2010-11-09
TWI400779B (en) 2013-07-01
US20090102060A1 (en) 2009-04-23
TW200929455A (en) 2009-07-01
WO2009051975A8 (en) 2009-10-29
WO2009051975A3 (en) 2009-09-24

Similar Documents

Publication Publication Date Title
US20110049712A1 (en) Wafer Level Stacked Die Packaging
USRE42349E1 (en) Wafer treating method for making adhesive dies
KR101185479B1 (en) Semiconductor device and method for manufacturing same
US20080085572A1 (en) Semiconductor packaging method by using large panel size
US7888172B2 (en) Chip stacked structure and the forming method
US8283251B2 (en) Method of manufacturing wafer level package
US7445963B2 (en) Semiconductor package having an interfacial adhesive layer
US20060192274A1 (en) Semiconductor package having double layer leadframe
US20080182363A1 (en) Method for forming a microelectronic assembly including encapsulating a die using a sacrificial layer
US11508671B2 (en) Semiconductor package and manufacturing method thereof
US20070215992A1 (en) Chip package and wafer treating method for making adhesive chips
US7888783B2 (en) Chip package structure and the method thereof with adhering the chips to a frame and forming UBM layers
US20070080435A1 (en) Semiconductor packaging process and carrier for semiconductor package
US7829389B2 (en) Roll-on encapsulation method for semiconductor packages
US8643177B2 (en) Wafers including patterned back side layers thereon
US20090085190A1 (en) Semiconductor Device and Method for Making Same
US20080265393A1 (en) Stack package with releasing layer and method for forming the same
US11881434B2 (en) Semiconductor die singulation
TW200933844A (en) Wafer level package with die receiving through-hole and method of the same
CN107680913B (en) Wafer level packaging method using lead frame
TWI425580B (en) Process for manufacturing semiconductor chip packaging module
US20200013701A1 (en) Wafer stencil for controlling die attach material thickness on die
US8785248B2 (en) Wafer level packaging using a lead-frame
CN215069986U (en) Double-layer plastic package 3D fan-out type packaging structure
US20230064066A1 (en) Wafer-level backside layer for semiconductor apparatus

Legal Events

Date Code Title Description
AS Assignment

Owner name: ANALOG DEVICES, INC., MASSACHUSETTS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GOIDA, THOMAS M.;REEL/FRAME:025079/0747

Effective date: 20071212

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION