US20110169574A1 - Equalization system with stabilized peaking gain for a communication system - Google Patents
Equalization system with stabilized peaking gain for a communication system Download PDFInfo
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- US20110169574A1 US20110169574A1 US12/687,861 US68786110A US2011169574A1 US 20110169574 A1 US20110169574 A1 US 20110169574A1 US 68786110 A US68786110 A US 68786110A US 2011169574 A1 US2011169574 A1 US 2011169574A1
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- variable gain
- equalization system
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/45197—Pl types
- H03F3/45206—Folded cascode stages
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/45197—Pl types
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/447—Indexing scheme relating to amplifiers the amplifier being protected to temperature influence
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45488—Indexing scheme relating to differential amplifiers the CSC being a pi circuit and a capacitor being used at the place of the resistor
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45504—Indexing scheme relating to differential amplifiers the CSC comprising more than one switch
Definitions
- Equalization amplifiers are commonly used in communication transceivers to compensate for a frequency dependent loss in the communication channels.
- these equalization amplifiers when used in binary serial transceivers, can reduce the inter-symbol interference (“ISI”) caused by high-frequency losses in the communication channels.
- ISI inter-symbol interference
- existing equalization amplifiers do not always adequately reduce the inter-symbol interference over different corner, temperature and voltage supply conditions.
- the communication transceiver that receives the transmitted data may have difficulty accurately recognizing the transmitted data. This can lead to data transmission errors.
- the present invention is directed to an equalization system that reduces inter-symbol interference in an input signal.
- the equalization system includes a variable gain amplifier, and one or more peaking amplifiers that are connected in series to the variable gain amplifier.
- the variable gain amplifier receives the input signal and scales the input signal. Further, each peaking amplifier selectively adjusts the peaking gain and the peaking corner frequency.
- the equalization system disclosed herein provides programmable and stabilized equalization gain, has a tunable peaking corner frequency, and superior common mode rejection.
- the equalization system additionally includes a PTAT bias generator that provides a PTAT bias current to one or more of the peaking amplifiers to maintain a transconductance of one or more of the peaking amplifiers substantially constant as temperature changes.
- one or more of the peaking amplifiers includes a programmable shunt capacitor array having one or more capacitor paths, and if there are multiple capacitor paths, they are connected in parallel.
- each capacitor path can include a variable capacitor and a capacitor switch that each can be selectively controlled to selectively control the capacitance of each capacitor path.
- each capacitor path can include a resistor that is in series with a bias voltage that is applied to the variable capacitor when the capacitor switch is closed.
- one or more of the peaking amplifiers includes a programmable resistor array having one or more resistor paths and if there are multiple resistor paths, they are connected in parallel.
- variable gain amplifier can also be designed to convert the input signal from a PMOS type common mode to an NMOS type common mode signal. Moreover, the variable gain amplifier can be used to adjust a variable gain with bandwidth extension.
- the variable gain amplifier includes a pair of folded PMOS transistors, a programmable resistor array, and a shunt capacitor.
- the present invention is also directed to a method for reducing inter-symbol interference in an input signal, the method including the steps of (i) scaling the input signal with a variable gain amplifier; and (ii) selectively adjusting the peaking gain and peaking corner frequency with a plurality of peaking amplifiers that are connected in series with the variable gain amplifier.
- FIG. 1 is a simplified illustration of a communication system with an equalization system having features of the present invention
- FIG. 2A is a simplified illustration of an input signal that is input into the equalization system of FIG. 1 ;
- FIG. 2B is a simplified illustration of an output signal that is output from the equalization system of FIG. 1 ;
- FIG. 3 is a graph that illustrates a gain curve
- FIG. 4 is a simplified block diagram of one embodiment of an equalization system having features of the present invention that includes a variable gain amplifier, a plurality of peaking amplifiers, and a PTAT bias generator;
- FIG. 5 is a simplified schematic that illustrates the electrical components of one embodiment of a variable gain amplifier having features of the present invention
- FIG. 6 is a simplified schematic that illustrates the electrical components of one embodiment of a peaking amplifier having features of the present invention
- FIG. 7 is a graph that illustrates capacitance-bias voltage (“C-V”) curve for a varactor having features of the present invention
- FIG. 8 is a simplified schematic that illustrates the components of one embodiment of a PTAT bias generator having features of the present invention
- FIG. 9 is a graph that illustrates two alternative common mode gain curves.
- FIG. 10 is a graph that illustrates a constant biasing current curve and a PTAT biasing current curve.
- FIG. 1 is a simplified illustration of one non-exclusive embodiment of a communication system 10 that includes a first component 12 (illustrated as a box), a second component 14 (illustrated as a box), and a communication channel 15 that electrically connects the components 12 , 14 together.
- the second component 14 includes a binary serial transceiver 16 (illustrated as a box) that transmits to and receives data from the first component 12 via the communication channel 15 .
- the transceiver 16 includes an equalization system 18 (illustrated as a box) that (i) compensates for frequency dependent losses in the communication channel 15 , (ii) effectively reduces any inter-symbol interference in an input signal 220 (illustrated in FIG.
- the communication transceiver 16 will receive and more accurately recognize the transmitted data.
- the type of communication system 10 that utilizes the equalization system 18 provided herein can vary.
- the communication system 10 can represent the serial communication between computers, or parts of a computer.
- the communication system 10 can represent the serial communication between a hard drive and central processing unit of a computer.
- FIG. 2A illustrates a non-exclusive example of the input data signal 220 that is received by and input into the equalization system 18 (illustrated in FIG. 1 )
- FIG. 2B illustrates a non-exclusive example of an output data signal 222 that is output from the equalization system 18 to the rest of the transceiver 16 (illustrated in FIG. 1 ) of FIG. 1 .
- Comparing the input signal 220 in FIG. 2A with the output signal 222 of FIG. 2B after the equalization system 18 , the eye diagram opening of the output data signal 222 has been enlarged significantly as compared to the input data signal 220 .
- the equalization system 18 has removed the inter-symbol interference from the input signal 220 . This makes it easier for the transceiver 16 to accurately recognize the transmitted information.
- FIG. 3 is a graph that illustrates a gain curve 324 that can be used to describe a number of the desired characteristics of the data signal. More specifically, there are a few critical performance specifications of the equalization system 18 , such as DC gain, peaking gain 326 , and peaking corner frequency 328 . These features can be better understood with reference to FIG. 3 . As provided herein, the equalization system 18 is uniquely designed to have programmability to adjust these performance parameters for different amount of channel loss and different data rates. Moreover, with the design provided herein, these electrical performance specifications are relatively stable across massive production quantities. Furthermore, the equalization system 18 provided herein is mostly implemented differentially. As a result thereof, the equalization system 18 rejects common mode input signal which is normally called common mode rejection.
- common mode rejection common mode rejection
- the equalization system 18 disclosed herein provides programmable and stabilized equalization gain, has a tunable peaking corner frequency, and superior common mode rejection.
- FIG. 4 is a simplified block diagram of one embodiment of the equalization system 18 .
- the equalization system 18 includes a variable gain amplifier (“VGA”) 430 , one or more peaking amplifiers 432 , and a PTAT bias generator 434 .
- VGA variable gain amplifier
- the input signals 220 (illustrated as a box) are input into the equalization system 18 on the left of the block diagram, while the output signals 222 (illustrated as a box) exit the equalization system 18 on the right.
- the input signals 220 initially enter the variable gain amplifier 430 and subsequently are directed to the cascading peaking amplifiers 432 .
- variable gain amplifier 430 doesn't provide the equalization function by itself.
- the variable gain amplifier 430 provided herein scales the amplitude of the input signals 220 to best fit the linear range of latter peaking amplifiers 432 .
- One reason for this scaling function is that it is not desirable to have amplitude clamping in the linear peaking amplifiers 432 .
- the variable gain amplifier 430 also is designed to convert input common mode at ground level to a comfortable level for the latter stage N-type CML circuits used in the cascading peaking amplifiers 432 .
- variable gain amplifier 430 performs common mode translation by translating the input PMOS type common mode to an NMOS type common mode signal so that more efficient NMOS transistors (as opposed to PMOS transistors) can be used in the subsequent peaking amplifiers 432 . Additionally, in certain embodiments, the variable gain amplifier 430 also adjusts the variable gain and performs bandwidth extension. Moreover, these functions can be implemented at same time with the variable gain amplifier 430 .
- the design scheme of one suitable variable gain amplifier 430 is illustrated in FIG. 5 and described below.
- the plurality of cascading peaking amplifiers 432 are used to provide a relatively large range of adjustment of the peaking gain and the peaking corner frequency.
- the multiple cascading peaking amplifiers can be used together to realized a peaking gain of up to approximately twenty-four decibels (24 dB).
- the total peaking gain of the equalization system 18 is adjusted in a step-wise fashion by adjusting the peaking gain of each of the cascading peaking amplifiers 432 .
- the number of peaking amplifiers 432 used in the equalization system 18 can be varied to achieve the design and adjustment requirements of the equalization system 18 .
- the equalization system 18 including five peaking amplifiers 432 that are connected in series. These peaking amplifiers 432 are labeled 432 A- 432 E for reference and can be referred to as first, second, third, fourth and fifth peaking amplifiers.
- the equalization system 18 can be designed to include more than five or fewer than five peaking amplifiers 432 .
- the design scheme of a suitable peaking amplifier 432 is illustrated in FIG. 6 and described below.
- each peaking amplifier 432 includes a programmable resistor array Rs and a programmable shunt capacitor array Cs.
- the total peaking gain of the equalization system 18 is adjusted by changing the peaking gain of each peaking amplifier 432 .
- the peaking gain of each peaking amplifier 432 is adjusted by changing the value of the resistance of the programmable resistor array Rs and the capacitance of the programmable shunt capacitor array. Therefore, by tweaking the programmable resistor array Rs and the programmable shunt capacitor array Cs of each peaking amplifier 432 , the total peaking gain can be adjusted and controlled in small steps, to best fit different channel loss.
- the PTAT bias generator 434 is electrically connected to each of the peaking amplifiers 432 and is used to bias each of the peaking amplifiers 432 .
- the PTAT bias generator 434 is designed to provide a PTAT biasing current that increases proportionally with temperture to each of the peaking amplifiers 432 .
- the design scheme of one suitable PTAT bias generator 434 is illustrated in FIG. 8 and is described below.
- the equalization 18 system can be designed so that each of the peaking amplifiers 432 is biased by a separate PTAT bias generator.
- FIG. 5 is a simplified schematic that illustrates the components of one embodiment of the variable gain amplifier 430 .
- the variable gain amplifier 430 is implemented with a first circuit portion 536 (illustrated with a dashed line) and a second circuit portion 538 (illustrated with a dashed line).
- the first circuit portion 536 includes (i) a pair of folded P-MOS input transistors T 1 540 A, T 2 540 B, (ii) a programmable resistor array Rs 544 , and (iii) a shunt capacitor Cs 546 .
- the pair of folded P-MOS input transistors T 1 540 A, T 2 540 B receive the input signal 220 , and the P-MOS input transistors T 1 540 A, T 2 540 B are source degenerated with the programmable resistor array Rs 544 . Further, the programmable resistor array Rs 544 can be controlled to simultaneously adjust the variable gain.
- the design of the programmable resistor array Rs 544 can be varied to achieve the desired level of source degeneration and variable gain.
- the programmable resistor array Rs 544 includes a first resistor path 544 A, a second resistor path 544 B, and a third resistor path 544 C, and the resistor paths 544 A- 544 C are connected in parallel with each other, and the programmable resistor array Rs 544 is in series with the P-MOS input transistors T 1 540 A, T 2 540 B.
- each resistor path 544 A- 544 C includes a spaced apart pair of resistors 548 and a pair of spaced apart resistor switches 550 .
- each resistor path 544 A- 544 C can be individually controlled to selectively control the overall resistance value of the programmable resistor array Rs 544 .
- the resistor paths 544 A- 544 C can be controlled so that the programmable resistor array Rs 544 has an overall resistance of between approximately one hundred and three hundred ohms.
- the system can designed so that the programmable resistor array Rs 544 has higher or lower overall resistance.
- a suitable resistor switch 550 can be a transistor having a gate that can be selectively opened and closed.
- the programmable resistor array Rs 544 of the variable gain amplifier 430 can be used to adjust the variable gain at least approximately ten, twenty, fifty or one-hundred percent.
- the programmable resistor array Rs 544 can be designed to have more than three or fewer than three resistor paths 544 A- 544 C, and/or each resistor path 544 A- 544 C can include more than or fewer than two resistors 548 .
- the first circuit portion 536 includes a bias voltage VBP 552 that is connected in series with each resistor path 544 A- 544 C.
- the bias voltage VBP 552 is used for biasing the pair of PMOS transistors T 1 540 A, T 2 540 B and causing the respective transistors to operate in a particular region of their transconductance curve.
- the DC bias voltage VBP 552 is independent from the input signal 220 .
- the shunt capacitor Cs 546 is used to boost the high frequency gain for bandwidth extension.
- the shunt capacitor Cs 546 is connected in parallel with the resistor paths 544 A- 544 C and in series with the PMOS transistors T 1 540 A, T 2 540 B.
- a non-exclusive example, of a suitable shunt capacitor Cs 546 has a capacitance of approximately 100 centumfarad.
- the shunt capacitor Cs 546 of the variable gain amplifier 430 can be used to boost the bandwidth of variable gain amplifier 430 at least approximately forty percent.
- input signal 220 (Sig In+, Sig In ⁇ ) is initially directed to the pair of PMOS transistors T 1 540 A, T 2 540 B of the first circuit portion 536 . Subsequently, the folded P-MOS transistors T 1 540 A, T 2 540 B steer the current into the second circuit portion 538 .
- input signal 220 (Sig In+, Sig In ⁇ ) is initially directed to the pair of PMOS transistors T 1 540 A, T 2 540 B of the first circuit portion 536 . Subsequently, the folded P-MOS transistors T 1 540 A, T 2 540 B steer the current into the second circuit portion 538 .
- FIG. 5 input signal 220 (Sig In+, Sig In ⁇ ) is initially directed to the pair of PMOS transistors T 1 540 A, T 2 540 B of the first circuit portion 536 . Subsequently, the folded P-MOS transistors T 1 540 A, T 2 540 B steer the current into the second circuit portion 538 .
- the second circuit portion 538 includes (i) a first pair of NMOS transistors T 3 554 A, T 4 554 B, (ii) a second pair of NMOS transistors T 5 556 A, T 6 556 B, (iii) a pair of load resistors RL 558 , (iv) a first DC bias voltage 560 connected to the first pair of NMOS transistors T 3 554 A, T 4 554 B, for biasing the first pair of NMOS transistors T 3 554 A, T 4 554 B and causing the respective transistors to operate in a particular region of their transconductance curve, and (v) a second DC bias voltage 562 connected to the second pair of NMOS transistors T 5 556 A, T 6 556 B, for biasing the second pair of NMOS transistors T 5 556 A, T 6 556 B and causing the respective transistors to operate in a particular region of their transconductance curve.
- the first and second DC bias voltages 560 connected to the first pair
- the second circuit portion 538 performs common mode translation by translating the input PMOS type common mode to an NMOS type common mode signal.
- the VGA output signal 564 (VGA Out+, VGA Out ⁇ ) is taken between the load resistors RL 558 and second pair of NMOS transistors T 5 556 A, T 6 556 B, and is subsequently directed to the latter peaking amplifiers 432 (illustrated in FIG. 4 ). It should be noted that, in certain embodiments, the VGA output signal 564 exiting from the variable gain amplifier 430 (i) has been scaled, (ii) has been converted to an NMOS type common mode signal, (iii) the high frequency gain has been boosted, and (iv) the bandwidth has been extended.
- FIG. 6 is a simplified schematic that illustrates the components of one embodiment of a peaking amplifier 432 having features of the present invention. It should be noted that one or more of the peaking amplifiers 432 A- 432 E (illustrated in FIG. 4 ) can have a design similar to that illustrated in FIG. 6 . As discussed above, the peaking amplifiers 432 are cascaded for relatively large range of peaking gain adjustment, with each individual peaking amplifier providing a controllable in size step-wise adjustment to the peaking gain, and the overall adjustment in the peaking gain being a summation of the step-wise adjustments from the individual peaking amplifiers 432 A- 432 E.
- the peaking amplifier 432 is an N-type current-mode-logic amplifier with resistive source degeneration and capacitive shunt path for high frequency peaking.
- the peaking amplifier 432 includes (i) a pair of NMOS transistors T 7 668 A, T 8 668 B; (ii) a pair of load resistors R L 670 A, 670 B that also have a capacitance of C L ; (iii) a programmable resistor array R s 672 ; and (iv) a shunt capacitor array C s 674 .
- the pair of load resistors R L 670 A, 670 B can be used to in conjunction with the NMOS transistors T 7 668 A, T 8 668 B to control the peaking gain of the peaking amplifier 432 .
- These load resistors R L 670 A, 670 B are connected in series with the NMOS transistors T 7 668 A, T 8 668 B.
- a non-exclusive example of a suitable load resistor R L 670 A, 670 B has a resistance of approximately one hundred ohms, a capacitance of approximately thirty sF.
- the programmable resistor array R s 672 can be used to suppress degeneration, and is used in conjunction with the shunt capacitor array C s 674 to adjust the gain of the signal.
- the design of the programmable resistor array R s 672 can be varied to achieve the desired level of adjustment of the variable gain.
- the programmable resistor array R s 672 includes a first resistor path 672 A, a second resistor path 672 B, and a third resistor path 672 C, and the resistor paths 672 A- 672 C are connected in parallel with each other.
- each resistor path 672 A- 672 C includes a spaced apart pair of resistors 676 and a resistor switch 678 .
- the resistor switch 678 of each resistor path 672 A- 672 C can be individually controlled to selectively control the overall resistance of the programmable resistor array R s 672 .
- the resistor paths 672 A- 672 C can be individually controlled so that the programmable resistor array Rs 672 has an overall resistance of between approximately one hundred and three hundred ohms.
- the system can designed so that the programmable resistor array Rs 672 has higher or lower overall resistance.
- a non-exclusive example of a suitable resistor 676 for each resistor path 672 A- 672 C can be a poly resistor having a resistance of approximately two hundred ohms.
- a suitable resistor switch 678 can be a transistor having a gate that can be selectively opened and closed.
- the programmable resistor array R s 672 can be designed to have more than three or fewer than three resistor paths 672 A- 672 C, and/or each resistor path 672 A- 672 C can include more than or fewer than two resistors 676 .
- the shunt capacitor array C s 674 is used to provide a wide tuning range of peaking corner frequency with a large tuning ratio of shunt capacitors. This wide tuning range is a desired feature since designers want to cover a variety of data rates. Moreover, lower data rate requires lower corner frequency.
- the design of the shunt capacitor array C s 674 can be varied to achieve the desired level of tuning range of the peaking corner frequency.
- the shunt capacitor array C s 674 includes a first capacitor path 674 A, a second capacitor path 674 B, and a third capacitor path 674 C; and the capacitor paths 674 A- 672 C are connected in parallel with each other.
- Each capacitor path 674 A- 674 C can be individually controlled to provide a controlled amount of capacitance for the shunt capacitor array C s 674 . Moreover, each capacitor paths 674 A- 672 C is connected in parallel with each resistor path 672 A- 672 C.
- each capacitor path 674 A- 672 C includes a pair of variable capacitors C var 680 A, 680 B, a capacitor switch 682 , and a pair of resistors R B 684 A, 684 B.
- the bias voltage for the variable capacitors C var 680 A, 680 B are connected in series with the resistors R B 684 A, 684 B when the serial capacitor switch 682 is closed.
- the capacitor switch 682 of each capacitor path 674 A- 674 C can be individually controlled to selectively control the overall capacitance of the programmable capacitor array C s 674 .
- the shunt capacitor array C s 674 can be designed to have more than three or fewer than three capacitor paths 674 A- 672 C, and/or one or more of the capacitor paths 674 A- 672 C can have a different design than that illustrated in FIG. 6 .
- a PA input signal 686 (PA In+, PA In ⁇ ) is directed to the pair of NMOS transistors T 7 668 A, T 8 668 .
- the peaking amplifier 432 of FIG. 6 is the first peaking amplifier 432 A (illustrated in FIG. 4 )
- the PA input signal 686 is same at the VGA output signal 564 (illustrated in FIG. 5 ) from the variable gain amplifier 430 (illustrated in FIG. 4 ).
- the peaking amplifier 432 of FIG. 6 is a subsequent one of the cascading peaking amplifiers 432 B- 432 E
- the PA input signal 686 is the same as the PA output signal 687 from the previous one of the cascading peaking amplifiers 432 A- 432 D.
- the DC gain of the PA input signal 686 is suppressed by degeneration by programmable resistor array R s 672 , and, in high frequency, the gain is restored with variable capacitors C var 680 A, 680 B in shunt with the resistors R B 684 A, 684 B
- the degeneration load resistors R L 670 A, 670 B and the transconductance (gm) of the NMOS transistors T 7 668 A, T 8 668 B control the peaking gain of the peaking amplifier 432 .
- the programmable resistor array R s 672 , the shunt capacitor array C s 674 , and the transconductance (gm) of the NMOS transistors T 7 668 A, T 8 668 together decide the peaking corner frequency of output signal from the peaking amplifier 432 .
- Their relationship can be roughly represented by Equations 1-3.
- H ⁇ ( s ) g m ⁇ R L 1 + sR L ⁇ C L ⁇ 1 + sR s ⁇ C s 1 + g m ⁇ R s + sR s ⁇ C s Equation ⁇ ⁇ 1 Peaking ⁇ ⁇ Gain ⁇ 1 + g m ⁇ R s Equation ⁇ ⁇ 2 Peaking ⁇ ⁇ Corner ⁇ ⁇ Frequency ⁇ 1 + g m ⁇ R s R s ⁇ C s Equation ⁇ ⁇ 3
- H(s) represents the transfer function in the Laplace domain
- s represents a complex variable
- R s is the resistance of the programmable resistor array 672
- C s is the capacitance of the programmable capacitor array 674
- G m is the transconductance of the NMOS transistors T 7 668 A, T 8 668
- R L is the resistance of the load resistors 670 A, 670 B
- C L is the capacitance of the load resistors 670 A, 670 B.
- Equations 1-3 it is straight forward to determine the following conclusions: (i) the peaking gain can be adjusted by changing the resistance of the programmable resistor array R s 672 ; (ii) the peaking corner frequency can be adjusted by changing the capacitance of the shunt capacitor array C s 674 ; and (iii) the peaking gain can be disabled by disconnecting the shunt capacitor array C s 674 .
- these equations show how to keep the peaking gain and the peaking corner frequency stable during changes in PVT.
- Semiconductor devices are subject to many variations such as manufacturing skew corners, temperature and voltage supply. These three dominant factors are also known as PVT variation. All these factors contribute to the change of the performance of the equalization amplifier.
- the present invention is effective in removing the inter-symbol interference across different corner, temperature and voltage supply conditions. Moreover, the present invention is provides superior common mode rejection.
- the peaking gain from each individual peaking amplifier 432 can be adjusted by changing the value of programmable resistor array R s 672 and value of the shunt capacitor array C s 674 . Therefore, by tweaking the value of programmable resistor array R s 672 and value of the shunt capacitor array C s 674 for each individual peaking amplifier 432 , each individual peaking amplifier 432 can be used to make a relatively small, step-wise controllable adjustment in gain.
- the step-wise gains are summed, and the overall gain of the equalization system 18 can be controlled to obtain a relatively large total gain (e.g. total 24 dB gain) at a controlled small step, to best fit different channel loss in the communication system 10 .
- each peaking amplifier 432 A- 432 E can be used to make a step-wise gain of at least approximately 1, 2, 3, 4, 5, or 6 dB.
- the system can make an adjustment in gain of at least approximately 5, 10, 15, 20, 25, or 30 dB. It should be noted that these adjustments can be made in any step wise increment smaller or larger than the examples provided herein.
- variable capacitors C var 680 A, 680 B are implemented with a varactor.
- its capacitance density is much higher than metal capacitor and the capacitance changes monotonically with the voltage across its gate node 688 A and its bulk node 688 B across a wide voltage range.
- the location of the gate node 688 A and the bulk node 688 A of one of the variable capacitors C var 680 A, 680 B is illustrated in FIG. 6
- a non-exclusive example of a suitable variable capacitor C VAR 680 A, 680 B for each capacitor path 674 A- 672 B has a capacitance that varies between one Pico farad and ten Pico farad.
- FIG. 7 is a graph that illustrates capacitance-bias voltage (“C-V”) curve 790 for one embodiment of a varactor that can be used in the variable capacitors C VAR 680 A, 680 B of FIG. 6 .
- C-V capacitance-bias voltage
- the capacitance of the varactor increases as the bias voltage applied across the gate and bulk nodes of the varactor increases.
- the C-V curve 790 includes a first zone 792 (illustrated with dashed box) and a second zone 794 (illustrated with dashed box) in which the capacitance of the varactor is fairly constant with its bias voltage.
- the capacitance is not fairly constant between the two zones 792 , 794 as the bias voltage varies.
- the bias voltage to each varactor can be selectively controlled so that the varactor is operating in either the first zone 792 , the second zone 794 , or somewhere therebetween.
- the bias voltage applied to the varactors can be used to control the capacitance of the variable capacitors C VAR 680 A, 680 B.
- the peaking amplifier 432 adjusts the peaking corner frequency by changing value of the shunt capacitor array C s 674 .
- this feature can be realized with doing two adjustments at the same time to each individual capacitor path 674 A- 674 C.
- One adjustment is turning on/off (opening/closing) the capacitor switch 682 that in series with the variable capacitors C var 680 A, 680 B for each individual capacitor path 674 A- 674 C.
- the other is to change a bias voltage applied to the variable capacitors C var 680 A, 680 B for each individual capacitor path 674 A- 674 C.
- a first bias voltage C_ 0 can be selectively applied (by a first bias voltage source to the area between the resistors R B 684 A, 684 B of the first capacitor path 674 A) to the variable capacitors C var 680 A, 680 B of the first capacitor path 674 A
- a second bias voltage C_ 1 can be selectively applied (by a second bias voltage source to the area between the resistors R B 684 A, 684 B of the second capacitor path 674 B) to the variable capacitors C var 680 A, 680 B of the second capacitor path 674 B
- a third bias voltage C_ 2 can be selectively applied (by a third bias voltage source to the area between the resistors R B 684 A, 684 B of the third capacitor path 674 C) to the variable capacitors C var 680 A, 680 B of the third capacitor path 674 C. Doing these two adjustments at the same time can minimize the impact from the parasitic capacitance from the capacitor switch 6
- variable capacitors C var 680 A, 680 B are connected in parallel with the programmable resistor array R s 672 or disconnected. Further, for each individual capacitor path 674 A, 674 B, (i) the bias voltage applied to the variable capacitors C var 680 A, 680 B is connected in series with the resistors R B 684 A, 684 B when the serial capacitor switch 682 is closed.
- the capacitance value of the variable capacitors C var 680 A, 680 B is changed (as illustrated in FIG. 7 ).
- the bias voltage at C_ 0 , C_ 1 , C_ 2 the capacitance value for each individual capacitor path 674 A- 674 C can be individually tuned and adjusted.
- a suitable capacitor switch 682 can be a transistor having a gate that can be selectively opened and closed. Further, the parasitic cap 689 of the capacitor switch 682 is also illustrated in FIG. 6 .
- each capacitor path 674 A- 674 C (i) when the respective bias voltage (C_ 0 , C_ 1 , C_ 2 ) is at ground, and when the capacitor switch 683 is closed, the varactor has a relatively high capacitance, and (ii) when, the respective bias voltage (C_ 0 , C_ 1 , C_ 2 ) is not at ground, and when the capacitor switch 683 is open, the varactor has a relatively low capacitance.
- This provides high tuning range for the capacitor paths 674 A- 674 C that can be individually tuned by selectively controlling the capacitor switch 683 and the bias voltage (C_ 0 , C_ 1 , C_ 2 ) for each capacitor path 674 A- 674 C.
- the resistors R B 684 A, 684 B of each individual capacitor path 674 A- 674 C is used to block the signal path from the variable capacitors C var 680 A, 680 B to the respective low impedance bias voltage sources C_ 0 , C_ 1 , C_ 2 . This can boost the common mode impedance of the variable capacitors C var 680 A, 680 B and improve the common mode rejection characteristics of the peaking amplifier 432 .
- a non-exclusive example of a suitable resistor R B 684 A, 684 B for each capacitor path 674 A- 672 B has a resistance of between approximately five and twenty kilo ohms.
- the PA output signal 687 (PA Out+, PA Out ⁇ ) is taken between the NMOS transistors T 7 668 A, T 8 668 and the load resistors R L 670 A, 670 B.
- the peaking amplifier 432 receives a PTAT bias current I BIAS from the PTAT bias generator 434 (illustrated in FIG. 6 ).
- the PTAT bias generator 434 is electrically connected to each of the peaking amplifiers 432 and is used to bias the NMOS transistors T 7 668 A, T 8 668 of each of the peaking amplifiers 432 .
- the PTAT bias generator 434 is designed to provide a PTAT biasing current having a value that increases proportionally with temperature.
- the PTAT bias current I BIAS can be used to maintain the transconductance G m of the NMOS transistors T 7 668 A, T 8 668 substantially constant as temperature changes. This feature reduces the influence of temperature on each peaking amplifier 432 .
- FIG. 8 is a simplified schematic that illustrates the components of one, non-exclusive embodiment a suitable the PTAT bias generator 434 .
- the PTAT bias generator 434 generates a reference bias current I BIAS that is proportional to temperature, inversely proportional to R BIAS , and does not change with the power supply.
- I BIAS reference bias current
- the value of the transconductance G m of the NMOS transistors T 7 668 A, T 8 668 of the peaking amplifiers 432 is kept approximately constant with temperature change.
- FIG. 9 is a graph that illustrates two alternative common mode gain curves, namely a first common mode gain curve 996 (illustrated with a long dashed line and circles), and a second common mode gain curve 997 (illustrated with a solid line).
- the resistors R B 684 A, 684 B of each individual capacitor path 674 A- 674 C are used to block the signal path from the variable capacitors C var 680 A, 680 B to the respective low impedance bias voltage C_ 0 , C_ 1 , C_ 2 . This can boost the common mode impedance of the variable capacitors C var 680 A, 680 B and improve the common mode rejection characteristics of the peaking amplifier 432 .
- the first common mode gain curve 996 represents the results from a peaking amplifier (not shown) that does not use the resistors R B 684 A, 684 B in the capacitor paths 674 A- 674 C; and (ii) the second common mode gain curve 997 represents the results from a peaking amplifier 432 (illustrated in FIG. 6 ) that uses resistors R B 684 A, 684 B in the capacitor paths 674 A- 674 .
- the first common mode gain curve 996 has an undesirable peaking higher frequency, while the second common mode gain curve 997 does not have the peaking higher frequency.
- the resistors R B 684 A, 684 B improve the common mode rejection characteristics of the peaking amplifier 432 .
- FIG. 10 illustrates a constant biasing current curve 1098 (illustrated with a long dashed line and circles) and a PTAT biasing current curve 1099 (illustrated with a solid line) that can be generated by the PTAT bias generator 434 illustrated in FIG. 8 .
- the constant biasing current curve 1098 the transconductance G m varies greatly as temperature changes.
- the PTAT biasing current curve 1099 the transconductance G m is substantially constant (varies less than approximately plus or minus five or ten percent over the operational temperature range of the system) as temperature changes.
Abstract
Description
- In communication systems, data is often transferred over one or more communication channels between two or more components. These components often include communication transceivers for receiving and transmitting data. Equalization amplifiers are commonly used in communication transceivers to compensate for a frequency dependent loss in the communication channels. For example, these equalization amplifiers, when used in binary serial transceivers, can reduce the inter-symbol interference (“ISI”) caused by high-frequency losses in the communication channels. Unfortunately, existing equalization amplifiers do not always adequately reduce the inter-symbol interference over different corner, temperature and voltage supply conditions. As a result thereof, the communication transceiver that receives the transmitted data may have difficulty accurately recognizing the transmitted data. This can lead to data transmission errors.
- The present invention is directed to an equalization system that reduces inter-symbol interference in an input signal. In one embodiment, the equalization system includes a variable gain amplifier, and one or more peaking amplifiers that are connected in series to the variable gain amplifier. In this embodiment, the variable gain amplifier receives the input signal and scales the input signal. Further, each peaking amplifier selectively adjusts the peaking gain and the peaking corner frequency. With this design, the equalization system disclosed herein provides programmable and stabilized equalization gain, has a tunable peaking corner frequency, and superior common mode rejection.
- In one embodiment, the equalization system additionally includes a PTAT bias generator that provides a PTAT bias current to one or more of the peaking amplifiers to maintain a transconductance of one or more of the peaking amplifiers substantially constant as temperature changes.
- In certain embodiments, one or more of the peaking amplifiers includes a programmable shunt capacitor array having one or more capacitor paths, and if there are multiple capacitor paths, they are connected in parallel. Further, each capacitor path can include a variable capacitor and a capacitor switch that each can be selectively controlled to selectively control the capacitance of each capacitor path. Additionally, each capacitor path can include a resistor that is in series with a bias voltage that is applied to the variable capacitor when the capacitor switch is closed.
- Moreover, in certain embodiments, one or more of the peaking amplifiers includes a programmable resistor array having one or more resistor paths and if there are multiple resistor paths, they are connected in parallel.
- As provided herein, the variable gain amplifier can also be designed to convert the input signal from a PMOS type common mode to an NMOS type common mode signal. Moreover, the variable gain amplifier can be used to adjust a variable gain with bandwidth extension. In certain embodiments, the variable gain amplifier includes a pair of folded PMOS transistors, a programmable resistor array, and a shunt capacitor.
- The present invention is also directed to a method for reducing inter-symbol interference in an input signal, the method including the steps of (i) scaling the input signal with a variable gain amplifier; and (ii) selectively adjusting the peaking gain and peaking corner frequency with a plurality of peaking amplifiers that are connected in series with the variable gain amplifier.
- The novel features of this invention, as well as the invention itself, both as to its structure and its operation, will be best understood from the accompanying drawings, taken in conjunction with the accompanying description, in which similar reference characters refer to similar parts, and in which:
-
FIG. 1 is a simplified illustration of a communication system with an equalization system having features of the present invention; -
FIG. 2A is a simplified illustration of an input signal that is input into the equalization system ofFIG. 1 ; -
FIG. 2B is a simplified illustration of an output signal that is output from the equalization system ofFIG. 1 ; -
FIG. 3 is a graph that illustrates a gain curve; -
FIG. 4 is a simplified block diagram of one embodiment of an equalization system having features of the present invention that includes a variable gain amplifier, a plurality of peaking amplifiers, and a PTAT bias generator; -
FIG. 5 is a simplified schematic that illustrates the electrical components of one embodiment of a variable gain amplifier having features of the present invention; -
FIG. 6 is a simplified schematic that illustrates the electrical components of one embodiment of a peaking amplifier having features of the present invention; -
FIG. 7 is a graph that illustrates capacitance-bias voltage (“C-V”) curve for a varactor having features of the present invention; -
FIG. 8 is a simplified schematic that illustrates the components of one embodiment of a PTAT bias generator having features of the present invention; -
FIG. 9 is a graph that illustrates two alternative common mode gain curves; and -
FIG. 10 is a graph that illustrates a constant biasing current curve and a PTAT biasing current curve. -
FIG. 1 is a simplified illustration of one non-exclusive embodiment of acommunication system 10 that includes a first component 12 (illustrated as a box), a second component 14 (illustrated as a box), and acommunication channel 15 that electrically connects thecomponents second component 14 includes a binary serial transceiver 16 (illustrated as a box) that transmits to and receives data from thefirst component 12 via thecommunication channel 15. Moreover, in this embodiment, thetransceiver 16 includes an equalization system 18 (illustrated as a box) that (i) compensates for frequency dependent losses in thecommunication channel 15, (ii) effectively reduces any inter-symbol interference in an input signal 220 (illustrated inFIG. 2A ) received by thetransceiver 16 across different corner, temperature and voltage supply conditions, and (iii) improves the signal integrity of theinput signal 220. As a result thereof, thecommunication transceiver 16 will receive and more accurately recognize the transmitted data. - The type of
communication system 10 that utilizes theequalization system 18 provided herein can vary. For example, thecommunication system 10 can represent the serial communication between computers, or parts of a computer. As one non-exclusive example, thecommunication system 10 can represent the serial communication between a hard drive and central processing unit of a computer. -
FIG. 2A illustrates a non-exclusive example of theinput data signal 220 that is received by and input into the equalization system 18 (illustrated inFIG. 1 ), andFIG. 2B illustrates a non-exclusive example of anoutput data signal 222 that is output from theequalization system 18 to the rest of the transceiver 16 (illustrated inFIG. 1 ) ofFIG. 1 . Comparing theinput signal 220 inFIG. 2A with theoutput signal 222 ofFIG. 2B , after theequalization system 18, the eye diagram opening of theoutput data signal 222 has been enlarged significantly as compared to theinput data signal 220. Thus, theequalization system 18 has removed the inter-symbol interference from theinput signal 220. This makes it easier for thetransceiver 16 to accurately recognize the transmitted information. -
FIG. 3 is a graph that illustrates again curve 324 that can be used to describe a number of the desired characteristics of the data signal. More specifically, there are a few critical performance specifications of theequalization system 18, such as DC gain, peakinggain 326, and peaking corner frequency 328. These features can be better understood with reference toFIG. 3 . As provided herein, theequalization system 18 is uniquely designed to have programmability to adjust these performance parameters for different amount of channel loss and different data rates. Moreover, with the design provided herein, these electrical performance specifications are relatively stable across massive production quantities. Furthermore, theequalization system 18 provided herein is mostly implemented differentially. As a result thereof, theequalization system 18 rejects common mode input signal which is normally called common mode rejection. - As provided herein, the
equalization system 18 disclosed herein provides programmable and stabilized equalization gain, has a tunable peaking corner frequency, and superior common mode rejection. -
FIG. 4 is a simplified block diagram of one embodiment of theequalization system 18. In this embodiment, theequalization system 18 includes a variable gain amplifier (“VGA”) 430, one ormore peaking amplifiers 432, and aPTAT bias generator 434. InFIG. 4 , the input signals 220 (illustrated as a box) are input into theequalization system 18 on the left of the block diagram, while the output signals 222 (illustrated as a box) exit theequalization system 18 on the right. In this embodiment, the input signals 220 initially enter thevariable gain amplifier 430 and subsequently are directed to the cascading peakingamplifiers 432. - In certain embodiments, the
variable gain amplifier 430 doesn't provide the equalization function by itself. In one embodiment, thevariable gain amplifier 430 provided herein scales the amplitude of the input signals 220 to best fit the linear range oflatter peaking amplifiers 432. One reason for this scaling function is that it is not desirable to have amplitude clamping in thelinear peaking amplifiers 432. Additionally, in certain embodiments, thevariable gain amplifier 430 also is designed to convert input common mode at ground level to a comfortable level for the latter stage N-type CML circuits used in the cascading peakingamplifiers 432. Thus, thevariable gain amplifier 430 performs common mode translation by translating the input PMOS type common mode to an NMOS type common mode signal so that more efficient NMOS transistors (as opposed to PMOS transistors) can be used in thesubsequent peaking amplifiers 432. Additionally, in certain embodiments, thevariable gain amplifier 430 also adjusts the variable gain and performs bandwidth extension. Moreover, these functions can be implemented at same time with thevariable gain amplifier 430. The design scheme of one suitablevariable gain amplifier 430 is illustrated inFIG. 5 and described below. - The plurality of cascading peaking
amplifiers 432 are used to provide a relatively large range of adjustment of the peaking gain and the peaking corner frequency. As a non-exclusive example, the multiple cascading peaking amplifiers can be used together to realized a peaking gain of up to approximately twenty-four decibels (24 dB). With this design, the total peaking gain of theequalization system 18 is adjusted in a step-wise fashion by adjusting the peaking gain of each of the cascading peakingamplifiers 432. - The number of peaking
amplifiers 432 used in theequalization system 18 can be varied to achieve the design and adjustment requirements of theequalization system 18. InFIG. 4 , theequalization system 18 including fivepeaking amplifiers 432 that are connected in series. These peakingamplifiers 432 are labeled 432A-432E for reference and can be referred to as first, second, third, fourth and fifth peaking amplifiers. Alternatively, theequalization system 18 can be designed to include more than five or fewer than five peakingamplifiers 432. The design scheme of asuitable peaking amplifier 432 is illustrated inFIG. 6 and described below. - As provided in more detail below, each peaking
amplifier 432 includes a programmable resistor array Rs and a programmable shunt capacitor array Cs. As provided herein, the total peaking gain of theequalization system 18 is adjusted by changing the peaking gain of each peakingamplifier 432. Further, the peaking gain of each peakingamplifier 432 is adjusted by changing the value of the resistance of the programmable resistor array Rs and the capacitance of the programmable shunt capacitor array. Therefore, by tweaking the programmable resistor array Rs and the programmable shunt capacitor array Cs of each peakingamplifier 432, the total peaking gain can be adjusted and controlled in small steps, to best fit different channel loss. - The
PTAT bias generator 434 is electrically connected to each of the peakingamplifiers 432 and is used to bias each of the peakingamplifiers 432. In certain embodiments, thePTAT bias generator 434 is designed to provide a PTAT biasing current that increases proportionally with temperture to each of the peakingamplifiers 432. The design scheme of one suitablePTAT bias generator 434 is illustrated inFIG. 8 and is described below. Alternatively, theequalization 18 system can be designed so that each of the peakingamplifiers 432 is biased by a separate PTAT bias generator. -
FIG. 5 is a simplified schematic that illustrates the components of one embodiment of thevariable gain amplifier 430. In one embodiment, thevariable gain amplifier 430 is implemented with a first circuit portion 536 (illustrated with a dashed line) and a second circuit portion 538 (illustrated with a dashed line). In this embodiment, thefirst circuit portion 536 includes (i) a pair of folded P-MOSinput transistors T1 540A,T2 540B, (ii) a programmableresistor array Rs 544, and (iii) ashunt capacitor Cs 546. - In this embodiment, the pair of folded P-MOS
input transistors T1 540A,T2 540B receive theinput signal 220, and the P-MOSinput transistors T1 540A,T2 540B are source degenerated with the programmableresistor array Rs 544. Further, the programmableresistor array Rs 544 can be controlled to simultaneously adjust the variable gain. - The design of the programmable
resistor array Rs 544 can be varied to achieve the desired level of source degeneration and variable gain. InFIG. 5 , the programmableresistor array Rs 544 includes afirst resistor path 544A, asecond resistor path 544B, and athird resistor path 544C, and theresistor paths 544A-544C are connected in parallel with each other, and the programmableresistor array Rs 544 is in series with the P-MOSinput transistors T1 540A,T2 540B. Further, inFIG. 5 , eachresistor path 544A-544C includes a spaced apart pair ofresistors 548 and a pair of spaced apart resistor switches 550. In one embodiment, (i) for eachresistor path 544A-544C, both resistor switches 550 are controlled to be opened or closed concurrently, and (ii) eachresistor path 544A-544C can be individually controlled to selectively control the overall resistance value of the programmableresistor array Rs 544. As non-exclusive example, theresistor paths 544A-544C can be controlled so that the programmableresistor array Rs 544 has an overall resistance of between approximately one hundred and three hundred ohms. Alternatively, the system can designed so that the programmableresistor array Rs 544 has higher or lower overall resistance. - Further, a
suitable resistor switch 550 can be a transistor having a gate that can be selectively opened and closed. As non-exclusive examples, the programmableresistor array Rs 544 of thevariable gain amplifier 430 can be used to adjust the variable gain at least approximately ten, twenty, fifty or one-hundred percent. - Alternatively, the programmable
resistor array Rs 544 can be designed to have more than three or fewer than threeresistor paths 544A-544C, and/or eachresistor path 544A-544C can include more than or fewer than tworesistors 548. - Additionally, in
FIG. 5 , thefirst circuit portion 536 includes abias voltage VBP 552 that is connected in series with eachresistor path 544A-544C. In this embodiment, thebias voltage VBP 552 is used for biasing the pair ofPMOS transistors T1 540A,T2 540B and causing the respective transistors to operate in a particular region of their transconductance curve. As provided herein, the DCbias voltage VBP 552 is independent from theinput signal 220. - The
shunt capacitor Cs 546 is used to boost the high frequency gain for bandwidth extension. InFIG. 5 , theshunt capacitor Cs 546 is connected in parallel with theresistor paths 544A-544C and in series with thePMOS transistors T1 540A,T2 540B. A non-exclusive example, of a suitableshunt capacitor Cs 546 has a capacitance of approximately 100 centumfarad. As a non-exclusive example, theshunt capacitor Cs 546 of thevariable gain amplifier 430 can be used to boost the bandwidth ofvariable gain amplifier 430 at least approximately forty percent. - In
FIG. 5 , input signal 220 (Sig In+, Sig In−) is initially directed to the pair ofPMOS transistors T1 540A,T2 540B of thefirst circuit portion 536. Subsequently, the folded P-MOS transistors T1 540A,T2 540B steer the current into thesecond circuit portion 538. InFIG. 5 , thesecond circuit portion 538 includes (i) a first pair ofNMOS transistors T3 554A,T4 554B, (ii) a second pair ofNMOS transistors T5 556A,T6 556B, (iii) a pair ofload resistors RL 558, (iv) a firstDC bias voltage 560 connected to the first pair ofNMOS transistors T3 554A,T4 554B, for biasing the first pair ofNMOS transistors T3 554A,T4 554B and causing the respective transistors to operate in a particular region of their transconductance curve, and (v) a secondDC bias voltage 562 connected to the second pair ofNMOS transistors T5 556A,T6 556B, for biasing the second pair ofNMOS transistors T5 556A,T6 556B and causing the respective transistors to operate in a particular region of their transconductance curve. As provided herein, the first and second DC bias voltages 560, 562 are independent from theinput signal 220. - In this embodiment, the
second circuit portion 538 performs common mode translation by translating the input PMOS type common mode to an NMOS type common mode signal. - In
FIG. 5 , the VGA output signal 564 (VGA Out+, VGA Out−) is taken between theload resistors RL 558 and second pair ofNMOS transistors T5 556A,T6 556B, and is subsequently directed to the latter peaking amplifiers 432 (illustrated inFIG. 4 ). It should be noted that, in certain embodiments, theVGA output signal 564 exiting from the variable gain amplifier 430 (i) has been scaled, (ii) has been converted to an NMOS type common mode signal, (iii) the high frequency gain has been boosted, and (iv) the bandwidth has been extended. -
FIG. 6 is a simplified schematic that illustrates the components of one embodiment of a peakingamplifier 432 having features of the present invention. It should be noted that one or more of the peakingamplifiers 432A-432E (illustrated inFIG. 4 ) can have a design similar to that illustrated inFIG. 6 . As discussed above, the peakingamplifiers 432 are cascaded for relatively large range of peaking gain adjustment, with each individual peaking amplifier providing a controllable in size step-wise adjustment to the peaking gain, and the overall adjustment in the peaking gain being a summation of the step-wise adjustments from theindividual peaking amplifiers 432A-432E. - In
FIG. 6 , the peakingamplifier 432 is an N-type current-mode-logic amplifier with resistive source degeneration and capacitive shunt path for high frequency peaking. InFIG. 6 , the peakingamplifier 432 includes (i) a pair ofNMOS transistors T7 668A,T8 668B; (ii) a pair ofload resistors R resistor array R s 672; and (iv) a shuntcapacitor array C s 674. - As provided herein, the pair of
load resistors R NMOS transistors T7 668A,T8 668B to control the peaking gain of the peakingamplifier 432. Theseload resistors R NMOS transistors T7 668A,T8 668B. A non-exclusive example of a suitableload resistor R - The programmable
resistor array R s 672 can be used to suppress degeneration, and is used in conjunction with the shuntcapacitor array C s 674 to adjust the gain of the signal. The design of the programmableresistor array R s 672 can be varied to achieve the desired level of adjustment of the variable gain. InFIG. 6 , the programmableresistor array R s 672 includes afirst resistor path 672A, asecond resistor path 672B, and athird resistor path 672C, and theresistor paths 672A-672C are connected in parallel with each other. Further, inFIG. 6 , eachresistor path 672A-672C includes a spaced apart pair of resistors 676 and aresistor switch 678. In one embodiment, theresistor switch 678 of eachresistor path 672A-672C can be individually controlled to selectively control the overall resistance of the programmableresistor array R s 672. As a non-exclusive example, theresistor paths 672A-672C can be individually controlled so that the programmableresistor array Rs 672 has an overall resistance of between approximately one hundred and three hundred ohms. Alternatively, the system can designed so that the programmableresistor array Rs 672 has higher or lower overall resistance. - A non-exclusive example of a suitable resistor 676 for each
resistor path 672A-672C can be a poly resistor having a resistance of approximately two hundred ohms. Further, asuitable resistor switch 678 can be a transistor having a gate that can be selectively opened and closed. - Alternatively, the programmable
resistor array R s 672 can be designed to have more than three or fewer than threeresistor paths 672A-672C, and/or eachresistor path 672A-672C can include more than or fewer than two resistors 676. - The shunt
capacitor array C s 674 is used to provide a wide tuning range of peaking corner frequency with a large tuning ratio of shunt capacitors. This wide tuning range is a desired feature since designers want to cover a variety of data rates. Moreover, lower data rate requires lower corner frequency. The design of the shuntcapacitor array C s 674 can be varied to achieve the desired level of tuning range of the peaking corner frequency. InFIG. 6 , the shuntcapacitor array C s 674 includes afirst capacitor path 674A, asecond capacitor path 674B, and athird capacitor path 674C; and thecapacitor paths 674A-672C are connected in parallel with each other. Eachcapacitor path 674A-674C can be individually controlled to provide a controlled amount of capacitance for the shuntcapacitor array C s 674. Moreover, eachcapacitor paths 674A-672C is connected in parallel with eachresistor path 672A-672C. - In one embodiment, each
capacitor path 674A-672C includes a pair ofvariable capacitors C capacitor switch 682, and a pair ofresistors R FIG. 6 , for eachcapacitor path 674A-672C, (i) the pair ofresistors R variable capacitors C resistors R serial capacitor switch 682 is closed. In one embodiment, thecapacitor switch 682 of eachcapacitor path 674A-674C can be individually controlled to selectively control the overall capacitance of the programmablecapacitor array C s 674. - Alternatively, the shunt
capacitor array C s 674 can be designed to have more than three or fewer than threecapacitor paths 674A-672C, and/or one or more of thecapacitor paths 674A-672C can have a different design than that illustrated inFIG. 6 . - In
FIG. 6 , a PA input signal 686 (PA In+, PA In−) is directed to the pair ofNMOS transistors T7 668A, T8 668. It should be noted that if the peakingamplifier 432 ofFIG. 6 is thefirst peaking amplifier 432A (illustrated inFIG. 4 ), that thePA input signal 686 is same at the VGA output signal 564 (illustrated inFIG. 5 ) from the variable gain amplifier 430 (illustrated inFIG. 4 ). Alternatively, if the peakingamplifier 432 ofFIG. 6 is a subsequent one of the cascading peakingamplifiers 432B-432E, thePA input signal 686 is the same as the PA output signal 687 from the previous one of the cascadingpeaking amplifiers 432A-432D. - As provided herein, the DC gain of the
PA input signal 686 is suppressed by degeneration by programmableresistor array R s 672, and, in high frequency, the gain is restored withvariable capacitors C resistors R - In
FIG. 6 , with this design of the peakingamplifier 432, the degenerationload resistors R NMOS transistors T7 668A,T8 668B control the peaking gain of the peakingamplifier 432. - Further, the programmable
resistor array R s 672, the shuntcapacitor array C s 674, and the transconductance (gm) of theNMOS transistors T7 668A, T8 668 together decide the peaking corner frequency of output signal from the peakingamplifier 432. Their relationship can be roughly represented by Equations 1-3. -
- In equations 1-3, (i) H(s) represents the transfer function in the Laplace domain, (ii) s represents a complex variable, (iii) Rs is the resistance of the
programmable resistor array 672, (iv) Cs is the capacitance of theprogrammable capacitor array 674, (v) Gm is the transconductance of theNMOS transistors T7 668A, T8 668, (vi) RL is the resistance of theload resistors load resistors - From Equations 1-3, it is straight forward to determine the following conclusions: (i) the peaking gain can be adjusted by changing the resistance of the programmable
resistor array R s 672; (ii) the peaking corner frequency can be adjusted by changing the capacitance of the shuntcapacitor array C s 674; and (iii) the peaking gain can be disabled by disconnecting the shuntcapacitor array C s 674. Moreover, these equations show how to keep the peaking gain and the peaking corner frequency stable during changes in PVT. Semiconductor devices are subject to many variations such as manufacturing skew corners, temperature and voltage supply. These three dominant factors are also known as PVT variation. All these factors contribute to the change of the performance of the equalization amplifier. By stabilizing and correlating the value of transconductance Gm to resistor value, the stabilization of the peaking gain and the corner frequency can be achieved. Thus, the present invention is effective in removing the inter-symbol interference across different corner, temperature and voltage supply conditions. Moreover, the present invention is provides superior common mode rejection. - As provided herein, the peaking gain from each
individual peaking amplifier 432 can be adjusted by changing the value of programmableresistor array R s 672 and value of the shuntcapacitor array C s 674. Therefore, by tweaking the value of programmableresistor array R s 672 and value of the shuntcapacitor array C s 674 for eachindividual peaking amplifier 432, eachindividual peaking amplifier 432 can be used to make a relatively small, step-wise controllable adjustment in gain. However, with the use of the cascading ofmultiple peaking amplifiers 432A-432E (illustrated inFIG. 4 ), the step-wise gains are summed, and the overall gain of theequalization system 18 can be controlled to obtain a relatively large total gain (e.g. total 24 dB gain) at a controlled small step, to best fit different channel loss in thecommunication system 10. - As non-exclusive examples, each peaking
amplifier 432A-432E can be used to make a step-wise gain of at least approximately 1, 2, 3, 4, 5, or 6 dB. With these non-exclusive examples, with five cascadingpeaking amplifiers 432A-432E, the system can make an adjustment in gain of at least approximately 5, 10, 15, 20, 25, or 30 dB. It should be noted that these adjustments can be made in any step wise increment smaller or larger than the examples provided herein. - In one embodiment, the
variable capacitors C gate node 688A and itsbulk node 688B across a wide voltage range. The location of thegate node 688A and thebulk node 688A of one of thevariable capacitors C FIG. 6 - A non-exclusive example of a suitable
variable capacitor C capacitor path 674A-672B has a capacitance that varies between one Pico farad and ten Pico farad. -
FIG. 7 is a graph that illustrates capacitance-bias voltage (“C-V”)curve 790 for one embodiment of a varactor that can be used in thevariable capacitors C FIG. 6 . As illustrated inFIG. 7 , the capacitance of the varactor increases as the bias voltage applied across the gate and bulk nodes of the varactor increases. Further, inFIG. 7 , theC-V curve 790 includes a first zone 792 (illustrated with dashed box) and a second zone 794 (illustrated with dashed box) in which the capacitance of the varactor is fairly constant with its bias voltage. Moreover, the capacitance is not fairly constant between the twozones first zone 792, thesecond zone 794, or somewhere therebetween. When the varactor is controlled to be in thefirst zone 792 it has a relatively high capacitance; and when the varactor is controlled to be in thesecond zone 794 it has a relatively low capacitance. With this design, the bias voltage applied to the varactors can be used to control the capacitance of thevariable capacitors C - Referring back to
FIG. 6 , with the present invention, the peakingamplifier 432 adjusts the peaking corner frequency by changing value of the shuntcapacitor array C s 674. As provided herein, this feature can be realized with doing two adjustments at the same time to eachindividual capacitor path 674A-674C. One adjustment is turning on/off (opening/closing) thecapacitor switch 682 that in series with thevariable capacitors C individual capacitor path 674A-674C. The other is to change a bias voltage applied to thevariable capacitors C individual capacitor path 674A-674C. InFIG. 6 , (i) a first bias voltage C_0 can be selectively applied (by a first bias voltage source to the area between theresistors R first capacitor path 674A) to thevariable capacitors C first capacitor path 674A, (ii) a second bias voltage C_1 can be selectively applied (by a second bias voltage source to the area between theresistors R second capacitor path 674B) to thevariable capacitors C second capacitor path 674B, and (iii) a third bias voltage C_2 can be selectively applied (by a third bias voltage source to the area between theresistors R third capacitor path 674C) to thevariable capacitors C third capacitor path 674C. Doing these two adjustments at the same time can minimize the impact from the parasitic capacitance from thecapacitor switch 682 in series with thevariable capacitors C capacitor array C s 674. - For each
individual capacitor path 674A-674C, by selectively connecting/disconnecting theserial capacitor switch 682, thevariable capacitors C resistor array R s 672 or disconnected. Further, for eachindividual capacitor path variable capacitors C resistors R serial capacitor switch 682 is closed. - By changing the bias voltage, the capacitance value of the
variable capacitors C FIG. 7 ). Thus, by changing the bias voltage at C_0, C_1, C_2, the capacitance value for eachindividual capacitor path 674A-674C can be individually tuned and adjusted. - A
suitable capacitor switch 682 can be a transistor having a gate that can be selectively opened and closed. Further, theparasitic cap 689 of thecapacitor switch 682 is also illustrated inFIG. 6 . - In one embodiment, for each
capacitor path 674A-674C, (i) when the respective bias voltage (C_0, C_1, C_2) is at ground, and when the capacitor switch 683 is closed, the varactor has a relatively high capacitance, and (ii) when, the respective bias voltage (C_0, C_1, C_2) is not at ground, and when the capacitor switch 683 is open, the varactor has a relatively low capacitance. This provides high tuning range for thecapacitor paths 674A-674C that can be individually tuned by selectively controlling the capacitor switch 683 and the bias voltage (C_0, C_1, C_2) for eachcapacitor path 674A-674C. - As provided herein, the
resistors R individual capacitor path 674A-674C is used to block the signal path from thevariable capacitors C variable capacitors C amplifier 432. A non-exclusive example of asuitable resistor R capacitor path 674A-672B has a resistance of between approximately five and twenty kilo ohms. - In
FIG. 6 , the PA output signal 687 (PA Out+, PA Out−) is taken between theNMOS transistors T7 668A, T8 668 and theload resistors R - Additionally, in the embodiment illustrated in
FIG. 6 , the peakingamplifier 432 receives a PTAT bias current IBIAS from the PTAT bias generator 434 (illustrated inFIG. 6 ). As provided above, thePTAT bias generator 434 is electrically connected to each of the peakingamplifiers 432 and is used to bias theNMOS transistors T7 668A, T8 668 of each of the peakingamplifiers 432. In certain embodiments, thePTAT bias generator 434 is designed to provide a PTAT biasing current having a value that increases proportionally with temperature. With this design, the PTAT bias current IBIAS can be used to maintain the transconductance Gm of theNMOS transistors T7 668A, T8 668 substantially constant as temperature changes. This feature reduces the influence of temperature on each peakingamplifier 432. -
FIG. 8 is a simplified schematic that illustrates the components of one, non-exclusive embodiment a suitable thePTAT bias generator 434. InFIG. 8 , thePTAT bias generator 434 generates a reference bias current IBIAS that is proportional to temperature, inversely proportional to RBIAS, and does not change with the power supply. With the help of PTAT bias current IBIAS, the value of the transconductance Gm of theNMOS transistors T7 668A, T8 668 of the peakingamplifiers 432 is kept approximately constant with temperature change. -
FIG. 9 is a graph that illustrates two alternative common mode gain curves, namely a first common mode gain curve 996 (illustrated with a long dashed line and circles), and a second common mode gain curve 997 (illustrated with a solid line). As discussed above and illustrated inFIG. 6 , theresistors R individual capacitor path 674A-674C are used to block the signal path from thevariable capacitors C variable capacitors C amplifier 432. - Referring back to
FIG. 9 , (i) the first commonmode gain curve 996 represents the results from a peaking amplifier (not shown) that does not use theresistors R capacitor paths 674A-674C; and (ii) the second commonmode gain curve 997 represents the results from a peaking amplifier 432 (illustrated inFIG. 6 ) that usesresistors R capacitor paths 674A-674. It should be noted that the first commonmode gain curve 996 has an undesirable peaking higher frequency, while the second commonmode gain curve 997 does not have the peaking higher frequency. Thus, theresistors R amplifier 432. -
FIG. 10 illustrates a constant biasing current curve 1098 (illustrated with a long dashed line and circles) and a PTAT biasing current curve 1099 (illustrated with a solid line) that can be generated by thePTAT bias generator 434 illustrated inFIG. 8 . With the constant biasingcurrent curve 1098, the transconductance Gm varies greatly as temperature changes. In contrast, with the PTAT biasingcurrent curve 1099, the transconductance Gm is substantially constant (varies less than approximately plus or minus five or ten percent over the operational temperature range of the system) as temperature changes. In certain non-exclusive embodiments, from simulation, it has been proven that using the PTAT biasingcurrent curve 1099 for the peakingamplifiers 432 can reduce the gain variation from plus or minus forty percent to plus or minus ten percent (+/−40% to +/−10%). This significant improvement mainly comes from the stabilized performance over different temperatures. - While the particular invention as herein shown and disclosed in detail are fully capable of obtaining the objectives and providing the advantages herein before stated, it is to be understood that they are merely illustrative of one or more embodiments and that no limitations are intended to the details of construction or design herein shown other than as described in the appended claims.
Claims (23)
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