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Publication numberUS20120001646 A1
Publication typeApplication
Application numberUS 13/173,621
Publication dateJan 5, 2012
Filing dateJun 30, 2011
Priority dateJun 30, 2010
Also published asCN103080739A, EP2588850A1, EP2588850A4, WO2012003359A1
Publication number13173621, 173621, US 2012/0001646 A1, US 2012/001646 A1, US 20120001646 A1, US 20120001646A1, US 2012001646 A1, US 2012001646A1, US-A1-20120001646, US-A1-2012001646, US2012/0001646A1, US2012/001646A1, US20120001646 A1, US20120001646A1, US2012001646 A1, US2012001646A1
InventorsJarie Bolander, Keith FIFE, Mark Milgrew
Original AssigneeLife Technologies Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Methods and apparatus for testing isfet arrays
US 20120001646 A1
Abstract
The invention provides testing of a chemically-sensitive transistor device, such as an ISFET device, without exposing the device to liquids. In one embodiment, the invention performs a first test to calculate a resistance of the transistor. Based on the resistance, the invention performs a second test to transition the testing transistor among a plurality of modes. Based on corresponding measurements, a floating gate voltage is then calculated with little or no circuitry overhead. In another embodiment, the parasitic capacitance of at least either the source or drain is used to bias the floating gate of an ISFET. A driving voltage and biasing current are applied to exploit the parasitic capacitance to test the functionality of the transistor.
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Claims(32)
1. A method of testing a chemical detecting device comprised of an array of pixel elements, each pixel element including a chemically-sensitive transistor having a source terminal, a drain terminal, and a floating gate terminal, the method comprising:
connecting of a group of the chemically-sensitive transistors' source terminals in common;
applying first test voltages at the source terminals of the group;
measuring corresponding first currents at the drain terminals produced by the first test voltages;
calculating resistance values based on the first test voltages and currents;
applying second test voltages at the source terminals of the group to operate the group in a different operational mode, wherein the second test voltages are based at least partially on the resistance values;
measuring a corresponding second set of currents at the drain terminals produced by the second test voltages; and
based on the second test voltages and currents and operational properties of the chemically-sensitive transistors, calculating a floating gate voltage of each chemically-sensitive transistor in the group.
2. The method of claim 1, wherein each chemically-sensitive transistor is an Ion Sensitive Field Effect Transistor (ISFET).
3. The method of claim 1, wherein the group comprises all of the chemically-sensitive transistors in the array.
4. The method of claim 1, wherein the group comprises alternate rows of the array.
5. The method of claim 1, wherein the group comprises alternate columns of the array.
6. The method of claim 1, wherein the first test voltages are applied at different sides of the array sequentially.
7. The method of claim 1, further comprising applying test currents with the second test voltages.
8. The method of claim 1, wherein the second test voltages are applied at different sides of the array sequentially, and wherein the floating gate voltage is calculated in relation to each side of the array.
9. The method of claim 8, wherein the calculated floating gate voltages are averaged together for all sides.
10. The method of claim 2, wherein there is no fluid sample in contact with or adjacent to any floating gate terminal in the array.
11. The method of claim 1, wherein the different operational mode of the chemically sensitive transistors includes one of triode mode and saturation mode.
12. A method of dry testing an array of chemically-sensitive transistors having a source, a drain, and a floating gate, the method comprising:
applying first test voltages to a common source connected group of the chemically-sensitive transistors;
calculating a resistance based on the first test voltages and currents produced by the first set of test voltages;
applying second test voltages, wherein the second test voltages drive the chemically-sensitive transistors to transition among a plurality of operational modes and wherein the second test voltages are based partially on the calculated resistance;
calculating a floating gate voltage of each driven chemically-sensitive transistor; and
determining if each calculated floating gate voltage is within a predetermined threshold.
13. The method of claim 12, wherein the chemically-sensitive transistor is an ISFET.
14. The method of claim 12, wherein the common source connected group is the entire array.
15. The method of claim 12, wherein the common source connected group comprises alternate rows of the array.
16. The method of claim 12, wherein the common source connected group comprises alternate columns of the array.
17. The method of claim 12, wherein the plurality of operational modes include triode mode and saturation mode.
18. A device, comprising:
an array of chemical detection elements, each element including:
a chemically-sensitive field effect transistor having a semiconductor body terminal, a source terminal, a drain terminal, and a floating gate terminal; and
a testing circuit including:
a plurality of driving voltage terminals at each side of the array, the plurality of driving voltage terminals coupled to a plurality of source terminals and a plurality of body terminals;
a current source coupled to the drain terminal of at least one element in the array to measure a drain current by converting the drain current into corresponding voltage measurements.
19. The device of claim 18, wherein the chemically-sensitive transistor is an ISFET.
20. The device of claim 18, wherein the testing circuit is configured to drive the chemically-sensitive field effect transistors to operate in different modes.
21. The device of claim 20, wherein the different modes include triode mode and saturation mode.
22. A method of testing a transistor having a floating gate and an overlap capacitance between the floating gate and at least one of a first and a second terminal, the method comprising:
applying a test voltage to the first terminal of the transistor;
biasing a second terminal of the transistor;
measuring an output voltage at the second terminal; and
determining if the output voltage is within a predetermined range;
wherein the test voltage via the overlap capacitance places the transistor into an active mode.
23. The method of claim 22, wherein the transistor is an ISFET.
24. The method of claim 22, wherein the first terminal is a drain terminal and the second terminal is a source terminal.
25. The method of claim 22, further comprising:
adjusting the test voltage to another voltage value;
applying the adjusted test voltage to the first terminal;
measuring a second output voltage at the second terminal; and
determining a transistor property based on the output voltages.
26. The method of claim 25, wherein the transistor property is a transistor gain.
27. The method of claim 22, wherein the overlap capacitance is formed by a gate oxide layer material that partially overlaps a terminal implant of the transistor.
28. The method of claim 23, wherein there is no fluid sample in contact with or adjacent to the floating gate terminal.
29. A device, comprising:
an array of detection elements, each element including:
a field effect transistor having a floating gate, a first terminal, a second terminal, and an overlap capacitance between the floating gate and at least one of the first and second terminals; and
a testing circuit including:
a driving voltage terminal coupled to at least one first terminal,
a biasing current terminal coupled to at least one second terminal, and
an output voltage measurement terminal coupled to the at least one second terminal.
30. The device of claim 29, wherein each field effect transistor is an ISFET.
31. The device of claim 29, wherein the first terminal of each field effect transistor is a drain terminal and the second terminal of each field effect transistor is a source terminal.
32. The device of claim 29, wherein the overlap capacitance is formed by a gate oxide layer material that partially overlaps a terminal implant of the transistor.
Description
RELATED APPLICATIONS

This application claims benefit of priority from U.S. provisional application Ser. No. 61/360,493 filed Jun. 30, 2010 and U.S. provisional application Ser. No. 61/360,495 filed Jul. 1, 2010, the disclosures of all of which are incorporated herein by reference in their entirety.

BACKGROUND

Electronic devices and components have found numerous applications in chemistry and biology (more generally, “life sciences”), especially for detection and measurement of various chemical and biological reactions and identification, detection and measurement of various compounds. One such electronic device is referred to as an ion-sensitive field effect transistor, often denoted in the relevant literature as an “ISFET” (or pHFET). ISFETs conventionally have been explored, primarily in the academic and research community, to facilitate measurement of the hydrogen ion concentration of a solution (commonly denoted as “pH”).

More specifically, an ISFET is an impedance transformation device that operates in a manner similar to that of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and is particularly configured to selectively measure ion activity in a solution (e.g., hydrogen ions in the solution are the “analytes”). A detailed theory of operation of an ISFET is given in “Thirty years of ISFETOLOGY: what happened in the past 30 years and what may happen in the next 30 years,” P. Bergveld, Sens. Actuators, 88 (2003), pp. 1-20 (“Bergveld”), which publication is hereby incorporated herein by reference in its entirety.

Details of fabricating an ISFET using a conventional CMOS (Complementary Metal Oxide Semiconductor) process may be found in Rothberg, et al., U.S. Patent Publication No. 2010/0301398, Rothberg, et al., U.S. Patent Publication No. 2010/0282617, and Rothberg et al, U.S. Patent Publication 2009/0026082; these patent publications are collectively referred to as “Rothberg”, and are all incorporated herein by reference in their entirety. In addition to CMOS, however, biCMOS (i.e., bipolar and CMOS) processing may also be used, such as a process that would include a PMOS FET array with bipolar structures on the periphery. Alternatively, other technologies may be employed wherein a sensing element can be made with a three-terminal devices in which a sensed ion leads to the development of a signal that controls one of the three terminals; such technologies may also include, for example, GaAs and carbon nanotube technologies.

Taking a CMOS example, a P-type ISFET fabrication is based on a p-type silicon substrate, in which an n-type well forming a transistor “body” is formed. Highly doped p-type (p+) regions S and D, constituting a source and a drain of the ISFET, are formed within the n-type well. A highly doped n-type (n+) region B may also be formed within the n-type well to provide a conductive body (or “bulk”) connection to the n-type well. An oxide layer may be disposed above the source, drain and body connection regions, through which openings are made to provide electrical connections (via electrical conductors) to these regions. A polysilicon gate may be formed above the oxide layer at a location above a region of the n-type well, between the source and the drain. Because it is disposed between the polysilicon gate and the transistor body (i.e., the n-type well), the oxide layer often is referred to as the “gate oxide.”

Like a MOSFET, the operation of an ISFET is based on the modulation of charge concentration (and thus channel conductance) caused by a MOS (Metal-Oxide-Semiconductor) capacitance. This capacitance is constituted by a polysilicon gate, a gate oxide and a region of the well (e.g., n-type well) between the source and the drain. When a negative voltage is applied across the gate and source regions, a channel is created at the interface of the region and the gate oxide by depleting this area of electrons. For an n-well, the channel would be a p-channel (and vice-versa). In the case of an n-well, the p-channel would extend between the source and the drain, and electric current is conducted through the p-channel when the gate-source potential is negative enough to attract holes from the source into the channel. The gate-source potential at which the channel begins to conduct current is referred to as the transistor's threshold voltage VTH (the transistor conducts when VGS has an absolute value greater than the threshold voltage VTH). The source is so named because it is the source of the charge carriers (holes for a p-channel) that flow through the channel; similarly, the drain is where the charge carriers leave the channel.

As described in Rothberg, an ISFET may be fabricated with a floating gate structure, formed by coupling a polysilicon gate to multiple metal layers disposed within one or more additional oxide layers disposed above the gate oxide. The floating gate structure is so named because it is electrically isolated from other conductors associated with the ISFET; namely, it is sandwiched between the gate oxide and a passivation layer that is disposed over a metal layer (e.g., top metal layer) of the floating gate.

As further described in Rothberg, the ISFET passivation layer constitutes an ion-sensitive membrane that gives rise to the ion-sensitivity of the device. The presence of analytes such as ions in an analyte solution (i.e., a solution containing analytes (including ions) of interest or being tested for the presence of analytes of interest), in contact with the passivation layer, particularly in a sensitive area that may lie above the floating gate structure, alters the electrical characteristics of the ISFET so as to modulate a current flowing through the channel between the source and the drain of the ISFET. The passivation layer may comprise any one of a variety of different materials to facilitate sensitivity to particular ions; for example, passivation layers comprising silicon nitride or silicon oxynitride, as well as metal oxides such as silicon, aluminum or tantalum oxides, generally provide sensitivity to hydrogen ion concentration (pH) in an analyte solution, whereas passivation layers comprising polyvinyl chloride containing valinomycin provide sensitivity to potassium ion concentration in an analyte solution. Materials suitable for passivation layers and sensitive to other ions such as sodium, silver, iron, bromine, iodine, calcium, and nitrate, for example, are known, and passivation layers may comprise various materials (e.g., metal oxides, metal nitrides, metal oxynitrides). Regarding the chemical reactions at the analyte solution/passivation layer interface, the surface of a given material employed for the passivation layer of the ISFET may include chemical groups that may donate protons to or accept protons from the analyte solution, leaving at any given time negatively charged, positively charged, and neutral sites on the surface of the passivation layer at the interface with the analyte solution.

With respect to ion sensitivity, an electric potential difference, commonly referred to as a “surface potential,” arises at the solid/liquid interface of the passivation layer and the analyte solution as a function of the ion concentration in the sensitive area due to a chemical reaction (e.g., usually involving the dissociation of oxide surface groups by the ions in the analyte solution in proximity to the sensitive area). This surface potential in turn affects the threshold voltage of the ISFET; thus, it is the threshold voltage of the ISFET that varies with changes in ion concentration in the analyte solution in proximity to the sensitive area. As described in Rothberg, since the threshold voltage VTH of the ISFET is sensitive to ion concentration, the source voltage Vs provides a signal that is directly related to the ion concentration in the analyte solution in proximity to the sensitive area of the ISFET.

Arrays of chemically-sensitive FETs (“chemFETs”), or more specifically ISFETs, may be used for monitoring reactions—including, for example, nucleic acid (e.g., DNA) sequencing reactions, based on monitoring analytes present, generated or used during a reaction. More generally, arrays including large arrays of chemFETs may be employed to detect and measure static and/or dynamic amounts or concentrations of a variety of analytes (e.g., hydrogen ions, other ions, non-ionic molecules or compounds, etc.) in a variety of chemical and/or biological processes (e.g., biological or chemical reactions, cell or tissue cultures or monitoring, neural activity, nucleic acid sequencing, etc.) in which valuable information may be obtained based on such analyte measurements. Such chemFET arrays may be employed in methods that detect analytes and/or methods that monitor biological or chemical processes via changes in charge at the chemFET surface. Such use of ChemFET (or ISFET) arrays involves detection of analytes in solution and/or detection of change in charge bound to the chemFET surface (e.g. ISFET passivation layer).

Research concerning ISFET array fabrication is reported in the publications “A large transistor-based sensor array chip for direct extracellular imaging,” M. J. Milgrew, M. O. Riehle, and D. R. S. Cumming, Sensors and Actuators, B: Chemical, 111-112, (2005), pp. 347-353, and “The development of scalable sensor arrays using standard CMOS technology,” M. J. Milgrew, P. A. Hammond, and D. R. S. Cumming, Sensors and Actuators, B: Chemical, 103, (2004), pp. 37-42, which publications are incorporated herein by reference and collectively referred to hereafter as “Milgrew et al.” Descriptions of fabricating and using ChemFET or ISFET arrays for chemical detection, including detection of ions in connection with DNA sequencing, are contained in Rothberg. More specifically, Rothberg describes using a chemFET array (in particular ISFETs) for sequencing a nucleic acid involving incorporating known nucleotides into a plurality of identical nucleic acids in a reaction chamber in contact with or capacitively coupled to chemFET, wherein the nucleic acids are bound to a single bead in the reaction chamber, and detecting a signal at the chemFET, wherein detection of the signal indicates release of one or more hydrogen ions resulting from incorporation of the known nucleotide triphosphate into the synthesized nucleic acid.

Prior techniques for testing a chemically-sensitive transistor based array, such as an ion-sensitive field effect transistor (ISFET) array, included “wet testing.” An ISFET array is sensitive to changes in chemical composition in a fluid. Accordingly, ISFET arrays were commonly tested by flowing one or more liquids over the array (e.g. liquids having different pH values), reading out the response for each ISFET element in the array, and determining whether the element is operating properly. Although wet testing has the benefit of testing an ISFET under intended operational conditions, wet testing is considered impractical in most circumstances.

In particular, wet testing is cumbersome and impractical for high volume manufacturing. Also, wet testing exposes the device to fluids that may cause corrosion and prevent the device from being fully dried before normal operations. Moreover, exposure of the device to liquids may create defects in the device or future contamination. For these reasons, once a device is exposed to fluids, a manufacturer will typically not accept the device.

Accordingly, there is a need in the art for dry testing a chemically-sensitive transistor based device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a cross section of an ion-sensitive field effect transistor (ISFET).

FIG. 2 illustrates a block diagram of an element array.

FIG. 3 illustrates a simplified flow diagram for testing an element array.

FIG. 4 illustrates an example of a 2-T pixel array.

FIG. 5 illustrates an example of a 3-T pixel.

FIG. 6 illustrates a cross section of a floating gate terminal transistor.

FIG. 7 illustrates a circuit schematic equivalent to a floating gate terminal transistor.

FIG. 8 illustrates a circuit schematic equivalent to a floating gate terminal transistor during a testing phase.

DETAILED DESCRIPTION

Embodiments of the present invention provide a method of testing a chemical a chemical detecting device comprised of an array of pixel elements where each pixel element includes a chemically-sensitive transistor having a source terminal, a drain terminal, and a floating gate terminal. The method may include connecting of a group of the chemically-sensitive transistors' source terminals in common, applying first test voltages at the source terminals of the group, measuring corresponding first currents at the drain terminals produced by the first test voltages, and calculating resistance values based on the first test voltages and currents. The method may also include applying second test voltages at the source terminals of the group to operate the group in a different operational mode, wherein the second test voltages are based at least partially on the resistance values, and measuring a corresponding second set of currents at the drain terminals produced by the second test voltages. Based on the second test voltages and currents and operational properties of the chemically-sensitive transistors, calculating a floating gate voltage of each chemically-sensitive transistor in the group.

Embodiments of the present invention provide a method of dry testing an array of chemically-sensitive transistors having a source, a drain, and a floating gate. The method may include applying first test voltages to a common source connected group of the chemically-sensitive transistors; calculating a resistance based on the first test voltages and currents produced by the first set of test voltages; applying second test voltages, where the second test voltages drive the chemically-sensitive transistors to transition among a plurality of operational modes and where the second test voltages are based partially on the calculated resistance; calculating a floating gate voltage of each driven chemically-sensitive transistor; and determining if each calculated floating gate voltage is within a predetermined threshold.

Embodiments of the present invention provide a device including an array of chemical detection elements and a testing circuit. Each element may include a chemically-sensitive field effect transistor having a semiconductor body terminal, a source terminal, a drain terminal, and a floating gate terminal. The testing circuit may include a plurality of driving voltage terminals at each side of the array where the plurality of driving voltage terminals coupled to a plurality of source terminals and a plurality of body terminals, and a current source coupled to the drain terminal of at least one element in the array to measure a drain current by converting the drain current into corresponding voltage measurements.

Embodiments of the present invention provide a method of testing a transistor having a floating gate and an overlap capacitance between the floating gate and at least one of a first and a second terminal. The method may include applying a test voltage to the first terminal of the transistor, biasing a second terminal of the transistor, measuring an output voltage at the second terminal, and determining if the output voltage is within a predetermined range. The test voltage via the overlap capacitance may place the transistor into an active mode.

Embodiments of the present invention provide a device including an array of detection elements and a test circuit. Each element may include a field effect transistor having a floating gate, a first terminal, a second terminal, and an overlap capacitance between the floating gate and at least one of the first and second terminals. The testing circuit may include a driving voltage terminal coupled to at least one first terminal, a biasing current terminal coupled to at least one second terminal, and an output voltage measurement terminal coupled to the at least one second terminal.

Embodiments of the present invention relate to a system and method for testing ion-sensing devices such as an ISFET device. Typically, ISFETs sense changes in the chemical composition in micro-wells that are formed above the ISFET. Such chemical changes may be caused by chemical reaction in fluids contained in the micro-wells. FIG. 1 is a simplified diagram of an ISFET 100. ISFET 100 is illustrated as an NMOS device; however, a PMOS device may also be used in aspects of the present invention. In this embodiment, the ISFET 100 is a semiconductor device with four terminals. The four terminals are a gate terminal 110, a drain terminal 120, a source terminal 130, and a body terminal 140. The gate terminal 110 may be a floating gate.

The ISFET 100 may include a floating gate with a micro-well above the floating gate. This micro-well may contain an oxide (or other materials) with surface sites that cause a specific ion species to bind, inducing a change in charge distribution, and causing a change in potential at the surface. This change in surface potential may then be detected by the ISFET and measured by a read circuit, and represents the amount of ions contained within the micro-well. It is in this way that each ISFET in an array (e.g., ISFET element array 210 of FIG. 2) can be used to detect local variations in ion concentration of a sample liquid that is presented over the array.

The ISFET 100 may operate similar to a standard MOSFET device and may transition among a few operational regions. When the ISFET 100 is biased such that VGS−Vth is positive and greater than VDS, the transistor is in the triode region, which is also commonly referred to as the linear region. In the triode region, the current through the drain terminal 120, ID, may be defined as:

I D = μ n C ox W L ( ( V GS - V th ) V DS - V DS 2 2 ) Triode Region Equation

where μn is a charge-carrier effective mobility coefficient, Cox is a gate oxide capacitance per unit area coefficient, W is a gate width, L is a gate length, VGS is a voltage between the gate and source terminals, Vth is the threshold voltage, and VDS is the voltage between the drain and source terminals. In the triode region, the transistor has ohmic behavior between the drain and source and the drain current does not saturate.

When VGS−Vth is positive and less than VDS, the ISFET 100 operates in the saturation region, which is also commonly referred to as the active region. In the saturation region, the current through the drain terminal 120, ID, may be defined as:

I D = μ n C ox 2 W L ( V GS - V th ) 2 ( 1 + λ V DS ) Saturation Region Equation

where μn is the charge-carrier effective mobility coefficient, Cox is the gate oxide capacitance per unit area coefficient, W is the gate width, L is the gate length, VGS is the voltage between the gate and source terminals, Vth is the threshold voltage, VDS is the voltage between the drain and source terminals, and λ the factor for channel length modulation.

The ISFET 100 also has a threshold voltage dependent on the bulk potential. The bulk potential is referred to as the body voltage at terminal 140 and may operate as a second gate. The body effect may be defined as:


V TN =V TO+γ(√{square root over (V SB+2φ)}−√{square root over (2φ)})  Body Effect Equation

where VTN is a threshold voltage with substrate bias present, VTO is a zero-VSB value of threshold voltage, VSB is a voltage between the source and body terminals, γ is a body effect parameter, and 2φ is a surface potential parameter.

The ISFET 100 may be placed in a pixel element, and the pixel element may be a part of an array. FIG. 2 illustrates a device 200 with an ISFET element array 210. Each element in the array 210 may include an ISFET as described above in FIG. 1 and may also include other transistors and electrical components. The array 210 may be arranged as a plurality of rows and columns. The array 210 may also have ISFET terminal connections at both ends of the columns and both sides of the rows, and, thus, may have ISFET terminal connections at each of the four edges of the array 210. The body connection may be set to a bias voltage. For example, each edge may have source connections of the ISFET in the array 210 as described below.

The array 210 is typically large and thus the source resistance along the array may vary by the inherent resistance of the transistor well and connection to the source. In an embodiment of the present invention, the ISFET array 210 may be tested by strategically placing body and source connections access at different physical locations around the array. Resistance of the source connections may then be calibrated to determine an accurate representation of the desired floating gate voltage.

FIG. 3 illustrates a simplified flow diagram of a method 300 to test an ISFET array, without the presence of fluids in contact with or adjacent to the array, according to an embodiment of the present invention. Initially, the device may be entered into a test mode where the device circuitry may connect the sources of all the ISFETs in common (i.e., all of the ISFET sources are connected together) (Step 310). In another embodiment, the array circuitry may connect the sources of alternate rows or columns in common (e.g., the sources of odd numbered rows connected together and the sources of even numbered rows connected together). The alternate rows or column arrangement may be a structural array testing technique to allow the test procedure to test the integrity of the arrays of the rows and columns. For example, the presence of column defects (e.g., two columns are shorted together due to a manufacturing defect) may be tested by driving odd columns (but not even columns) high (e.g. by applying a voltage) and measuring the even columns to see whether the even columns stay low. If an even column measures high, this identifies a defective column. For row testing, one row may be driven and the other side of the row may measured to ensure that the signal passes across the array. Thus, structural array testing may test the connectivity of rows and columns in the array. In addition to connecting the sources of ISFETs in the array as desired, other or similar connections to drains of the ISFETs may also be established.

After the source connections are made, a first test may be performed (Step 320). In the first test, first test voltages may be forced (applied) through the array. The first test voltages may be applied at multiple sides of the device such as either end of the columns or either side of the rows in the array. For example, the first test voltages may be applied to each of the sides sequentially. The first test voltages may be applied to the body and source terminals of the connected ISFETs. The first test voltages may include an initial voltage sweep to identify a suitable operating (or bias) voltage to test the pixel array.

First test measurements corresponding to the first test may then be obtained (Step 330). The first test voltages may produce corresponding currents through each connected ISFET. The produced currents may then be measured. A range of different voltage and current measurements may be provided in the embodiments of the present invention. For example, source and drain voltages may be forced while setting the body to a bias voltage of either an analog supply voltage or analog ground (depending on whether the ISFET is a PMOS or NMOS device). The resultant drain current may then be measured by a current source converting the measured current into a corresponding voltage value. In another example, the body, in principle, may be set to a voltage between the analog supply voltage and analog ground. Further, all body terminals may be set to the same voltage in an ISFET array and, thus, all the ISFETS in the array may be similarly biased. Another test may characterize threshold voltage mismatches across the array.

Based on the first test voltage values and the corresponding measured currents, a resistance value for the source connections may be calculated (Step 340). For example, a resistance gradient for the source connections may be calculated showing the resistance relationship of the test voltages and measured currents.

After calculating a resistance value for the source connections, body and source connections relative to one side of the device (e.g., one end of the columns) may be established. A second test may then be performed (Step 350). In the second test, second test voltages and currents may be forced or applied through the array. The second test voltages may be a voltage sweep at different operating (or bias) voltage points. Hence, the body connection, which is a bias voltage, may be set accordingly. The second test voltages and currents may be a sweep of a range of voltages that will operate the ISFETs in a different operational mode as described above, such as triode mode and saturation mode. Further, the ISFETs may be operated in body effect mode by using the body terminal as a second gate.

Second test measurements corresponding to the second test may then be obtained (Step 360). In each iteration of forcing or applying the second test voltages and currents, different currents and voltages as seen on the array may be measured. For example, source and drain voltages may be forced while the body voltage ranges between the analog supply voltage and analog ground voltage. The produced drain currents may be measured by a current source that may convert the current into corresponding voltage values. Based on the forced and measured voltages and currents, the gate voltage of the ISFETs may be calculated (Step 370). Specifically, the operational equations of the different modes described above may be used to calculate the gate voltage based on the forced and measured voltages and currents. Thus, the gate voltage for each ISFET element may be calculated to determine if the ISFET is working properly.

In an embodiment, steps 350-370 may be repeated for one or more other sides of the device (such as, e.g., the opposite end of the column). In another embodiment, steps 350-370 may be repeated after increasing or decreasing the forced voltages and currents by a factor of, for example, two. The gate voltage may then be calculated from the adjusted voltage (the bias point). The increased or decreased iteration may also be repeated for one or more other sides of the device. Also, the increasing or decreasing iteration may be repeated multiple times, each time in which the forced voltages and currents are adjusted by some factor with each iteration. After all iterations are complete, the calculated gate voltages may be averaged together to obtain a more accurate representation of the ISFET gate voltage. The averaged gate voltage may then be compared to a desired threshold range to determine if each ISFET is working properly. Further, the location (e.g., X and Y column and row in the array), values for each ISFET gate voltage, and/or the working condition of each ISFET may be recorded in a register, for example. Additional circuitry may be provided to allow for programming and/or erasing of each pixel element where the floating gate voltage of each ISFET may be programmed and/or erased. In some embodiments, the program/erase capability may provide a higher level of fault detection coverage. However, the program/erase circuitry may operate on a higher voltage than other circuit components, and design techniques to isolate higher voltage circuits may need to be applied to ensure circuit components are not damaged.

In another embodiment, in addition to voltage and current, the temperature of the device may also be varied to modulate the threshold voltage of the ISFET element. By varying the temperature, alternate data points may be observed and used to calculate the gate voltage of the ISFET element.

Further, the circuitry for individual pixel elements may take a variety of different forms. FIG. 4 illustrates a two-transistor (2-T) pixel array 400 showing 4 pixel elements that may be used in aspects of the present invention. The pixel array 400 may include a plurality of pixel elements 401.1-401.n. Each pixel element 401 may include an ISFET 410 and another transistor 420. In a 2-T pixel embodiment, the array may be tested by controlling and/or measuring all nodes except the floating gate terminal of the ISFET.

FIG. 5 illustrates a three-transistor (3-T) pixel element 500 that may be used in aspects of the present invention. The pixel element 500 may include an ISFET 510, and two other transistors 520, 530. In a 3-T pixel embodiment, the array may be tested by controlling and/or measuring all nodes except the floating gate terminal of the ISFET. The I-Sink may be a controllable current source to provide a constant current to the ISFET. In this embodiment, the I Sink capability adds another measurement point that may be used to more accurately calculate the gate voltage. Other variations of the pixel circuitry may be used with the embodiments of the present invention.

The dry testing embodiments of the present invention described above exploit the characteristics of a floating gate transistor to test the functionality of the floating gate transistor. Therefore, the operation of the device can be tested with little to no circuit overhead, and the array size can be optimized because additional test circuitry is not required in the array area. Moreover, embodiments of the present invention do not require liquid to fully test the array; therefore, possible contamination is avoided.

Although aspects of the present invention have been described in which an ISFET array may be tested without the use of liquids, aspects of the present invention may be employed in conjunction with the use of liquids for testing purposes. For example, liquids having a known pH may be applied before, during, or after the dry testing techniques described herein. Thus, dry testing techniques described herein may be used together with wet testing techniques, if desired.

Moreover, different embodiments of the present invention herein have been described using an ISFET. However, the present invention is not limited to ISFETs and may be applicable to other suitable floating gate transistor devices or other suitable chemically-sensitive transistors.

In another embodiment of the present invention, the parasitic capacitances coupled to the floating gate may be used to test the functionality of a floating gate transistor. FIG. 6 shows a simplified diagram of a floating gate transistor 600 such as an ISFET. The transistor 600 may include a floating gate 612, a drain 614, and a source 616. In this embodiment, the drain 614 and source 616 may be p-type implants within an n-type substrate, thus forming a p-channel FET device. However, it will be understood by those skilled in the art that the transistor 600 may be formed using an n-channel FET device having its drain and source formed using n-type implants within a p-type semiconductor.

An ISFET may be formed, generally, using a self-aligned process. A polysilicon gate may be formed, and floating gate 612 may be formed on a gate oxide 615 or other suitable gate insulator. Source and drain implants may be made in several steps. Before a nitride spacer is applied, an LDD (lightly doped drain) implant may be made. The LDD implant diffuses a small distance under the gate to reduce the electric field and to reduce the negative aspects of transistor performance such as hot carriers. The LDD implant, along with a step of degenerative doped implantation, forms the drain 614 and the source 616. The drain 614 and source 616 may have partially overlapping portions 607, 608 arranged under respective portions of gate oxide 615. The overlapping portions 607, 608 are formed within their respective implants such that a portion of the implants are beneath the floating gate electrode creating a parasitic capacitance. A process parameter relating to size of the overlap portions may be adjusted to control the size of the overlap portion and their capacitance.

FIG. 7 shows a circuit schematic equivalent to transistor 600 illustrating parasitic capacitance between the gate and source (CGS) and parasitic capacitance between the gate and drain (CGD). Alternatively, parasitic capacitance may exist between the gate and drain only or between the gate and source only.

In an embodiment of the present invention, a floating gate transistor may be tested using the above-described parasitic capacitance without using a fluidic bias to operate the floating gate. FIG. 8 illustrates a floating gate transistor test structure for a pixel element in an array according to an embodiment of the present invention. The floating gate transistor (e.g. an ISFET) of FIG. 8 is arranged in a source follower configuration; however, it will be understood by those skilled in the art that other configurations are applicable such as common source. The drain of the floating gate transistor may be coupled to a voltage power supply, VDD, to drive the transistor. VDD, for example, may be 3 volts. The source of the floating gate transistor may be biased with a current source. For example, the current source may be a 1 μA current source.

The voltage at the source (shown as VOUT in FIG. 8) may then be measured. The source voltage VOUT may be representative of the voltage on the floating gate. The parasitic capacitance of the transistor forces the floating gate into the saturation region and, thus, the transistor may produce source voltage VOUT, which follows the gate potential of interest. The transistor's threshold voltage and parasitic capacitance values may be designed to allow the proper coupling to the floating gate that is sufficient to bring the transistor into its operational range.

If the source voltage VOUT is within an expected range of a normal distribution of the array, the pixel may be considered operational because the test determines that the floating gate transistor can produce a valid and measurable signal. However, if the measured signal is too high or too low as compared to the normal distribution, it may indicate that an excessive trapped charge may be present at the floating gate. Also, if the distribution of the measured values in the tested array is significantly wide, it may indicate a large non-uniformity of the individual pixel elements. Large non-uniformities are generally considered unreliable and, thus, the array may be unusable.

In another embodiment, the floating gate transistor test may be expanded to measure the gain of the pixel and/or to determine other pixel properties. Again, the test may be conducted without using a fluidic bias to operate the floating gate and, therefore, maintaining the integrity of the array.

In an embodiment, the drain voltage may be varied while measuring corresponding source voltages. The source biasing current may held constant while the drain voltage is varied. In a first step, a first voltage may be applied to the drain, for example 3V, and the source may be biased accordingly. In a second step, the drain voltage may be adjusted to a second voltage, for example 2.8V, while the bias current at the source is held constant from the first step. The corresponding source voltage may be measured. The difference in the drain voltage (200 mV in the example) couples to the floating gate because of the overlap capacitance CGD. The resulting source voltage may thus be a fraction of the drain voltage difference. The ratio of the measured value to the input voltage represents the pixel gain and may be used to ascertain other pixel properties of interest.

Several embodiments of the present invention are specifically illustrated and described herein. However, it will be appreciated that modifications and variations of the present invention are covered by the above teachings. In other instances, well-known operations, components and circuits have not been described in detail so as not to obscure the embodiments. It can be appreciated that the specific structural and functional details disclosed herein may be representative and do not necessarily limit the scope of the embodiments.

Those skilled in the art may appreciate from the foregoing description that the present invention may be implemented in a variety of forms, and that the various embodiments may be implemented alone or in combination. Therefore, while the embodiments of the present invention have been described in connection with particular examples thereof, the true scope of the embodiments and/or methods of the present invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, specification, and following claims.

Various embodiments may be implemented using hardware elements, software elements, or a combination of both. Examples of hardware elements may include processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth), integrated circuits, application specific integrated circuits (ASIC), programmable logic devices (PLD), digital signal processors (DSP), field programmable gate array (FPGA), logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth. Examples of software may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces (API), instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an embodiment is implemented using hardware elements and/or software elements may vary in accordance with any number of factors, such as desired computational rate, power levels, heat tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds and other design or performance constraints.

Some embodiments may be implemented, for example, using a computer-readable medium or article which may store an instruction or a set of instructions that, if executed by a machine, may cause the machine to perform a method and/or operations in accordance with the embodiments. Such a machine may include, for example, any suitable processing platform, computing platform, computing device, processing device, computing system, processing system, computer, processor, or the like, and may be implemented using any suitable combination of hardware and/or software. The computer-readable medium or article may include, for example, any suitable type of memory unit, memory device, memory article, memory medium, storage device, storage article, storage medium and/or storage unit, for example, memory, removable or non-removable media, erasable or non-erasable media, writeable or re-writeable media, digital or analog media, hard disk, floppy disk, Compact Disc Read Only Memory (CD-ROM), Compact Disc Recordable (CD-R), Compact Disc Rewriteable (CD-RW), optical disk, magnetic media, magneto-optical media, removable memory cards or disks, various types of Digital Versatile Disc (DVD), a tape, a cassette, or the like. The instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, encrypted code, and the like, implemented using any suitable high-level, low-level, object-oriented, visual, compiled and/or interpreted programming language.

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Classifications
U.S. Classification324/679, 324/705, 257/253, 257/E23.179, 257/48
International ClassificationG01R27/08, H01L23/544, G01R27/26
Cooperative ClassificationH01L2924/0002, G01N27/4143, G01N27/4148, G01N27/4145, G01R31/2621, G01R31/2829
European ClassificationG01R31/28E9, G01R31/26C3
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Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BOLANDER, JARIE;FIFE, KEITH;MILGREW, MARK;SIGNING DATES FROM 20110715 TO 20110727;REEL/FRAME:026711/0180