US 20120070971 A1
There is provided a method for fabricating a semiconductor device comprising the formation of a first device in the first device region, the first device comprising first diffusion regions. A stressor layer covering the substrate in the first device region and the first device is subsequently formed, the stressor layer having a first stress value. A laser anneal to memorize at least a portion of the first stress value in the first device is carried out followed by an activation anneal after the laser anneal to activate dopants in the first diffusion regions.
1. A method for fabricating a semiconductor device comprising:
providing a substrate comprising a first device region;
forming a first device in the first device region, the first device comprising first diffusion regions;
forming a stressor layer covering the substrate in the first device region and the first device, the stressor layer having a first stress value;
performing a laser anneal to memorize at least a portion of the first stress value in the first device; and
performing an activation anneal after the laser anneal to activate dopants in the first diffusion regions.
2. The method of
3. The method of
4. The method of
5. The method of
6. The method of
7. The method of
8. The method of
9. The method of
10. The method of
11. The method of
12. The method of
This application is a continuation-in-part of U.S. application Ser. No. 12/510,276 filed Jul. 28, 2009, which is a continuation of U.S. application Ser. No. 11/940,326 filed Nov. 15, 2007, now issued as U.S. Pat. No. 7,592,270 which is a continuation of U.S. application Ser. No. 11/304,412 filed Dec. 15, 2005, which is now abandoned. These applications are hereby incorporated by reference in their entireties.
The present invention relates to generally to methods for fabricating semiconductor devices, and more particularly to methods for improving carrier mobility in semiconductor devices using stress engineering.
Integrated circuits (ICs) comprising many tens of thousands of semiconductor devices including field effect transistors (FETs) are a cornerstone of modern microelectronic systems. A common active device within an integrated circuit is the metal-oxide-semiconductor field effect transistor (MOSFET). A MOSFET typically comprises a gate stack composed of a gate electrode and an underlying gate dielectric. The gate stack is formed over a semiconductor substrate with a source and a drain diffusion region formed within the substrate on opposed sides of the gate stack. A channel region is located under the gate dielectric and between the source and drain regions. During operation, the channel region is converted to an “inversion mode” where a conductive path is formed to link the source and drain when a voltage is applied to the gate electrode.
One of the factors influencing the amount of current flow through a MOSFET channel is the mobility of carriers within the channel region. Specifically, an increase in the mobility of carriers in the transistor channel leads to a higher current during operation and correspondingly faster device operation. Therefore, semiconductor device structures and methods of fabrication that lead to increased mobility of carriers in the channel region are desirable.
The present invention relates to semiconductor devices and in particular, to semiconductor devices that utilize strain engineering.
In accordance with a first aspect of the invention, there is provided a method for fabricating a semiconductor device comprising providing a substrate comprising a first device region, forming a first device in the first device region, the first device comprising first diffusion regions and forming a stressor layer covering the substrate in the first device region and the first device, the stressor layer having a first stress value. A laser anneal is performed to memorize at least a portion of the first stress value in the first device followed by an activation anneal to activate dopants in the first diffusion regions.
These and other objects, along with advantages and features of the present invention herein disclosed, will become apparent through reference to the following description and the accompanying drawings. Furthermore, it is understood that the features of the various embodiments described herein are not mutually exclusive and can exist in various combinations and permutations.
In the drawings, like reference numbers generally refer to the same parts throughout the different views. Also, the drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, embodiments of the invention will now be described, by way of example with reference to the drawings of which:
The following embodiments are described in sufficient detail to enable those skilled in the art to make and use the invention. It is to be appreciated that other embodiments would be evident based on the present disclosure, and that system, process, or mechanical changes may be made without departing from the scope of the present invention.
Additionally, it is to be understood that a plurality of conventional processes that are well known in the art and not repeated herein, may precede or follow
Referring now to
The NMOS device comprises a p-well 106 formed within a semiconducting portion of the substrate and a gate electrode 122 formed above the surface of the substrate. A gate dielectric 120 separates the gate electrode from the surface of the substrate. First sidewall spacers 124 abut both vertical sidewalls of the gate dielectric and gate electrode stack, while second sidewall spacers 126 abut the outer sidewalls of the first spacers 124. At this stage of the manufacturing process, n-type source drain extension (NSDE) 130 regions substantially aligned to the outer edges of the first spacers 124 and n-type source drain (NSD) regions 132 substantially aligned to the outer edges of the second spacers 126 have been formed within the substrate on opposed sides of the gate electrode 122. The NMOS also includes a channel region 134 located below the gate dielectric 120 between the NSDE regions 130. In one embodiment, the NSDE and NSD regions (130, 132) are formed by implantation of n-type dopants such as Phosphorus, Arsenic or compounds thereof. A higher dose is typically used for the formation of NSD regions 132 and the dopants used for the two implant processes may be the same or different.
At least a surface portion of the NSD region 132 extending from the surface of the substrate 101 is in an amorphous state. The depth and degree of amorphization being chosen so as to facilitate the memorization of stress transmitted from a subsequently deposited stressor layer to the NMOS device. In general, the amount of stress memorization increases with the depth of the amorphous region but there is also a need to avoid dopant punchthrough and mitigate substrate damage caused by any amorphization implant.
The substrate in the NSD regions 132 may be transformed from a crystalline to amorphous state by implanting atoms such as Ge, Si, or inert gases like Ne, Ar, Kr into the targeted region. In one embodiment, the amorphization implant is carried out separately from the NSDE and NSD implant processes. It may take the form of an intermediate pre-amorphization implant step that is performed after the formation of the second spacers 126 and before implantation of N+ source/drain dopants. In another embodiment, the process of implanting NSDE and/or NSD dopants into the substrate may be capable of creating a degree of amorphization that is sufficient for the efficient transmission of stress from the above mentioned stress layer to the NMOS channel 134.
The PMOS device in
Each of the foregoing gate dielectric layer, gate electrode layer and spacers may be formed in a manner generally conventional in the semiconductor fabrication art. For example, the gate dielectric layer may comprise a dielectric material such as but not limited to silicon dioxide, silicon oxynitride, silicon nitride, a high-K metal oxide or a combination thereof. The gate dielectric may also be deposited using methods such as thermal oxidation, chemical vapor deposition, rapid thermal oxidation or the like. As for the gate electrode, it may comprise a conductive or semi-conductive material. Non-limiting examples include doped polysilicon, a metal silicide or a combination thereof. In one embodiment, the first and third spacers (124, 144) may comprise silicon oxide and the second and fourth spacers silicon nitride. Alternatively, other material compositions may also be used for the spacers depending on design and performance requirements and the number of sidewall spacers may also vary from that illustrated in
Referring now to
The laser SMT anneal conditions are also chosen so that the amorphized portions of the NSD regions are re-crystallized and substantial activation of the NSD dopants occurs during the SMT anneal. The laser SMT anneal may comprise the use of a gas laser source such as CO2/Argon-ion, or an excimer laser such as of ArF [193 nm], KrCl [222 nm], KrF [248 nm], XeCl [308 nm], and XeF [351 nm]). The duration of the laser SMT anneal may fall within the us—ns range with the laser source heating the substrate to a peak temperature of between 900° C. to 1400° C. The chuck temperature may range between 500° C. to 1000° C. It is to be appreciated that these parameters are not limiting and those skilled in the art will appreciate that the specific combination of parameters chosen will vary and additional parameters may also be employed/manipulated to effect the purpose of stress memorization and substantial dopant activation.
In general, the amount of stress transferred from a stressor layer to the channel of an NMOS tends increase with SMT anneal temperature. In this regard, laser SMT offers an advantage over other SMT anneal techniques such as lamp-based spike anneal because a laser source can achieve a peak temperature in excess of 1200° C. compared to a maximum temperature of between 1000 to 11150 ° C. for a lamp-based rapid thermal anneal source. Furthermore, laser anneal also has a lower thermal budget compared to other anneal sources such as rapid thermal anneal and lamp based anneals. The lower thermal budget allows for the use of high SMT anneal temperatures without incurring excessive junction outdiffusion.
Following the laser SMT anneal, a source/drain dopant activation anneal (as represented by arrows 520 in
It will be appreciated by those skilled in the art that after the source/drain activation anneal, additional conventional steps such as silicide contact formation, interconnect formation etc. can be performed as desired for the formation of an NMOS and PMOS transistor.
In one embodiment (not shown), portions of the stressor layer 220 overlying the PMOS device may be selectively removed before commencing the laser SMT anneal shown in
The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments, therefore, are to be considered in all respects illustrative rather than limiting the invention described herein. Scope of the invention is thus indicated by the appended claims, rather than by the foregoing description, and all changes that come within the meaning and range of equivalency of the claims are intended to be embraced therein.