|Publication number||US20120142187 A1|
|Application number||US 13/400,592|
|Publication date||Jun 7, 2012|
|Filing date||Feb 21, 2012|
|Priority date||Apr 16, 2010|
|Also published as||CN102222654A, CN102222654B, US8148824, US8202801, US20110254169|
|Publication number||13400592, 400592, US 2012/0142187 A1, US 2012/142187 A1, US 20120142187 A1, US 20120142187A1, US 2012142187 A1, US 2012142187A1, US-A1-20120142187, US-A1-2012142187, US2012/0142187A1, US2012/142187A1, US20120142187 A1, US20120142187A1, US2012142187 A1, US2012142187A1|
|Original Assignee||Shian-Jyh Lin|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (6), Classifications (12), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a division of U.S. application Ser. No. 12/761,413 filed Apr. 16, 2010.
1. Field of the Invention
The present invention relates to interconnection technologies within semiconductor chips, especially to semiconductor devices with Through-Silicon-Via (TSV).
2. Description of the Prior Art
Since the invention of integrated circuits, the semiconductor industry has experienced continuous rapid growth due to constant improvements in the integration density of various electronic components. For the most part, this improvement in integration density has come from repeated reductions in the minimum feature size, allowing more components to be integrated into chips.
One method of scaling down includes three-dimensional stacking of chips used to form a stacked integrated circuit package. Three-dimensional (3-D) die stacking increases integration density and chip functionality by vertically integrating two or more dice. 3-D integration also improves interconnect speed by decreasing interconnect wire length, and reduces power dissipation and crosstalk.
Therefore, the Through-Silicon-Via (TSV) connection is developed to use in forming interconnects for stacked wafers, stacked chip, and/or combinations thereof for 3-D packaging technologies.
TSV is created through a substrate (e.g. wafer), by forming a via extending from a front surface to a back surface of the substrate, and filling the via with a conductive material. Generally the conductive material is copper.
Copper has a coefficients of thermal expansion (CTE) of approximately 16.5×10−6/K, and silicon has a CTE of approximately 4.68×10−6/K. Thus, this CTE mismatch may result in significant stress between the silicon and copper.
Because of the CTE mismatch, under normal operation, a mechanical stress may be induced at a copper-silicon interface when the package undergoes a temperature excursion. The stress may result in numerous problems, including thin-film delamination, cracking of the silicon and reduced transistor performance.
To maintain a mechanical stress resulting from a CTE mismatch for a given temperature excursion, via size may be reduced, spacing between adjacent vias may be increased, or vias may be positioned far from active circuitry. Each of these options may lead to increased chip size, lower density circuits or increased cost per chip.
In an exemplary embodiment, a semiconductor device with a through substrate via includes: a substrate; and a through substrate via penetrating the substrate, wherein the through substrate via comprises: an outer tube penetrating the substrate; at least one inner tube disposed within the outer tube; a dielectric layer lining on a side wall of the outer tube, and a side wall of the inner tube respectively; a strength-enhanced material filling the inner tube; and a conductive layer filling the outer tube.
In another exemplary embodiment, a method of fabricating a semiconductor device with a through substrate via, includes: providing a substrate; patterning the substrate to form at least one inner tube in the substrate; forming a first dielectric layer on an exposed surface of the inner tube; forming a strength-enhanced material filling the inner tube; patterning the first dielectric layer and the substrate to form an outer tube, wherein the inner tube is surrounded by the outer tube; forming a second dielectric layer on a side wall of the inner tube, and a side wall of the outer tube; and filling the outer tube with a conductive layer.
A novel structure of a through substrate via is provided. The novel structure is composed of the outer tube with a plurality of inner tubes within. The conductive layer for connecting stacked wafers or stacked chips fills up the outer tube. Furthermore, the inner tube is filled with strength-enhanced material for increasing the mechanical strength of the through substrate via. Because of the numerous inner tubes inside the outer tube, the stress formed due to CTE mismatch can be dispersed.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:
As shown in
Next, a patterned mask 22 such as a patterned photoresist having at least one inner tube pattern is formed on the hard mask 20. Referring to
As shown in
As shown in
As shown in
As shown in
According to another preferred embodiment of the present invention, a semiconductor device with a through substrate via 40 is provided. Referring to
The lower end of each of the inner tubes 24 has a distance d1 lower than the front side 12 of the substrate 10. The distance d1 is advantageously 1 μm to 7 μm. More specifically, the lower end of each of the inner tubes 24 has distance d2 distant from the back side 14 of the substrate 10. The distance d2 is preferably 43 μμm to 49 μm, but not limited to it. The distance d1 is decided basing on the depth of the semiconductor element 16.
The shape of the outer tube 34 and the inner tubes 24 may be cylinder, trihedron, tetrahedron, pentahedron or hexahedron. For example, as shown in
The feature of the embodiment in the present invention is that there are numerous inner tubes disposed inside the outer tube. The stress arises from CTE mismatch can be distributed onto the numerous inner tubes. Furthermore, the silicon nitride filling within the inner tubes can increase the strength of the top portion of the through substrate via. The top portion of the through substrate via refers to 1˜7 μm below the front side of the substrate. Therefore, the semiconductor element near the through substrate via will not be deteriorated by the stress. Moreover, tungsten has a CTE of is approximately 4.5 10−6/K, and silicon nitride has a CTE of approximately 3.3 10−6/K. As illustrated in the foregoing description, the copper has a CTE of approximately 16.5 10−6/K, and silicon has a CTE of approximately 4.68 10−6/K. Therefore, the CTE of copper is much greater than that of the silicon. Compared to copper, tungsten has a similar CTE as compared to silicon. Therefore, a through substrate via with tungsten as the conductive layer will have smaller stress generated by CTE mismatch than a through substrate via with copper as the conductive layer. Furthermore, silicon nitride has even smaller CTE than tungsten. As a result, the silicon nitride filling inside the inner tubes merely generate small stress. As a result, the through substrate via described in the foregoing preferred embodiment possesses a structure with low stress generated by the CTE mismatch.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US6180536 *||Jun 4, 1998||Jan 30, 2001||Cornell Research Foundation, Inc.||Suspended moving channels and channel actuators for microfluidic applications and method for making|
|US7898087 *||May 13, 2008||Mar 1, 2011||International Business Machines Corporation||Integrated chip carrier with compliant interconnects|
|US7964972 *||Jun 29, 2005||Jun 21, 2011||Renesas Electronics Corporation||Semiconductor device providing a first electrical conductor and a second electrical conductor in one through hole and method for manufacturing the same|
|US20070052067 *||Aug 29, 2006||Mar 8, 2007||Sanyo Electric Co., Ltd||Semiconductor device, method of manufacturing the same, circuit board, and method of manufacturing the same|
|US20100048019 *||Feb 25, 2010||Nec Electronics Corporation||Method for manufacturing a semiconductor device|
|US20100197134 *||Aug 5, 2010||John Trezza||Coaxial through chip connection|
|U.S. Classification||438/667, 257/E21.597|
|Cooperative Classification||H01L2924/01019, H01L2225/06544, H01L2924/09701, H01L23/481, H01L2224/94, H01L25/0657, H01L21/76898|
|European Classification||H01L21/768T, H01L23/48J|
|Feb 21, 2012||AS||Assignment|
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LIN, SHIAN-JYH;REEL/FRAME:027732/0869
Effective date: 20100415
Owner name: NANYA TECHNOLOGY CORP., TAIWAN