US20120149133A1 - Mems process method for high aspect ratio structures - Google Patents
Mems process method for high aspect ratio structures Download PDFInfo
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- US20120149133A1 US20120149133A1 US12/966,397 US96639710A US2012149133A1 US 20120149133 A1 US20120149133 A1 US 20120149133A1 US 96639710 A US96639710 A US 96639710A US 2012149133 A1 US2012149133 A1 US 2012149133A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
- B81C1/00555—Achieving a desired geometry, i.e. controlling etch rates, anisotropy or selectivity
- B81C1/00619—Forming high aspect ratio structures having deep steep walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
- H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
Abstract
Methods for the controlled manufacture of high aspect ratio features. The method may include forming a layer stack on a top surface of a substrate and forming features in the layers of the layer stack. The high aspect ratio features may be defined using a resist layer that is patterned with a photolithographic condition. After removing at least one of the layers removed from the top of the layer stack, a feature dimension may be measured for features at different locations on the substrate. The method may further include changing the photolithographic condition based on the measured dimension and processing another substrate using the changed photolithographic condition.
Description
- The present invention relates to semiconductor device fabrication, and more specifically, to the fabrication of high aspect ratio structures.
- Micro-electro-mechanical system (MEMS) manufacturing often requires the fabrication of high aspect ratio structures. One of the primary challenges in MEMS manufacturing is the ability to etch uniform high aspect ratio structures across a substrate surface. For example, profile asymmetries as low as 10 nm have been observed to produce unacceptable device performance in a MEMS gyroscope element. Etch non-uniformities may exhibit an aspect ratio dependence, a micro-loading or pattern density dependence, an across-substrate dependence, or an etch chamber dependence.
- Critical dimension features near the bottom portion of the high aspect ratio structures are difficult to measure with an in-line critical dimension (CD) scanning electron microscope (SEM) because shadowing of the primary electron beam occurs beyond a certain depth at a given feature aspect ratio. While dimensions of the top portion of the high aspect ratio structures can be readily measured using an SEM, the dimensions of the bottom portion of the high aspect ratio structures is arguably more important. Specifically, the bottom portion of the high aspect ratio structures determines the feature size uniformity of subsequently etched features if the high aspect ratio structures are used as a hardmask, or the device performance depends on the original high aspect ratio structures. An inaccurately measured critical dimension influenced by the depth of the high aspect ratio structures may produce errors if used to adjust either the photolithography process or a subsequent etching process.
- Therefore, there is a need for processing methods that improve the dimensional uniformity of high aspect ratio structures.
- In an embodiment, a method may include forming a plurality of layers on a top surface of a first substrate and forming a plurality of features extending through at least one of the plurality of layers. The features may be defined using a resist layer patterned with a photolithographic condition. At least one of the layers may be removed and, in response to removing at least one of the layers, a feature dimension may be measured for features at different locations on the first substrate. The method may further include changing the photolithographic condition based on the measured dimension and processing a second substrate using the changed photolithographic condition.
- The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with a general description of the invention given above, and the detailed description given below, serve to explain the invention.
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FIG. 1 is a flow diagram of a conventional high aspect ratio etch process. -
FIG. 2 illustrates a series of cross-sectional views at different points during the etch process ofFIG. 1 and at different locations on the substrate during the high aspect ratio etches. -
FIG. 3 is a flow diagram of a high aspect ratio etch process consistent with embodiments of the invention. -
FIG. 4 illustrates a series of cross-sectional views at different points during the etch process ofFIG. 3 and at different locations on the substrate during the high aspect ratio etches. -
FIG. 5 is a flow diagram of a conventional surface high aspect ratio etch process. -
FIG. 6 illustrates a series of cross-sectional views at different points during the etch process ofFIG. 5 and at different locations on the substrate during the high aspect ratio etches. -
FIG. 7 is a flow diagram of a surface high aspect ratio etch process consistent with embodiments of the invention. -
FIG. 8 illustrates a series of cross-sectional views at different points during the etch process ofFIG. 7 and at different locations on the substrate during the high aspect ratio etches. -
FIG. 9 is a block diagram of a multi-chamber configuration for a conventional high aspect ratio etch process. -
FIG. 10 is a block diagram of a multi-chamber configuration for a high aspect ratio etch process consistent with embodiments of the invention. - Embodiments of the invention assist in preventing feature size variation, such as CD variation, across a wafer or substrate during a high-aspect-ratio etching process. Feedback from a reference standard may be used to assist in fabricating high aspect ratio structures with uniform feature dimensions across the substrate surface in a manufacturing environment, which may include multiple product designs and multiple etching platforms.
- With reference to the flow diagram 10 in
FIG. 1 and the cross-sectional views ofFIG. 2 , a conventional method for the fabrication of features in the form of high aspect ratio structures is described for comparative purposes. Atblock 12, alayer stack 30 is formed that may include apad layer 34 of oxide (SiO2), apad layer 36 of silicon nitride (Si3N4), and one or moresacrificial films 38 formed on a top surface of a wafer orsubstrate 32. One of ordinary skill in the art will recognize that other materials and additional or fewer layers may be used depending on the requirements of the final fabricated device. - The
substrate 32 may be comprised of any material that a person having ordinary skill in the art would recognize as suitable for use in fabricating a MEMS structure or another type of structure with high aspect ratio features. Thesubstrate 32 may be comprised of silicon (Si), silicon-germanium (SiGe), a III-V substrate such as gallium arsenide (GaAs), sapphire, or another type of material, or a layered substrate such as silicon-on-insulator (SOI), that. In a representative embodiment, thesubstrate 32 may be comprised of a bulk silicon wafer. - The materials constituting the
pad oxide layer 34,pad nitride layer 36, andsacrificial film 38 are chosen to etch selectively to (i.e., at a higher etch rate than) the semiconductor material constituting thesubstrate 32 and to also be readily removed at a subsequent fabrication stage. In one embodiment,sacrificial film 38 may be comprised of SiO2 deposited, for example, by a chemical vapor deposition (CVD) process. Thepad oxide layer 34, which is thinner than thepad nitride layer 36 andsacrificial film 38, may be formed by a wet or dry thermal oxidation process. Thepad nitride layer 36 may be deposited by, for example, a CVD process. - At
block 14, aresist film 28, which is used to pattern thelayer stack 30, is formed on a top surface of the one or moresacrificial films 38 by applying a resist coating and using a photolithography process to pattern the resist coating. The photolithography process entails exposing theresist film 28, which is comprised of a radiation-sensitive sacrificial organic material, to radiation imaged through a photomask and developing the resultant latent feature pattern in the exposed resist to define openings or windows at the intended locations of high aspect ratio structures. The windows in theresist film 28 extend to the top surface of the one or moresacrificial films 38. - At
block 16, adimension 40, for example a critical dimension (CD), of the windows in theresist film 28 may be measured as indicated in the left hand panel ofFIG. 2 using a scanning electron microscope (SEM) (e.g., an in-line critical dimension scanning electron microscope (CDSEM)) or another suitable metrology tool. The critical dimension, also known as the minimum feature size, represents the dimensions of the smallest geometrical features, in this case a width of the high aspect ratio structures, that can be formed during semiconductor device/circuit manufacturing using given technology. The measurement process may be limited to assess only those windows having a critical dimension. - At
block 18, a first high aspect ratio etch occurs through thesacrificial film 38,pad nitride layer 36, andpad oxide layer 34 to form initial high aspect ratio structures in thelayer stack 30 at the locations of the windows in the patternedresist film 28. The patternedlayer stack 30 will function as a hardmask for subsequently etching the high aspect ratio structures into thesubstrate 32. The first high aspect ratio etch may over-etch to a shallow depth into the semiconductor material of thesubstrate 32. The feature pattern may be transferred from the patternedresist film 28 to thelayer stack 30 by an anisotropic dry etch process, such as a reactive-ion etching (RIE) process. Theresist film 28 is removed by ashing or chemical stripping. - At
block 20, an SEM may be used to measure adimension 40 a of thelayer stack 30 near the center of thesubstrate 32 and adimension 40 b of thelayer stack 30 near a peripheral edge of thesubstrate 32 as indicated in the central panel ofFIG. 2 . The measurement process may be restricted to measuringdimensions measurable dimensions dimensions substrate 32, respectively, may differ and may not be within an acceptable tolerance. This variation may be due to, for example, material variations, variations in the process equipment, or potentially other process variations. Because of the high aspect ratio of the windows in thelayer stack 30, the SEM cannot measure thedimensions - At
block 22, a second high aspect ratio etch is performed that uses the patternedlayer stack 30 as a hardmask. At the locations of the windows in the patternedlayer stack 30, the second high aspect ratio etch forms features insubstrate 32 having the form of highaspect ratio structures FIG. 2 . In the representative embodiment, the highaspect ratio structures substrate 32. The second high aspect ratio etch may be executed using any suitable conventional anisotropic etch process, such as deep reactive ion etching (e.g., DRIE), capable of producing substantially vertical trench sidewalls. Areas of thesubstrate 32 masked by the patternedlayer stack 30 are protected during the second high aspect ratio etch. - A representative DRIE process for forming the high
aspect ratio structures substrate 32. During the passivation step, a plasma generated from a source gas, such as C4F8, coats the sidewalls of the highaspect ratio structures aspect ratio structures - Alternatively, another DRIE process for forming the high
aspect ratio structures - At
block 24 and after the highaspect ratio structures sacrificial film 38 is removed to expose thepad nitride layer 36. Thesacrificial film 38 may be removed utilizing a conventional wet chemical stripping process, such as substrate immersion in a solution containing a mixture of hydrofluoric and sulfuric acids. Atblock 26, a SEM is employed to actually measure thedimension 42 a of highaspect ratio structures 37 at or near the center of thesubstrate 32 and thedimension 42 b at or near the peripheral edge of thesubstrate 32. Because of etch non-uniformity across thesubstrate 32 in the conventional process flow, thedimensions aspect ratio structures FIG. 2 . This dimensional difference may be significant enough that the highaspect ratio structures unmeasured dimensions aspect ratio structures - To assist in avoiding the variation of the feature dimensions across the
substrate 32 resulting from the conventional process flow, embodiments of the invention employ a feedback method to assist in fabricating uniform high aspect ratio structures across thesubstrate 32 surface in a manufacturing environment, which also may include multiple product designs and multiple etch platforms. Exemplary embodiments related to both bulk silicon MEMS structures, such as the structure inFIGS. 1 and 2 above, as well as surface MEMS structures explained in more detail later. - In accordance with an embodiment of the invention, a sacrificial substrate may be used to assess the uniformity of the first high aspect ratio etch. After the first high aspect ratio etch is performed, all or a portion of the hardmask is removed to reveal the etched features. A dimension of these features is measured, for example with an in-line SEM. The information from the measurements on the partially etched sacrificial substrate may then be fed back to the photolithography process. Subsequently processed substrates may be regionally compensated with reliance upon the feedback from the sacrificial substrate. This method may also apply to high aspect ratio structures formed using more than two sequential etch processes, as will be understood by one of ordinary skill in the art.
- With reference to
FIGS. 3 , 4 in which like reference numerals refer to like features inFIGS. 1 , 2 and in accordance with an embodiment of the invention, the resistfilm 28 is spin coated ontolayer stack 30 atblock 52 in the flow diagram 50. Atblock 54, the resistfilm 28 is patterned using a set of photolithographic conditions in the lithography tool. Atblock 56, after the pattern has been developed, the SEM is used to measure one or more dimensions, such as critical dimensions, of the windows in the resistfilm 28 at several preset locations, such as near the center of thesubstrate 32 and near the peripheral edge of thesubstrate 32. - At
block 58, the first high aspect ratio etch is executed that patterns thelayer stack 30 with an over-etch condition that etches to a shallow depth into the semiconductor material of thesubstrate 32. At this point, atblock 60, the process flow is interrupted and the resistfilm 28 and thesacrificial film 38 are removed. The resistfilm 28 may be removed by ashing or chemical stripping. Thesacrificial film 38 may be removed utilizing a conventional wet chemical stripping process, such as immersion in an etchant containing a mixture of hydrofluoric and sulfuric acids if thesacrificial film 38 is comprised of SiO2. - At
block 62, the SEM is used to measure thedimensions substrate 32 and near the peripheral edge of thesubstrate 32 as apparent in the left hand panel ofFIG. 4 . The removal of the interveningsacrificial film 38 permits the measurement of thedimensions dimensions - The measured
dimensions dimensions 40 of the corresponding windows in the resistfilm 28. Based upon the evaluation, field compensations for the photolithographical patterning of the resistfilm 28 are calculated inblock 64. The field compensations are attributed to the etch process and given a spatial correlation with location across thesubstrate 32. The field compensations may be implemented by adjustments or modulations of the one or more of the photolithographic conditions (e.g., radiation dose) of the radiation (e.g., light or UV radiation) used during the photolithography process patterning the resistfilm 28. The field compensations may be contained in a look-up table or may be formula-based. The field compensations contain correlation data or curves that provide correction data for the photolithography process based upon the measureddimensions - At
block 66, the feedback from the sacrificial substrate is implemented in the patterned resistfilm 28 formed on subsequently processedsubstrates 32. The resist pattern includes regional compensations for one or more of the photolithographic conditions in the lithography tool based upon the field compensations derived from the sacrificial substrate. As a result of the information contained in the feedback, the feature size in the portion of the resistfilm 28 a near the substrate center (dimension 46 a) may be different than the feature size in the portion of the resistfilm 28 b near the substrate peripheral edge (dimension 46 b) as apparent in the central panel ofFIG. 4 . - The first and second high aspect ratio etches are conducted at
blocks FIG. 4 . Each of the highaspect ratio structures 39 has a depth and a width that contribute to an aspect ratio, which may be defined as the ratio of depth to width of a feature. The highaspect ratio structures 39 may have a depth-to-width ratio in a range of 10:1 to 50:1 or higher. - At
block 72, thesacrificial film 38 is removed. The SEM is used to measure thedimension 48 of the high aspect ratio features 39 at one or more locations across thesubstrate 32 atblock 74. As a result of the regional compensations made to the photolithography process forming the pattern in resistfilm 28,dimension 48 is more uniform across thesubstrate 32. - While the above described process flow applies to fabrication requiring micromachining of a bulk substrate, the principles of the embodiments of the invention also apply to a different application, namely surface micromachining.
- For comparative purposes, a conventional surface micromachining process flow is presented below with reference to
FIGS. 5 and 6 . Beginning with the flow diagram 80 inFIG. 5 and with reference to the structural cross-sections ofFIG. 6 , blocks 82-92 provide a conventional process flow to create alayered structure 110 with high aspect ratio etching. Atblock 82, afirst layer 116 of polycrystalline silicon (polysilicon) is deposited on asilicon substrate 112 covered by apad oxide layer 114 and apad nitride layer 115. The polysilicon in thefirst polysilicon layer 116 may be deposited using a known deposition process, such as physical vapor deposition (PVD) or CVD. - At
block 84, thefirst polysilicon layer 116 is patterned and etched to impart a desired configuration. Thefirst polysilicon layer 116 may be patterned by applying a photoresist (not shown), exposing the photoresist using radiation imaged through a photomask, and then developing the exposed photoresist to provide an intended pattern to be formed in thefirst polysilicon layer 116. The pattern may be transferred from the photoresist into thefirst polysilicon layer 116 with a RIE process. - At
block 86, alayer 118 of, for example, SiO2 is deposited and also patterned to impart a desired configuration. Atblock 90, asecond polysilicon layer 120 is deposited, followed by asacrificial film 122 comprised of e.g., SiO2 atblock 92. One of ordinary skill in the art will realize that any number of deposition and pattern/etch steps may be performed to generate the appropriate structure for etching and that such structures are not limited to the exemplary structure provided in this example. - A resist
film 124 may be deposited on the layer stack 164 and patterned in a photolithography step atblock 94. After the pattern has been developed, atblock 96, a SEM may be used to measure adimension 126, for example a critical dimension (CD), of the windows in the patterned resistfilm 124 at several locations across thesubstrate 112, as apparent in the left hand panel ofFIG. 6 . - At
block 98, a first high aspect ratio etch is performed that produces features extending through, in this example, thesacrificial film 122 and slightly into thepolysilicon layer 120. Atblock 100, featuredimensions substrate 112. For example, a SEM may be used to measure thedimension 126 a near the center of thesubstrate 112 and thedimension 126 b near the peripheral edge of thesubstrate 112, as apparent in the central panel ofFIG. 6 . While the measureddimensions dimensions substrate 112, respectively, are not measurable with the SEM. Thedimensions 128 a, 128 may be non-uniform and outside of acceptable tolerances, and this out-of-tolerance condition may be unknown at this stage of the process flow in the flow diagram 80. The dimensional variation may be due to variations in the material, variations in the process equipment, or other process variations. - A second high aspect ratio etch is performed at
block 102 to form features in the representative form of highaspect ratio structures sacrificial film 118 is removed atblock 104. Atblock 106, the SEM is used to determine therespective dimensions aspect ratio structures FIG. 6 . Thedimension 128 a of highaspect ratio structure 129, which is measured near the center of thesubstrate 112, may differ from thedimension 128 b of highaspect ratio structure 131 measured near the peripheral edge of thesubstrate 112. The difference in thedimensions substrate 112. - With reference to
FIGS. 7 , 8 in which like reference numerals refer to like features inFIGS. 5 , 6 and in accordance with an embodiment of the invention, the different layers in the layer stack of thelayered structure 110 are applied tosubstrate 112 and patterned at blocks 132-142 in the flow diagram 130 as described above with regard to flow diagram 80 (FIG. 5 ). Atblock 144, a resist film (not shown) is applied and patterned to define windows at the intended locations for the high aspect ratio structures. After the pattern has been formed in the resist film, atblock 146, an SEM is used to measure a dimension (e.g. a critical dimension) for the resist windows at several locations across thesubstrate 112. - At
block 148, a first high aspect ratio etch similar to the first high aspect ratio etch described above (FIGS. 5 , 6) is executed that patterns thesacrificial film 122 of thelayered structure 110 with an over-etch condition that etches to a shallow depth into thepolysilicon layer 120, as apparent in the left hand panel ofFIG. 8 . At this point, atblock 150, the process flow is interrupted and the resist film and thesacrificial film 122 is removed. The resist film may be removed by ashing or chemical stripping. Thesacrificial film 122 may be removed utilizing a conventional wet chemical stripping process, such as immersion in an etchant containing a mixture of hydrofluoric and sulfuric acids if thesacrificial film 122 is comprised of SiO2. - At
block 152, the SEM is used to measure thedimensions substrate 112 and near the peripheral edge of thesubstrate 112 as apparent in the left hand panel ofFIG. 8 . The removal of the interveningsacrificial film 122 permits the measurement of thedimensions dimensions polysilicon layer 120 that are critical dimensions. - The measured
dimensions block 152. The field compensations are attributed to the etch process and given a spatial correlation with location across thesubstrate 112. The field compensations may be implemented by adjustments or modulations of the one or more of the photolithographic conditions (e.g., radiation dose) of the radiation (e.g., light or UV radiation) used during the photolithography process patterning the resist film. The field compensations may be contained in a look-up table or may be formula-based. The field compensations contain correlation data or curves that provide correction data for the photolithography process based upon the measureddimensions - At
block 154, a pattern is formed in the resistfilm 124 deposited onsubstrate 112, which may be a production substrate. The pattern includes regional compensations for one or more of the photolithographic conditions in the lithography tool based upon the field compensations from thesacrificial substrate 112 such that thefeature dimension 166 a in the resistfilm 124 near the substrate center is different than thefeature dimension 166 b in the resistfilm 28 near the substrate peripheral edge. - At
block 154, these patterns are developed in the resistfilm 124 that is deposited onproduction substrates 112. The two-stage high aspect ratio etch occurs atblocks aspect ratio structures 155, which are features represented by openings with sidewalls extending into thepolysilicon layer 120. Thesacrificial film 122 is removed atblock 160. TheCD 168 is measured atblock 162, which, due to the compensations made to the photolithographic film patterns, may now be more uniform across theproduction substrate 112. - At
block 154, the feedback from the sacrificial substrate is implemented in the patterned resistfilm 124 formed on subsequently processedsubstrates 112. The resist pattern includes regional compensations for one or more of the photolithographic conditions in the lithography tool based upon the field compensations derived from the sacrificial substrate. As a result of the information contained in the feedback, the feature size in portion of the resistfilm 124 a near the substrate center (dimension 166 a) may be different than the feature size in the portion of the resistfilm 124 b near the substrate peripheral edge (dimension 166 b) as apparent in the central panel ofFIG. 8 . - The first and second high aspect ratio etches are conducted at
blocks FIG. 8 . The highaspect ratio structures 155 are features represented by openings with sidewalls extending into the thepolysilicon layer 120. Each of the highaspect ratio structures 155 has a depth and a width that contribute to an aspect ratio, which is defined as the ratio of depth to width of a feature. The highaspect ratio structures 155 may have a depth-to-width ratio is a range of 10:1 to 50:1 or higher. - At
block 160, thesacrificial film 122 is removed. The SEM is used to measure the dimension 168 (e.g., a critical dimension) of the high aspect ratio features 155 at one or more locations across thesubstrate 112 atblock 162. As a result of the regional compensations made to the photolithography process forming the pattern in resistfilm 124,dimension 168 is more uniform across thesubstrate 32. - The feedback process may also be applied to compensate for etch variations when multiple etch chambers are used. For example, and as illustrated in the block diagram in
FIG. 9 , asubstrate 112 to be processed has a hardmask comprised of, for example, oxide and nitride pad films and/or a thicker sacrificial film applied atblock 172. A photo step occurs atblock 174 to provide an appropriately patterned resist layer for a mask open etch. At this point, thesubstrate 112 may be etched in either of theplasma etching chambers etch chambers substrate 112 may be subsequently etched in eitherplasma etching chambers previous chamber block 180 and critical dimension measurements acquired inblock 182. - The critical dimension for any combination of
Etch 1 inetch chambers Etch 2 inetch chambers etch chambers →block 178 b; block 176 b→block 178 b; block 176 b→block 178 a). Any compensation calculated inblock 184 is applied back at the photo step inblock 174. The feedback may assist in improving the critical dimension uniformity across thesubstrate 112, but as mentioned above, may not optimize the processing due to potential critical dimension variations originating from the mask open etch that are convolved in the critical dimension measurement and not easily extricable. Additionally, while the etch chamber parameters may be adjusted to assist in maintaining critical dimension matching, these changes are actually compensating for changes at both the substrate (e.g., silicon) etch and mask open etch, so variability may be high and thereby cause more frequent changes to the etch process parameters. - In order to improve critical dimension matching independent of the mask open etch and semiconductor etch path, and referring now to
FIG. 10 , a sacrificial substrate may be employed to measure and account for any variation after the mask open etch inblock block 172 and a photo step atblock 174 in preparation for the mask open etch. At this point, the mask open etch of the sacrificial substrate may be performed in either chamber represented byblock block 192 and critical dimension measurements are taken atblock 194. At this point, field compensations for the photolithography process (as described above) and chamber matching for theetch chambers block 184 and applied at the photolithography step inblock 174 as well as the mask open etch inetch chambers - Each of the
etch chambers - The
etch chambers substrates 112. With use or following maintenance or chamber cleaning, the etching conditions ofetch chambers etch chambers etch chambers etch chambers etch chambers - Once the inhomogeneities between the
etch chambers block 172 and the photo step atblock 174. At this point, the substrate may be etched in either chamber represented byblock block block 180 after the features are formed in the production substrate and critical dimension measurements taken inblock 182. - Because compensations for the mask open etch have already been applied, the only compensations left are for chamber matching of the
etch chambers FIG. 9 , and any subsequent substrates being processed should be more path independent without having the large critical dimension variations produced in the absence of compensating for differences between theetch chambers - The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
- The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
Claims (19)
1. A method comprising:
forming a plurality of layers comprising a hardmask on a top surface of a first substrate;
forming a first plurality of high aspect ratio features extending through at least one of the layers, the first plurality of high aspect ratio features defined with an etching process using a first resist layer patterned with a photolithographic condition in a photolithography tool;
removing at least one of the layers;
in response to removing at least one of the layers, measuring a dimension of the first high aspect ratio features at different locations on the first substrate;
changing the photolithographic condition in the photolithography tool based on the measured dimension; and
processing a second substrate in the photolithography tool using the changed photolithographic condition,
wherein processing the second substrate includes etching a second plurality of high aspect ratio features and measuring a dimension of the second plurality of high aspect ratio features.
2. The method of claim 1 further comprising:
applying a second resist layer on a third substrate; and
patterning the second resist layer in the photolithography tool using the changed photolithographic condition.
3. The method of claim 2 wherein the second resist layer is applied on a plurality of layers on the third substrate, and further comprising:
etching a plurality of third features extending through the layers on the third substrate and into the third substrate.
4. The method of claim 3 wherein the third features are high aspect ratio structures each with sidewalls that extend into the third substrate.
5. The method of claim 2 wherein the second resist layer is applied to a plurality of layers on the third substrate, and further comprising:
etching a plurality of third features extending through at least one of the layers on the third substrate.
6. The method of claim 5 further comprising:
removing at least one of the layers using the third features as an access path for an etchant.
7. The method of claim 5 wherein the third features are high aspect ratio structures each with sidewalls that extend through the one or more of the layers but not into the third substrate.
8. The method of claim 2 wherein the changed photolithographic condition is a change in a dose of radiation used to pattern the second resist layer in comparison with the first resist layer.
9-10. (canceled)
11. The method of claim 1 wherein the first plurality of high aspect ratio features are formed using a process recipe in a first etch chamber, and each of the first plurality of high aspect ratio extend through the layers features to a shallow depth into the first substrate.
12. The method of claim 11 wherein removing at least one of the layers comprises:
removing the hardmask.
13. The method of claim 11 further comprising:
changing at least one process parameter for the process recipe used by the first etch chamber based on the measured dimension for the first plurality of high aspect ratio features.
14. The method of claim 12 further comprising:
forming a plurality of layers comprising a hardmask on a top surface of a third substrate;
forming a third plurality of high aspect ratio features extending through the layers on the third substrate to a shallow depth into the third substrate using the etch recipe in a second etch chamber;
removing the hardmask;
in response to removing the hardmask, measuring a dimension of each of the third plurality of high aspect ratio features at the shallow depth in the third substrate; and
changing at least one process parameter of the process recipe for the second etch chamber based on the measured dimension for the third plurality of high aspect ratio features.
15. The method of claim 14 wherein the at least one process parameter of the process recipe for the first etch chamber and the at least one process parameter of the process recipe for the second etch chamber are changed to minimize a difference between the measured dimension of each of the first plurality of high aspect ratio features at the shallow depth in the first substrate and the measured dimension of each of the third plurality of high aspect ratio features at the shallow depth in the third substrate so that the first etch chamber is matched to the second etch chamber.
16. The method of claim 1 wherein the measured dimension is a critical dimension.
17. The method of claim 1 wherein measuring the dimension of the first high aspect ratio features at different locations on the first substrate comprises:
measuring the dimension of at least one of the first high aspect ratio features near the center of the first substrate; and
measuring the dimension of at least one of the first high aspect ratio features near a peripheral edge of the first substrate.
18. The method of claim 1 wherein measuring the dimension of the first high aspect ratio features at different locations on the first substrate comprises:
assessing the dimension of the first high aspect ratio features by imaging with a secondary electron microscopy.
19. The method of claim 1 further comprising:
processing a third substrate with the changed photolithographic condition in the photolithography tool to perform bulk micromachining of a micro-electro-mechanical systems device.
20. The method of claim 1 further comprising:
processing a third substrate with the changed photolithographic condition in the photolithography tool to perform surface micromachining of a micro-electro-mechanical systems device.
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