US20150001672A1 - Bi-directional esd diode structure with ultra-low capacitance that consumes a small amount of silicon real estate - Google Patents

Bi-directional esd diode structure with ultra-low capacitance that consumes a small amount of silicon real estate Download PDF

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US20150001672A1
US20150001672A1 US13/931,936 US201313931936A US2015001672A1 US 20150001672 A1 US20150001672 A1 US 20150001672A1 US 201313931936 A US201313931936 A US 201313931936A US 2015001672 A1 US2015001672 A1 US 2015001672A1
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semiconductor layer
layer
diode structure
touches
dopant concentration
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US9059324B2 (en
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Toshiyuki Tani
Akihiko Yamashita
Motoaki KUSAMAKI
Kentaro Takahashi
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Texas Instruments Inc
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Texas Instruments Inc
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Priority to CN201410271089.5A priority patent/CN104253162A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66121—Multilayer diodes, e.g. PNPN diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8618—Diodes with bulk potential barrier, e.g. Camel diodes, Planar Doped Barrier diodes, Graded bandgap diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66136—PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes

Definitions

  • the present invention relates to bi-directional ESD diode structures and, more particularly, to a bi-directional ESD diode structure with ultra-low capacitance that consumes a small amount of silicon real estate.
  • An electrostatic discharge (ESD) circuit is a circuit that protects an integrated circuit from voltage spikes, which commonly occur when the integrated circuit is handled.
  • an ESD circuit provides an open circuit between a first node and a second node when the voltage difference across the first and second nodes is less than a breakdown voltage.
  • the ESD circuit when the voltage difference across the first and second nodes spikes up to be equal to or greater than the breakdown voltage, the ESD circuit provides a low-resistance current path between the first and second nodes.
  • a bi-directional ESD circuit provides protection regardless of whether the voltage on the first node rises with respect to the second node, or the voltage on the second node rises with respect to the first node.
  • Conventional bi-directional ESD circuits typically include a combination of Zener diodes and high-breakdown-voltage avalanche diodes.
  • Zener diodes typically include a combination of Zener diodes and high-breakdown-voltage avalanche diodes.
  • One of the drawbacks to utilizing a conventional combination of Zener and avalanche diodes is that the metal lead, which is required to connect the Zener and avalanche diodes together, consumes a large amount of silicon real estate.
  • FIG. 1 shows a cross-sectional view that illustrates an example of a prior-art bi-directional ESD diode structure 100 .
  • diode structure 100 includes a p+ substrate region 110 , an n+ epitaxial region 112 that touches the top surface of p+ substrate region 110 , and a p+ region 114 that touches the top surface of n+ epitaxial region 112 .
  • Diode structure 100 also includes a trench isolation structure 116 that laterally surrounds a portion of p+ substrate region 110 , n+ epitaxial region 112 , and p+ region 114 .
  • Diode structure 100 further includes a non-conductive layer 120 that touches and lies over p+ region 114 , and a metal contact 122 that touches and extends through non-conductive layer 120 to make an electrical connection to p+ region 114 .
  • diode structure 100 includes a non-conductive layer 124 that touches and lies over non-conductive layer 120 and metal contact 122 . Further, non-conductive layer 124 has an opening 130 that exposes metal contact 122 .
  • p+ region 114 forms the anode and n+ epitaxial region 112 forms the cathode of a top Zener diode
  • p+ substrate region 110 forms the anode
  • n+ epitaxial region 112 forms the cathode of a bottom Zener diode, where the cathodes of the two diodes are connected together.
  • diode structure 100 consumes much less silicon real estate than a conventional combination of Zener and avalanche diodes.
  • diode structure 100 has a much higher capacitance than a conventional combination of Zener and avalanche diodes.
  • the dopant concentrations of substrate region 110 , n+ epitaxial region 112 , and p+ region 114 can be selected so that diode structure 100 has a capacitance of 14.7 pF, the top Zener diode has a breakdown voltage of ⁇ 6.5V, and the bottom Zener diode has a breakdown voltage of +11V.
  • Diode structures with a higher capacitance cannot be used with high-speed signal applications, such as USB 3.0 and HDMI 1.4.
  • a diode structure of the present invention includes a substrate region of a first conductivity type. The substrate region has a dopant concentration.
  • the diode structure also includes a first semiconductor layer of a second conductivity type. The first semiconductor layer has a dopant concentration, and touches and lies over the substrate region.
  • the diode structure additionally includes a second semiconductor layer of the first conductivity type. The second semiconductor layer touches and lies over the first semiconductor layer. The second semiconductor layer has a dopant concentration that is substantially less than the dopant concentration of the substrate region.
  • the diode structure further includes a third semiconductor layer of the second conductivity type. The third semiconductor layer touches and lies over the second semiconductor layer.
  • the diode structure includes a fourth semiconductor layer of the first conductivity type. The fourth semiconductor touches and lies over the third semiconductor layer.
  • the present invention also provides a method of forming a diode structure with ultra-low capacitance and a small size.
  • the method of the present invention includes epitaxially growing a first semiconductor layer on a substrate region.
  • the substrate region has a first conductivity type and a dopant concentration.
  • the first semiconductor layer has a second conductivity type and a dopant concentration.
  • the method also includes epitaxially growing a second semiconductor layer on the first semiconductor layer.
  • the second semiconductor layer has the first conductivity type and a dopant concentration that is substantially less than the dopant concentration of the substrate region.
  • the method further includes epitaxially growing a third semiconductor layer on the second semiconductor layer.
  • the third semiconductor layer has the second conductivity type.
  • FIG. 1 is a cross-sectional view illustrating an example of a prior-art bi-directional ESD diode structure 100 .
  • FIG. 2 is a cross-sectional view illustrating an example of a bi-directional ESD diode structure 200 in accordance with the present invention.
  • FIGS. 3A-3L are cross-sectional views illustrating an example of a method 300 of forming a bi-directional ESD diode structure in accordance with the present invention.
  • FIG. 2 shows a cross-sectional view that illustrates an example of a bi-directional ESD diode structure 200 in accordance with the present invention.
  • the capacitance of diode structure 100 is substantially reduced by forming a p ⁇ epitaxial layer to lie in-between two n+ epitaxial layers.
  • ESD diode structure 200 includes a p+ single-crystal-silicon substrate region 210 , an n+ epitaxial region 212 that touches the top surface of p+ substrate region 110 , and a p ⁇ region 214 that touches the top surface of n+ epitaxial region 112 .
  • ESD diode structure 200 also includes an n+ epitaxial region 216 that touches the top surface of p ⁇ epitaxial region 214 , and a p+ region 218 that touches the top surface of n+ epitaxial region 216 .
  • Diode structure 200 also includes a trench isolation structure 220 that laterally surrounds a portion of p+ substrate region 210 , n+ epitaxial region 212 , p ⁇ region 214 , n+ epitaxial region 216 , and p+ region 218 .
  • Diode structure 200 further includes non-conductive layer 222 that touches and lies over p+ region 218 , and a metal contact 224 that touches and extends through non-conductive layer 222 to make an electrical connection to the portion of p+ region 218 that is surrounded by trench isolation structure 220 .
  • diode structure 200 includes a non-conductive layer 226 that touches and lies over non-conductive layer 222 and metal contact 224 . Further, non-conductive layer 226 has an opening 230 that exposes metal contact 224 .
  • Diode structure 200 operates the same as diode structure 100 except that diode structure 200 has a substantially lower capacitance.
  • the dopant concentrations of the p+ substrate regions 110 and 210 are substantially the same, the dopant concentrations of the n+ epitaxial regions 112 , 212 , and 216 are substantially the same, the dopant concentrations of the p+ regions 114 and 218 are substantially the same, and the dopant concentration of p ⁇ epitaxial region 214 is substantially less than the dopant concentrations of p+ region 218 , diode structure 200 has a capacitance of 1.3 pF as compared to the 14.7 pF capacitance of diode structure 100 .
  • the top diode in diode structure 200 has a breakdown voltage of ⁇ 7.9V compared to the ⁇ 6.5V breakdown voltage of the top diode in diode structure 100 .
  • the bottom diode in diode structure 200 has a breakdown voltage of +15V compared to the +11V breakdown voltage of the top diode in diode structure 100 .
  • the diodes in diode structure 200 also have greater breakdown voltages.
  • FIGS. 3A-3L show cross-sectional views that illustrate an example of a method 300 of forming a bi-directional ESD diode structure in accordance with the present invention.
  • method 300 utilizes a conventionally-formed p+ single-crystal-silicon substrate region 310 , and begins by growing an epitaxial structure 320 on the top surface of substrate region 310 .
  • a hard mask can optionally be formed before epitaxial structure 320 is formed so that epitaxial structure 320 can be formed on only selected areas of a die.
  • Epitaxial structure 320 is grown in a conventional manner to have an n+ lower epitaxial layer 322 that touches and lies over p+ substrate region 310 , a p ⁇ middle epitaxial layer 324 that touches and lies over n+ lower epitaxial layer 322 , and an n+ upper epitaxial layer 326 that touches and lies over p ⁇ middle epitaxial layer 324 .
  • arsenic, antimony, or phosphorous can be implanted and annealed after n+ lower epitaxial layer 322 has been formed, and before n+ upper epitaxial layer 326 is formed. Implanting arsenic, antimony, or phosphorous controls the dopant concentration of n+ lower epitaxial layer 322 which, in turn, allows a variety of breakdown voltages to be obtained.
  • arsenic, antimony, or phosphorous can also be implanted and annealed after n+ upper epitaxial layer 326 has been formed. Implanting arsenic, antimony, or phosphorous controls the dopant concentration of n+ upper epitaxial layer 326 which, in turn, allows a further variety of breakdown voltages to be obtained.
  • P ⁇ middle epitaxial layer 324 has a dopant concentration that is, for example, lower than 1 ⁇ 10 16 atoms/cm 3
  • p+ substrate region 310 has a dopant concentration that is, for example, greater than 1 ⁇ 10 18 atoms/cm 3
  • p ⁇ middle epitaxial layer 324 lies completely between n+ lower epitaxial layer 322 and n+ upper epitaxial layer 326 .
  • a non-conductive layer 330 such as an oxide layer, is formed on the top surface of n+ upper epitaxial layer 326 .
  • a p ⁇ type dopant is implanted into n+ upper epitaxial layer 326 through non-conductive layer 330 at a dose that is sufficient to convert the top portion of n+ upper epitaxial layer 326 into a p+ layer 332 that touches and lies above the remainder of n+ upper epitaxial layer 326 .
  • the implanted dopants are then diffused using a conventional approach. Further, n+ upper epitaxial layer 326 lies completely between p ⁇ middle epitaxial layer 324 and p+ layer 332 .
  • Non-conductive layer 334 is formed on p+ layer 332 .
  • Non-conductive layer 334 can be implemented with, for example, tetraethyl orthosilicate (TEOS). TEOS can be deposited and then annealed for 20 minutes at 900° C. to make the film dense. Following this, a patterned photoresist layer 336 is formed on non-conductive layer 334 .
  • TEOS tetraethyl orthosilicate
  • Patterned photoresist layer 336 is formed in a conventional manner, which includes depositing a layer of photoresist, projecting a light through a patterned black/clear glass plate known as a mask to form a patterned image on the layer of photoresist to soften the photoresist regions exposed by the light, and removing the softened photoresist regions.
  • the exposed regions of non-conductive layer 334 , non-conductive layer 330 , p+ layer 332 , n+ upper epitaxial layer 326 , p ⁇ middle epitaxial layer 324 , n+ lower epitaxial layer 322 , and p+ substrate region 310 are etched in a conventional fashion to form a trench opening 340 .
  • Patterned photoresist layer 336 is then removed in a conventional manner, such as with an ash process.
  • Non-conductive layer 342 is deposited in a conventional fashion on non-conductive layer 334 to line trench opening 340 .
  • Non-conductive layer 342 can be implemented with, for example, a layer of oxide followed by a layer of TEOS.
  • a layer of polycrystalline silicon 344 is deposited in a conventional manner on non-conductive layer 342 to fill up trench opening 340 .
  • polycrystalline silicon is formed on both the front and back of the wafer, and removed from the back of the wafer using well-known materials and methods, such as with a plasma etch.
  • trench isolation structure 360 includes a polycrystalline silicon core 362 that is isolated from p+ substrate region 310 by a non-conductive structure 364 .
  • Non-conductive layer 370 is deposited in a conventional fashion on p+ region 332 .
  • Non-conductive layer 370 can be implemented with, for example, borophosphosilicate glass (BPSG) which has been deposited and densified.
  • BPSG borophosphosilicate glass
  • a patterned photoresist layer 372 is conventionally formed on non-conductive layer 370 .
  • patterned photoresist layer 372 As shown in FIG. 3H , after patterned photoresist layer 372 has been formed, the exposed portion of non-conductive layer 370 is etched in a conventional manner to form an opening 374 that exposes the top surface of p+ region 332 . Following the etch, patterned photoresist layer 372 is removed in a conventional fashion.
  • Metal layer 376 is formed to touch non-conductive layer 370 , fill opening 374 , and make an electrical connection with p+ region 332 .
  • Metal layer 376 can be implemented with, for example, a silicide layer, a layer titanium tungsten that touches and overlies the silicide layer, and a layer of aluminum that touches overlies the titanium tungsten layer.
  • the silicide layer can be implemented with, for example, platinum silicide, cobalt silicide, or titanium silicide.
  • the silicide layer is conventionally formed, such as by depositing a metal, sintering the metal to form a silicide structure on each single-crystal silicon and polycrystalline silicon region covered by the metal, and then removing the metal from the non-conductive regions of the wafer. After metal layer 376 has been deposited, a patterned photoresist layer 380 is conventionally formed on metal layer 346 .
  • patterned photoresist layer 380 As shown in FIG. 3J , after patterned photoresist layer 380 has been formed, the exposed portion of metal layer 376 is etched in a conventional manner to form a metal contact 382 that touches the top surface of p+ region 332 . Following the etch, patterned photoresist layer 380 is removed in a conventional fashion.
  • a non-conductive layer 384 is deposited to touch non-conductive layer 370 and metal contact 382 .
  • a patterned photoresist layer 386 is conventionally formed on non-conductive layer 384 .
  • patterned photoresist layer 386 As shown in FIG. 3L , after patterned photoresist layer 386 has been formed, the exposed portion of non-conductive layer 384 is etched in a conventional manner to form an opening 390 that exposes the top surface metal contact 382 . Following the etch, patterned photoresist layer 386 is removed in a conventional fashion to form a diode structure 392 . After this, method 300 continues with conventional steps.
  • bi-directional diode structure consumes substantially less silicon real estate than prior art bi-directional diode structures, and provides ultra-low capacitance by utilizing a p ⁇ epitaxial layer that touches and lies between two n+ epitaxial layers.

Abstract

A bi-directional electrostatic discharge diode structure consumes substantially less silicon real estate and provides ultra-low capacitance by utilizing a p− epitaxial layer that touches and lies between an n+ lower epitaxial layer and an n+ upper epitaxial layer. A metal contact touches and lies over a p+ layer, which touches and lies over the n+ upper epitaxial layer.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to bi-directional ESD diode structures and, more particularly, to a bi-directional ESD diode structure with ultra-low capacitance that consumes a small amount of silicon real estate.
  • 2. Description of the Related Art
  • An electrostatic discharge (ESD) circuit is a circuit that protects an integrated circuit from voltage spikes, which commonly occur when the integrated circuit is handled. In operation, an ESD circuit provides an open circuit between a first node and a second node when the voltage difference across the first and second nodes is less than a breakdown voltage.
  • However, when the voltage difference across the first and second nodes spikes up to be equal to or greater than the breakdown voltage, the ESD circuit provides a low-resistance current path between the first and second nodes. A bi-directional ESD circuit provides protection regardless of whether the voltage on the first node rises with respect to the second node, or the voltage on the second node rises with respect to the first node.
  • Conventional bi-directional ESD circuits typically include a combination of Zener diodes and high-breakdown-voltage avalanche diodes. One of the drawbacks to utilizing a conventional combination of Zener and avalanche diodes is that the metal lead, which is required to connect the Zener and avalanche diodes together, consumes a large amount of silicon real estate.
  • FIG. 1 shows a cross-sectional view that illustrates an example of a prior-art bi-directional ESD diode structure 100. As shown in FIG. 1, diode structure 100 includes a p+ substrate region 110, an n+ epitaxial region 112 that touches the top surface of p+ substrate region 110, and a p+ region 114 that touches the top surface of n+ epitaxial region 112.
  • Diode structure 100 also includes a trench isolation structure 116 that laterally surrounds a portion of p+ substrate region 110, n+ epitaxial region 112, and p+ region 114. Diode structure 100 further includes a non-conductive layer 120 that touches and lies over p+ region 114, and a metal contact 122 that touches and extends through non-conductive layer 120 to make an electrical connection to p+ region 114. In addition, diode structure 100 includes a non-conductive layer 124 that touches and lies over non-conductive layer 120 and metal contact 122. Further, non-conductive layer 124 has an opening 130 that exposes metal contact 122.
  • In operation, p+ region 114 forms the anode and n+ epitaxial region 112 forms the cathode of a top Zener diode, while p+ substrate region 110 forms the anode and n+ epitaxial region 112 forms the cathode of a bottom Zener diode, where the cathodes of the two diodes are connected together.
  • Thus, when the voltage on metal contact 122 spikes up with respect to the voltage on p+ substrate region 110 and exceeds the breakdown voltage of the bottom Zener diode, a discharge current flows from metal contact 122 to p+ substrate region 110. On the other hand, when the voltage on p+ substrate region 110 spikes up with respect to the voltage on metal contact 122 and exceeds the breakdown voltage of the top Zener diode, a discharge current flows from p+ substrate region 110 to metal contact 122.
  • One of the advantages of diode structure 100 is that diode structure 100 consumes much less silicon real estate than a conventional combination of Zener and avalanche diodes. However, one of the disadvantages of diode structure 100 is that diode structure 100 has a much higher capacitance than a conventional combination of Zener and avalanche diodes.
  • For example, the dopant concentrations of substrate region 110, n+ epitaxial region 112, and p+ region 114 can be selected so that diode structure 100 has a capacitance of 14.7 pF, the top Zener diode has a breakdown voltage of −6.5V, and the bottom Zener diode has a breakdown voltage of +11V. Diode structures with a higher capacitance, however, cannot be used with high-speed signal applications, such as USB 3.0 and HDMI 1.4. Thus, there is a need for a bi-directional ESD diode structure with a low capacitance that also consumes a small amount of silicon real estate.
    • SUMMARY OF THE INVENTION
  • The present invention provides a diode structure that consumes a small amount of silicon real estate and provides ultra-low capacitance. A diode structure of the present invention includes a substrate region of a first conductivity type. The substrate region has a dopant concentration. The diode structure also includes a first semiconductor layer of a second conductivity type. The first semiconductor layer has a dopant concentration, and touches and lies over the substrate region. The diode structure additionally includes a second semiconductor layer of the first conductivity type. The second semiconductor layer touches and lies over the first semiconductor layer. The second semiconductor layer has a dopant concentration that is substantially less than the dopant concentration of the substrate region. The diode structure further includes a third semiconductor layer of the second conductivity type. The third semiconductor layer touches and lies over the second semiconductor layer. In addition, the diode structure includes a fourth semiconductor layer of the first conductivity type. The fourth semiconductor touches and lies over the third semiconductor layer.
  • The present invention also provides a method of forming a diode structure with ultra-low capacitance and a small size. The method of the present invention includes epitaxially growing a first semiconductor layer on a substrate region. The substrate region has a first conductivity type and a dopant concentration. The first semiconductor layer has a second conductivity type and a dopant concentration. The method also includes epitaxially growing a second semiconductor layer on the first semiconductor layer. The second semiconductor layer has the first conductivity type and a dopant concentration that is substantially less than the dopant concentration of the substrate region. The method further includes epitaxially growing a third semiconductor layer on the second semiconductor layer. The third semiconductor layer has the second conductivity type.
  • A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set forth an illustrative embodiment in which the principals of the invention are utilized.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross-sectional view illustrating an example of a prior-art bi-directional ESD diode structure 100.
  • FIG. 2 is a cross-sectional view illustrating an example of a bi-directional ESD diode structure 200 in accordance with the present invention.
  • FIGS. 3A-3L are cross-sectional views illustrating an example of a method 300 of forming a bi-directional ESD diode structure in accordance with the present invention.
    •  DETAILED DESCRIPTION OF THE INVENTION
  • FIG. 2 shows a cross-sectional view that illustrates an example of a bi-directional ESD diode structure 200 in accordance with the present invention. As described in greater detail below, the capacitance of diode structure 100 is substantially reduced by forming a p− epitaxial layer to lie in-between two n+ epitaxial layers.
  • As shown in FIG. 2, ESD diode structure 200 includes a p+ single-crystal-silicon substrate region 210, an n+ epitaxial region 212 that touches the top surface of p+ substrate region 110, and a p− region 214 that touches the top surface of n+ epitaxial region 112. ESD diode structure 200 also includes an n+ epitaxial region 216 that touches the top surface of p− epitaxial region 214, and a p+ region 218 that touches the top surface of n+ epitaxial region 216.
  • Diode structure 200 also includes a trench isolation structure 220 that laterally surrounds a portion of p+ substrate region 210, n+ epitaxial region 212, p− region 214, n+ epitaxial region 216, and p+ region 218. Diode structure 200 further includes non-conductive layer 222 that touches and lies over p+ region 218, and a metal contact 224 that touches and extends through non-conductive layer 222 to make an electrical connection to the portion of p+ region 218 that is surrounded by trench isolation structure 220. In addition, diode structure 200 includes a non-conductive layer 226 that touches and lies over non-conductive layer 222 and metal contact 224. Further, non-conductive layer 226 has an opening 230 that exposes metal contact 224.
  • Diode structure 200 operates the same as diode structure 100 except that diode structure 200 has a substantially lower capacitance. When the dopant concentrations of the p+ substrate regions 110 and 210 are substantially the same, the dopant concentrations of the n+ epitaxial regions 112, 212, and 216 are substantially the same, the dopant concentrations of the p+ regions 114 and 218 are substantially the same, and the dopant concentration of p− epitaxial region 214 is substantially less than the dopant concentrations of p+ region 218, diode structure 200 has a capacitance of 1.3 pF as compared to the 14.7 pF capacitance of diode structure 100.
  • In addition, the top diode in diode structure 200 has a breakdown voltage of −7.9V compared to the −6.5V breakdown voltage of the top diode in diode structure 100. Further, the bottom diode in diode structure 200 has a breakdown voltage of +15V compared to the +11V breakdown voltage of the top diode in diode structure 100. Thus, in addition to providing a substantially lower capacitance, the diodes in diode structure 200 also have greater breakdown voltages.
  • FIGS. 3A-3L show cross-sectional views that illustrate an example of a method 300 of forming a bi-directional ESD diode structure in accordance with the present invention. As shown in FIG. 3A, method 300 utilizes a conventionally-formed p+ single-crystal-silicon substrate region 310, and begins by growing an epitaxial structure 320 on the top surface of substrate region 310. (A hard mask can optionally be formed before epitaxial structure 320 is formed so that epitaxial structure 320 can be formed on only selected areas of a die.)
  • Epitaxial structure 320 is grown in a conventional manner to have an n+ lower epitaxial layer 322 that touches and lies over p+ substrate region 310, a p− middle epitaxial layer 324 that touches and lies over n+ lower epitaxial layer 322, and an n+ upper epitaxial layer 326 that touches and lies over p− middle epitaxial layer 324.
  • Further, arsenic, antimony, or phosphorous can be implanted and annealed after n+ lower epitaxial layer 322 has been formed, and before n+ upper epitaxial layer 326 is formed. Implanting arsenic, antimony, or phosphorous controls the dopant concentration of n+ lower epitaxial layer 322 which, in turn, allows a variety of breakdown voltages to be obtained.
  • In addition, arsenic, antimony, or phosphorous can also be implanted and annealed after n+ upper epitaxial layer 326 has been formed. Implanting arsenic, antimony, or phosphorous controls the dopant concentration of n+ upper epitaxial layer 326 which, in turn, allows a further variety of breakdown voltages to be obtained.
  • P− middle epitaxial layer 324 has a dopant concentration that is, for example, lower than 1×1016 atoms/cm3, while p+ substrate region 310 has a dopant concentration that is, for example, greater than 1×1018 atoms/cm3. In addition, p− middle epitaxial layer 324 lies completely between n+ lower epitaxial layer 322 and n+ upper epitaxial layer 326. After epitaxial structure 320 has been formed, a non-conductive layer 330, such as an oxide layer, is formed on the top surface of n+ upper epitaxial layer 326.
  • As shown in FIG. 3B, after non-conductive layer 330 has been formed, a p− type dopant is implanted into n+ upper epitaxial layer 326 through non-conductive layer 330 at a dose that is sufficient to convert the top portion of n+ upper epitaxial layer 326 into a p+ layer 332 that touches and lies above the remainder of n+ upper epitaxial layer 326. The implanted dopants are then diffused using a conventional approach. Further, n+ upper epitaxial layer 326 lies completely between p− middle epitaxial layer 324 and p+ layer 332.
  • As shown in FIG. 3C, once the implant has been completed, a non-conductive layer 334 is formed on p+ layer 332. Non-conductive layer 334 can be implemented with, for example, tetraethyl orthosilicate (TEOS). TEOS can be deposited and then annealed for 20 minutes at 900° C. to make the film dense. Following this, a patterned photoresist layer 336 is formed on non-conductive layer 334.
  • Patterned photoresist layer 336 is formed in a conventional manner, which includes depositing a layer of photoresist, projecting a light through a patterned black/clear glass plate known as a mask to form a patterned image on the layer of photoresist to soften the photoresist regions exposed by the light, and removing the softened photoresist regions.
  • As shown in FIG. 3D, after patterned photoresist layer 336 has been formed, the exposed regions of non-conductive layer 334, non-conductive layer 330, p+ layer 332, n+ upper epitaxial layer 326, p− middle epitaxial layer 324, n+ lower epitaxial layer 322, and p+ substrate region 310 are etched in a conventional fashion to form a trench opening 340. Patterned photoresist layer 336 is then removed in a conventional manner, such as with an ash process.
  • As shown in FIG. 3E, once patterned photoresist layer 336 has been removed, a non-conductive layer 342 is deposited in a conventional fashion on non-conductive layer 334 to line trench opening 340. Non-conductive layer 342 can be implemented with, for example, a layer of oxide followed by a layer of TEOS. Next, a layer of polycrystalline silicon 344 is deposited in a conventional manner on non-conductive layer 342 to fill up trench opening 340. (In the present example, polycrystalline silicon is formed on both the front and back of the wafer, and removed from the back of the wafer using well-known materials and methods, such as with a plasma etch.)
  • Next, as shown in FIG. 3F, after polycrystalline silicon layer 334 has been deposited, polycrystalline silicon layer 334 and the non-conductive layers 334 and 330 are planarized to expose the top surface of p+ layer 322 and form a trench isolation structure 360 that laterally and completely surrounds a portion of p+ substrate region 310, n+ lower epitaxial layer 322, p− middle epitaxial layer 324, n+ upper epitaxial layer 326, and p+ region 332. The layers can be planarized using, for example, chemical-mechanical polishing or an etch back. Trench isolation structure 360 includes a polycrystalline silicon core 362 that is isolated from p+ substrate region 310 by a non-conductive structure 364.
  • As shown in FIG. 3G, following the formation of trench isolation structure 360, a non-conductive layer 370 is deposited in a conventional fashion on p+ region 332. Non-conductive layer 370 can be implemented with, for example, borophosphosilicate glass (BPSG) which has been deposited and densified. Once non-conductive layer 370 has been formed, a patterned photoresist layer 372 is conventionally formed on non-conductive layer 370.
  • As shown in FIG. 3H, after patterned photoresist layer 372 has been formed, the exposed portion of non-conductive layer 370 is etched in a conventional manner to form an opening 374 that exposes the top surface of p+ region 332. Following the etch, patterned photoresist layer 372 is removed in a conventional fashion.
  • As shown in FIG. 3I, after patterned photoresist layer 372 has been removed, a metal layer 376 is formed to touch non-conductive layer 370, fill opening 374, and make an electrical connection with p+ region 332. Metal layer 376 can be implemented with, for example, a silicide layer, a layer titanium tungsten that touches and overlies the silicide layer, and a layer of aluminum that touches overlies the titanium tungsten layer.
  • The silicide layer can be implemented with, for example, platinum silicide, cobalt silicide, or titanium silicide. In addition, the silicide layer is conventionally formed, such as by depositing a metal, sintering the metal to form a silicide structure on each single-crystal silicon and polycrystalline silicon region covered by the metal, and then removing the metal from the non-conductive regions of the wafer. After metal layer 376 has been deposited, a patterned photoresist layer 380 is conventionally formed on metal layer 346.
  • As shown in FIG. 3J, after patterned photoresist layer 380 has been formed, the exposed portion of metal layer 376 is etched in a conventional manner to form a metal contact 382 that touches the top surface of p+ region 332. Following the etch, patterned photoresist layer 380 is removed in a conventional fashion.
  • As shown in FIG. 3K, after patterned photoresist layer 380 has been removed, a non-conductive layer 384 is deposited to touch non-conductive layer 370 and metal contact 382. After non-conductive layer 384 has been deposited, a patterned photoresist layer 386 is conventionally formed on non-conductive layer 384.
  • As shown in FIG. 3L, after patterned photoresist layer 386 has been formed, the exposed portion of non-conductive layer 384 is etched in a conventional manner to form an opening 390 that exposes the top surface metal contact 382. Following the etch, patterned photoresist layer 386 is removed in a conventional fashion to form a diode structure 392. After this, method 300 continues with conventional steps.
  • Thus, a bi-directional diode structure and a method of forming the bi-directional diode structure have been described. The bi-directional diode structure consumes substantially less silicon real estate than prior art bi-directional diode structures, and provides ultra-low capacitance by utilizing a p− epitaxial layer that touches and lies between two n+ epitaxial layers.
  • It should be understood that the above descriptions are examples of the present invention, and that various alternatives of the invention described herein may be employed in practicing the invention. Thus, it is intended that the following claims define the scope of the invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.

Claims (20)

What is claimed is:
1. A diode structure comprising:
a substrate region of a first conductivity type, the substrate region having a dopant concentration;
a first semiconductor layer of a second conductivity type, the first semiconductor layer having a dopant concentration, and touching and lying over the substrate region;
a second semiconductor layer of the first conductivity type, the second semiconductor layer touching and lying over the first semiconductor layer, the second semiconductor layer having a dopant concentration that is substantially less than the dopant concentration of the substrate region;
a third semiconductor layer of the second conductivity type, the third semiconductor layer touching and lying over the second semiconductor layer; and
a fourth semiconductor layer of the first conductivity type, the fourth semiconductor touching and lying over the third semiconductor layer.
2. The diode structure of claim 1 wherein the third semiconductor layer has a dopant concentration substantially equal to the dopant concentration of the first semiconductor layer.
3. The diode structure of claim 2 wherein the fourth semiconductor layer has a dopant concentration substantially equal to the dopant concentration of the substrate region.
4. The diode structure of claim 3 and further comprising a metal contact that touches and lies over the fourth semiconductor layer.
5. The diode structure of claim 4 wherein the second semiconductor layer lies completely between the first semiconductor layer and the third semiconductor layer.
6. The diode structure of claim 5 wherein the third semiconductor layer lies completely between the second semiconductor layer and the fourth semiconductor layer.
7. The diode structure of claim 6 and further comprising a trench isolation structure that touches and laterally surrounds a portion of the substrate region, the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer.
8. The diode structure of claim 7 wherein the trench isolation structure includes a polycrystalline silicon core and an isolation structure that lies between the polycrystalline silicon core and the substrate region.
9. The diode structure of claim 7 and further comprising:
a first non-conductive layer that touches and lies over the fourth semiconductor layer; and
a second non-conductive layer that touches and lies over the first non-conductive layer.
10. The diode structure of claim 9 wherein the metal contact touches and lies over a portion of the first non-conductive layer.
11. A method of forming a diode structure comprising:
epitaxially growing a first semiconductor layer on a substrate region, the substrate region having a first conductivity type and a dopant concentration, the first semiconductor layer having a second conductivity type and a dopant concentration;
epitaxially growing a second semiconductor layer on the first semiconductor layer, the second semiconductor layer having the first conductivity type and a dopant concentration that is substantially less than the dopant concentration of the substrate region; and
epitaxially growing a third semiconductor layer on the second semiconductor layer, the third semiconductor layer having the second conductivity type.
12. The method of claim 11 and further comprising implanting a dopant of the first conductivity type into the third semiconductor layer to form a fourth semiconductor layer that touches and lies over the third semiconductor layer, the fourth semiconductor layer having the first conductivity type.
13. The method of claim 12 wherein the third semiconductor layer has a dopant concentration that is substantially equal to the dopant concentration of the first semiconductor layer.
14. The method of claim 13 wherein the fourth semiconductor layer has a dopant concentration that is substantially equal to the dopant concentration of the substrate region.
15. The method of claim 14 wherein the second semiconductor layer lies completely between the first semiconductor layer and the third semiconductor layer.
16. The method of claim 15 wherein the third semiconductor layer lies completely between the second semiconductor layer and the fourth semiconductor layer.
17. The method of claim 16 and further comprising forming a trench isolation structure that touches and laterally surrounds a portion of the substrate region, the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer.
18. The method of claim 17 and further comprising:
forming a first non-conductive layer that touches and lies over the fourth semiconductor layer; and
forming a metal opening that extends through the first non-conductive layer to expose the fourth semiconductor layer.
19. The method of claim 18 and further comprising:
depositing a metal layer that touches and lies over the first non-conductive layer, and fills up the metal opening; and
etching the metal layer to form a metal contact that touches and lies over the fourth semiconductor layer.
20. The method of claim 19 and further comprising:
forming a second non-conductive layer that touches and lies over the first non-conductive layer and the metal contact; and
forming a contact opening that extends through the second non-conductive layer to expose the metal contact.
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