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Publication numberUS2429228 A
Publication typeGrant
Publication dateOct 21, 1947
Filing dateJun 11, 1945
Priority dateJun 11, 1945
Publication numberUS 2429228 A, US 2429228A, US-A-2429228, US2429228 A, US2429228A
InventorsHerbst Philip J
Original AssigneeRca Corp
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Electronic computer
US 2429228 A
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Description  (OCR text may contain errors)

Oct. 2l, .1947. P. J. HERBST 2,429,228

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attorney Oct. 21, 1947. P. J. HERBST 2,429,228

ELECTRONIC `COMPUTER :Slwcntor Igerfi @L22 dttorum Oct. 2l, 1947.

P. J. HERBST ELECTRONIC COMPUTER Filed June 11, 1945 4 Sheets-Sheet 3 06f. 2l, 1947. P, HERBST 2,429,228

ELEcTRoNIc COMPUTER Filed June 11, 1945 4 sheets-sheet 4 (0m/.Ayia zal,

"0xff-#Q22 /fwirfo-AMA 7 ,Q jup/sar Elly. +o' (Hf/a) /Nmerfo (M+ )ga/Mey (e): @www /fv r//vf 77H5 raf/v4@ foro/@M64 l T R NVEN O ATTORNEY Patented Oct. 21, 1947 ELECTRONIC COIVIPUTER Philip J. Herbst, Princeton, N. J., assignor to Radio Corporation of America, a corporation of Delaware Application June 11, 1945, Serial No. 598,702

(Cl. 23S-61) 20 Claims.

This application is a continuation-in-part of my copending application Serial No, 488,801, filed May 26, 1943, for Electronic computer.

This invention relates generally to electronic computers and more particularly to an electronic computing system for deriving the product of at least two quantities, each f which are represented by separate groups of voltages characteristic of the binary values of each of the quantities.

The binary system of computation is particularly suited to electronic computation, since a complete binary term of a binary number may be expressed in terms (a) of conducting condition or (b) of the cut-off condition of the anode circuit of a conventional Vacuum tube. A saving in the number of tubes required for a given quantity is also possible in a ratio of 3:1 over a numerical system utilizing a radix of 10. Furthermore, binary quantities may be expressed in terms of voltage pulse trains having pulses of unit magnitude which are indicative of the presence of a binary 1 term and the absence of unit magnitude pulses indicative of binary 0 terms. A description of the binary system of computation may be found in Elementary Number Theory, by Uspenski and Heaslet.

` Briefly, the instant invention comprises two distinct methods of deriving the product of two quantities by means of the systems described in detail hereinafter.

First method The rst method comprises generating a pulse train in which unit magnitude pulses bear a time relation indicative of the binary number corresponding to one of the quantities. For example, the binary numberllOl would be represented by a pulse train having two unit magnitude pulses separated by the width of a pulse, followed at an interval of three pulse widths by a third unit magnitude pulse. The pulses will therefore correspond to binary 1 terms and the absence of a pulse between the second and third pulses would correspond to a binary 0 term. The multiplicand would be represented by a pulse train, of the type described, which would be applied to a group of cascaded delay circuits each of which provides a delay equal to the pulse period.

A plurality of blocking ampliers are connected to the delay circuits in a manner whereby the pulse train applied to successive delay circuits also is applied to the control electrodeof a corresponding one of the blocking amplifiers. The respective blocking amplifiers are connected to a plurality of switches whereby normal bias, or cut-olf bias, may be applied to each of the respective amplifiers. Cut-ofi bias is applied to an ampliiier if a corresponding term of the multiplier is binary 0, while normal bias is applied thereto if the corresponding term of the binary multiplier is binary 1. Therefore, if the binary multiplier is 1001, the first and fourth blocking amplifiers would receive norma1 bias, while the second and third ampliers would be biased beyond anode current cut-oil'.

The amplifiers will therefore be non-conductive except at such times as a pulsevofthe applied multiplier pulse train is applied to the control electrode of one of the normally biased amplifiers.

In Athe latter instance, the anode circuit of the normally biased amplifier will include a pulse train indicative of the corresponding sub-total of the multiplication process. Sub-total pulse trains derived from the first two blocking amplifiers may be added by means of a pulse train adding circuit of the type described in applicants copending U. S. application Serial No. 485,308, filed May 1, 1943. Similarly, the output pulse train derived from the rst adding circuit is applied to a second similar adding circuit which also receives a sub-total pulse train from the third blocking amplifier. The output pulse train of the second adding circuit is combined with the sub-total output pulse train of the fourth blocking amplifier and applied to a third adding circuit, This process is continued through additional adding circuits until the output pulse trains- Second method The second method includes means for generating separate pulse trains indicative of the binary values of each of the quantities to be multiplied. These pulsetrains are applied at opposite ends of a group of cascaded delay networks in which each network provides a delay equal to one-half of the pulse period of the pulse trains. A plurality of blocking amplifiers which are normally biased beyond anode current cut-oil condition, are respectively connected to the input of each successive delay network. The various blocking amplifiers are arranged to pass no anode current except when unit magnitude pulses from both the multiplier and the multiplicand applied pulse trains coincide in time on the control electrode of the respective ampliers. The pulse trains derived from the anode circuits of each of the blocking amplifiers are combined in pulse train adding circuits of the type disclosed in applicants copending application mentioned heretofore, in the same manner as described heretofore for applicants first method of multiplication.

Among the objects of the invention are to provide an improved method of and means for deriving electronically the product of tWo quantities. Another object of the invention is to provide an improved method of and means for generating voltage pulse trains characteristic ci.' the binary value of one or more quantities and combining said pulse trains to provide an output pulse train characteristic of the binary value of the product of said quantities. Another object of the invention is to provide an improved method of and means for deriving the product of two quantities wherein one of said quantities is represented by a pulse train indicative oi the binary value of said quantity, the other oi said quantities is represented by different values oi bias voltages applied to a plurality of cascaded blocking amplifiers, said pulse train is applied to said amplifiers at successive time intervals, and pulse trains derived from each of said amplifiers are combined to provide an output pulse train indicative of the binary value of the product of said quantities.

An additional object of the invention is to provide an improved method of and means for generating separate pulse trains indicative of the binary values of two quantities, delaying each of said pulse trains, combining said pulse trains to derive sub-total pulse trains and lcombining said sub-total pulse trains; to derive an output pulse train which is indicative of the binary value of the product of said quantities. An additional object of the invention is to provide an improved method of andlmeans for deriving electronically the product of two quantities which are represented by separate groups of voltages indicative of the binary values of said quantites, deriving an output pulse train indicative of the productV of said quantities and indicating said product.

The invention will be described in further detail by reference to the accompanying drawings of which Figure 1 is a schematic circuit diagram of a pulse train generator; Figure 2 is a schematic circuit diagram of one embodiment/of applicants multiplying system; Figure 3 is a schematic circuit diagram of a second embodiment of applicants multiplying system; Figure 4 is a family of graphs indicating the circuit operation of Figure 2; Figure 5 is a family of graphs indicating the circuit operation of Figure 3; Figure 6 is a schematic circuit diagram of the adding circuit forming a component of the circuits of both Figure 2 and Figure 3; Figure 'l is a family of graphs indicative of th'e circuit operation of Figure 6; Figure 8 is a schematic circuit diagram of a binary indicator; and Figure 9 is an elevational view of the type of indication provided thereby on a cathode ray oscilloscope. Similar reference numerals are applied to similar elements throughout the drawing.

Apparatus for first multiplier method Referring to Figure 1, a pulse train generator, for deriving pulse trains indicative of a particular quantity to be multiplied, includes a source of voltage such as, ior example, a battery I, which is connected to a capacitor 2 through a series resistor 3 in such a manner that a capacitor 2 is normally charged by the voltage source I. A plurality of delay circuits 4, 5, 6, 1, 8 are connected in cascade arrangement. The ilrst delay circuitI 4 is connected through a first switch 9 to the common terminals of the capacitor 2 and the resistor 3. The input of the iirst delay circuit 4 is also connected, through a second resistor I0, to the common grounded terminals of the battery I and the capacitor 2. One output terminal il is grounded, and a second output terminal I2 is connected to the input and output circuits of the various delay networks through separate output switches I3, I4, I5, I6, I1, I8 and I9, respectively.

In operation, if a pulse train corresponding to the number IIIlI is desired, the switches I3, I5 and IB are closed. When the switch 9 is closed, a single pulse train having the desired characteristics may be derived from the output terminals II, I2, which are connected effectively across the second, or load, resistor I3. If then the switch 9 is opened, the capacitor 2 will again be charged by the voltage source I. A second voltage pulse train having characteristics determined by the positions of the output switches I3, I4, I5, I6, I1, I8 and I9 may thereafter be derived from the output terminals- I I, I2 when the switch 9 is again closed.

In Figure 2 the output pulse train, derived from the circuit of Figure l, is applied to input terminals II', I2' which apply the pulses to the control electrode of a rst blocking ampliiler 2I and to the input of the first of a plurality of serially connected delay circuits 22, 23, 24, 25, 26 and 21. The delay provided by each of the delay circuits is equivalent to the pulse period of the pulse train. The control electrode of a second blocking ampliiier 28 is connected to the output of the iirst delay circuit 22. The anode circuits of the iirst and second blocking amplifiers 2|, 28, respectively, are connected to the input of a rst pulse train adding circuit 29, which will be described in detail hereinafter.

Similarly, the output of the second delay circuit 23 is applied to the control electrode of a third blocking ampliier 3Il, and the outputs of the third, fourth, fifth, and sixth delay circuits 24, 25, 26, 21, respectively, are connected to the control electrodes of the fourth, iifth, sixth, and seventh blocking ampliers 3I, 32, 33 and 34, respectively. The anode circuit of the third blocking amplier 3U and the output of the first pulse train adding circuit 29 are applied to the input of a second pulse train adding circuit 35. Similarly, the anode circuit of the fourth blocking ampliilerSI and the output of the second pulse train adding circuit 35 are applied to the input of a third pulse train adding circuit 3S. The anode circuit of the fifth blocking amplier 32 and the output of the third adding circuit 36 are applied to the input of a fourth adding circuit 31. Likewise, the anode circuit of the sixth blocking amplifier 33 and the output of the fourth adding circuit 31 are applied to the input of the fth adding circuit 38. Also, the anode circuit of the seventh blocking amplifier 34 and the output of the fifth adding circuit 38 are applied to the input of the sixth adding circuit 39. The output of the sixth adding circuit 39 is connected to the output terminals 40 from which a pulse train may be derived which' is characteristic of the binary number corresponding to the product. An indicator 4I, which may be of the type described in the circuit of Figure 6, may

l be connected across the output terminals 40, if the product is to be indicated directly.

The control electrode circuits of the blocking amplifiers 2l, 28, 30, 3|, 32, 33 and 34 are connected to grid resistors 42, 43, 44, 45, 46, 41 and 48, respectively. The remaining terminals of the grid resistors are each connected to the movable contacts of one of a plurality of bias control switches 49, 50, 5|, 52, 53, 54 and 55, respectively. One of the fixed contacts of each of the bias control switches is grounded, and the remaining fixed contacts of these switches are connected to the negative terminal of a source of bias voltage, 56. The positive terminal of the source of bias voltage is grounded. The cathodes of all of the blocking amplifiers also are grounded.

Mode of operation--Method I The pulse train applied to the input terminals I I', I2' is indicative of the value of the binary number corresponding to the multiplicand. The position of the bias control switches 49, 50, 5|, 52, 53, 54 and 55 is indicative of the value of the binary number corresponding to the multiplier. For example, if the multiplier is the binary number IUII, switches 49, 50, and 52 (because the switches are set up from right to left) will be connected to the grounded contact, and switches 5I, 53, 54 and 55 will be connected to the contacts which are at negative potential derived from the voltage source 56. The value of this negative potential is selected to provide anode current cut-off of all blocking amplier tubes to which it is applied. It should be understood that the number of delay circuits, blocking amplifiers and adding circuits required will depend upon the number of binary digits in the numbers to be multiplied.

In operation, the multiplicand pulse train applied to the input terminals II', I2 will provide anode current only in the blocking ampliers 2|, 28, 3|, of which the bias control switches 49, 50, 52 are at ground potential. The pulse train in the output of these normally biased amplifiers will be of magnitude proportional to the magnitude of the applied pulse train and the time relation thereof will be dependent upon the total delay provided by the delay circuits intermediate the input terminals and the particular tube control electrode. The voltage pulse trains in the anode circuits of the respective blocking amplifiers will be combined or added in the adding circuits as described in detail hereinafter. It will be seen that only two pulse trains are -applied to each adding circuit, and that these pulse trains are derived from either two blocking amplifier anode circuits, or from one anode circuit and a preceding pulse train adding circuit.

Eample.' Product of 13 11 (binary 1101 X binary Figure 4 is a family of graphs indicating the progress of the applied pulse train through the several blocking amplifiers, delay circuits and adding circuits described herein for the circuit of Figure 2. It is assumed that the switches 49, 5| and 52 are connected to the grounded contacts thereof, so that the blocking amplifiers 2|, 30 and 3| are supplied with normal grid bias. Therefore, the blocking amplifiers 28, 32, 33 and 34 would be biased by the voltage from the source 56 and would not be responsive to the pulse train.

Graph (a) shows the first pulse of the pulse 2|. Graph i illustrates the fact that no pulse train is transmitted by the overbiased second blocking amplifier 28. Graph 7' illustrates the combined pulse train derived from the firsty add' ing circuit 29, which pulse train is equivalent to the sum of the pulse trains shown in graphs h and i. Graph k shows the pulse train derived from the third blocking amplifier 30. Graph l shows the combined pulse train in the second adding circuit 35 which is equivalent to the sum of the pulse trains derived from the third blocking amplifier and the first adding circuit 29. Graph m is the pulse train derived from the output of the second adding circuit 35 after the carryover of the double magnitude pulse in graph l.

Graph n is the pulse train derived from the fourth blocking amplifier tube 3 I. Graph o is the pulse train in the third adding circuit 36 whichv is equivalent to the sum of the pulse trains derived from the fourth amplifier 3| and the second adding circuit 35. Graph p is equivalent to graph o after the first carryover of the double amplitude pulse in graph o. Graph q is equivalent to graph p after the carryover of the double amplitude pulse in graph p; and graph ris equivaient to graph q after the carryover of the double amplitude pulse of graph q.

Since the fifth, sixth and seventh blocking amplifiers 32, 33, 34 do not-transmit the pulse train, the pulse train represented by graph r is merely repeated through the fourth, fifth and sixth adding circuits 31, 38, 39. It may be derived from the output terminals 40, or indicated on the indicator 4|. The time relation is indicated by the scale below graph r, and the equivalent binary number 10001111, corresponding to the product, may be derived by reading the pulse train r on a reversed time scale; i. e., from right to left.

Apparatus ,for second multiplier method Figure 3, comprising the circuit required for performing applicants second method, includes a first pair of input terminals 60, to which are applied a pulse train characteristic of one of the quantities to be multiplied. The circuit also includes a second pair of input terminals 6I to which are applied, simultaneously with the application of the first pulse train to the terminals 60, a second pulse train characteristic of the binary value of the second number to be multiplied. The simultaneous application of both pulse trains may be effected by gauging the control switches 9 of the two pulse generating circuits of the type described in Fig. l. A plurality of delay networks 62, 63, 64, 65, 66, B7, 68, 69, each providing a delay equal to one half the pulse period of the of a source of bias potential 13. I'he positive terminal of the source of bias potential 18 is grounded. and the value of the bias voltage is selected to provide anode current cut-od in the absence of the coincidence of applied voltage pulses of both of the pulse trains.

Similarly, the control electrode of a second blocking ampliiier tube 14 is connected to the output of the first delay network 62, the control electrode of a, third blocking amplifier 15 is connected to the output of the second delay network 63, andthe control electrodes of fourth, ilfth, sixth, seventh and eighth blocking amplifiers 16, 11, 18, 19, 88, respectively. are connected to the output of the third, fourth, fifth, sixth and seventh delay networks 64, 65, 66, 81, and 88, respectively. The control electrode of the ninth blocking amplier 8| is connected to the ungrounded terminal 8| of the eighth delay network 69. Similarly, the control electrodes of the blocking amplifiers 18, 11, 18, 19, 88, and 8| are connected through separate grid resistors to the negative terminal of the source of bias potential 13. The cathodes of all of the blocking ampliiiers are grounded.

The anode circuits of the iirst and second blocking amplifiers *1|, 14 are connected to the input of a first pulse train adding circuit 82. The output of the first pulse train adding circuit 82, and the anode circuit of the third blocking amplifier 15 are connected to the input of a second pulse adding circuit 83. The output of the second pulse train adding circuit 83 and the anode circuit of the fourth blocking amplifier 16 are connected to the input of a third pulse train adding circuit 84. Similarly, the output of the third pulse train adding circuit 84 and the anode circuit of the fth blocking amplifier 11 are applied to the input of a, fourth pulse train adding circuit 85. Also, the output of the adding circuit 85 and the anode circuit of the tube 18 are applied to the input of a fth pulse train adding circuit 88. The output of the adding circuit 86 and the anode circuit of the tube 18 are applied to the inputof a sixth pulse train adding circuit 81. The output of the sixth adding circuit 81 and the anode circuit of the eighth blocking amplier tube 80 are applied to the input of a seventh pulse train adding circuit 88. Similarly, the output of the seventh adding circuit 88 and the anode circuit of the last amplifier tube 8| are applied to the input of an eighth pulse train adding circuit 89. -The output of the last pulse train adding circuit 89 is applied to the output terminals 98, to derive therefrom an output pulse train which is characteristic of the binary number corresponding to the product of the two quantities to be multiplied. An indicator 9| may be connected across the outputterminals 88 if the product is to be indicated directly. The pulse train adding circuits 82, 83, 84, 85, 86, 81, 88 and 89, and the indicator 9| are each of the types described in detail hereinafter in the circuit of Figure 6. It should be understood that the number of delay networks, blocking amplifiers and adding circuits will depend upon the nurnber of binary digits of the numbers to be multiplied. In practice there necessarily will be one more blocking amplifer than delay network in order to combine fully delayed pulse trains traveling in both directions.

Mode of operation-Method II In operation, a, pulse train corresponding to the binary multipllcand is applied to the input terminals B8, while simultaneously a pulse train corresponding to the binary multiplier is applied to the other input terminals 8|. The two pulse trains are each delayed intervals equivalent to one half the pulse period as they progress in opposite directions through each of the delay networks. When pulses in both trains coincide in time at the input of any of the blocking ampliers, the particular amplifier provides a unit magnitude pulse in its output circuit, which unit pulse is applied to the particular pulse train adding circuit connected thereto.

The several pulse train adding circuits 82, 83, 84, 85, 88, 81, 88 and 89 are so connected in series and to the separate blocking ampliers that the proper time relations and carryovers are maintained for the unit pulses transmitted thereto by the several blocking amplifiers. The resultant pulse train derived from the output circuit of the last adding circuit 89 corresponds in magnitude and time relation to the value of the binary product.

Example: Product of 13x11 (binary 1101 Xbinary 1011) Figure 5 is illustrative of the progress of the two pulse trains applied respectively to the input terminals 68 and 6| of the circuit of Figure 3. The position of the blocking ampliers and delay circuits are indicated by the numbered circles and squares, respectively, at the upper portion of the family of graphs. The time intervals are indicated on the right hand margin of the family of graphs. The pulse train applied to the input terminals 88 is read as a binary number from left to right, while the pulse train applied to the input terminals 8| is read as a binary number from right to left.

Graph a illustrates the two pulse trains applied simultaneously to the end blocking ampliers 1|, 8|, respectively. Graph b illustrates the progress of the two pulse trains to the ampliilers 14, 88, respectively at a time delay of one half the pulse period. Graphs c, d, e, j, g, h, i, d, lc, Z, and m indicate successive progress of the two pulse trains toward the opposite ends of the bank of blocking ampliilers. The successive graphs indicate conditions at time intervals of one half the' pulse period. The encircled pulses of the graphs e, f, y, h., i, y and lc indicate the concidence of pulses in a particular blocking amplifier whereby the amplier is caused to transmit a pulse to the adding circuit connected thereto.

Graph n indicates that no pulses are transmitted by the rst blocking amplifier 1|, Graph o indicates that a single pulse is transmitted by the second blocking amplifier 14 at a time interval of '1/2 the pulse period, Graph p indicates the pulse derived from the first adding circuit 82 in response to the single pulse derived from the blocking amplifiers 1i and 14. Graph q indicates that no pulses are derived from the third blocking amplliier 15. Graph r indicates the single pulse which is therefore transmitted by the second adding circuit 83 in response to the single pulse applied thereto from the first adding circuit 82.

Graph s indicates the two pulses derived from the fourth blocking amplifier 16. Graph t indicates the three pulses derived from the third adding circuit 84 in response to the two pulses from the fourth amplifier 18 and the single pulse from the second adding circuit 83.

Graph u indicates the two pulses derived from the fth blocking amplifier 11, while graph v indi- Cates thedve pulses derived from the fourth adding circuit 85 in response to the two pulses from the fifth amplifier Tl and the three pulses from the .third adding circuit 84,

Graph w indicates the single pulse derived from the sixth blocking ampliiier 18 while graph :c indicates the output pulse train from the fifth adding circuit 86 in response to the pulse trains 'u and w applied thereto. It will be seen that the coincidence of two pulses in the graphs v and w has provided a carryover to the next pulse period.

Graph y indicates the two pulses derived from the seventh blocking amplifier 19 whilegraph z indicates the pulse train derived from the sixth adding circuit 81 in response to the applied pulse trains :c and y. It will be seen that three successive carryovers occurred in the adding circuit 81.

Graph a2 indicates the single pulse derived from the eighth blocking amplifier 80, while graph b2 indicates the pulse train derived from the seventh adding circuit, 88 in response to applied pulse trains represented by the graphs z and a2.

Graph c2 indicates that no pulses are transmitted by the last blocking amplifier 8| while graph d2 indicates the output pulse train derived from the last adding circuit 89 which is identical to that derived from the seventh adding circuit 88. The output pulse train may be derived from the output terminals 90 or indicated on the indicator 9|.. It corresponds to the binary number 10001111 represented by the pulse train represented by graph d2 on a reversed time scale-i. e., reading from right to left.

These rvarious steps are set forth in the following tabulation wherein the rst column shows the reference numerals of the various tubes, the second column shows the times at which these tubes conduct, the third column shows the output pulses, and the fourth column shows the carry pulses:

Output Method of adding pulses 'Ihe principle employed is the summation of the pulses representing the numbers to be added, the generation of a control pulse train having pulses whenever the pulse train representing the summationI exceeds the amplitude of one pulse and in which the amplitudes of the pulses in the control train are all of the same magnitude, the delay of this control train by a time equal to the interval between pulses in the train. The addition of this delayed train to the input so as to represent the carryover from one digit to the next and the subtraction of the undelayed control train from the total sum to accomplish the cancellation of pulses of double magnitude.

Brieily, the system comprises an improved method and means for adding the magnitudes of the voltage pulses of each of the input pulse trains to derive therefrom a combined pulse train. To the combined pulse train is added a delayed pulse train representing the carryover counts in the binary addition to derive a rst control pulse train representing the binary sum but not in proper form for normal use. The first control pulse train may contain pulses of zero, unity. double or triple amplitude. The method employed consists in utilizing these amplitudes to produce a pulse train representing the binary sum in correct form as follows: Amplltudes of unity produce a count in the output puise train but introduce no carryover pulse in the circuit, double amplitudes produce a carryover pulse but no count in the output train, pulses. of triple amplitude produce both carryover and count pulses. To accomplish this the rst control pulse train is clipped at unit amplitude and limited at double amplitude to derive a second control pulse train which represents the carryover pulses used which is delayed and added to the combined pulse train as previously described to produce the rst control pulse train. The second control pulse train is amplied to derive a third control pulse train of double amplitude. Y The third control pulse train is combined in opposing polarity with the first control pulse train to derive a fourth pulse train which is characteristic ofthe sum of the binary numbers to be added. The fourth pulse train may be applied to additional computing apparatus or the sum may be indicated directly.

The two pulse trains to be added are impressed upon the input of a thermionic tube circuit having a common load, to derive therefrom the first combined pulse train. The combined pulse train is applied to the grid of a conventional amplier stage to which the delayed pulse train representing the carryover operation is also applied. The output of this stage constitutes the rst control puise train and is applied to a clipping-limiting stage, the output of which consists only of pulses of unit magnitude occurring whenever the magnltude of the pulses in the first control pulse train exceed unity and comprising the second control puise train. This second control pulse train is applied to a conventional delay circuit which delays its pulses an amount equal to the time interval between pulses. The delayed pulses are combined with the combined pulse train to derive the ilrst control pulse train as previously described. 'I'he second control pulse train is also applied to a conventional amplier to derive a third control pulse train of double amplitude. The rst and third control pulse trains are applied to the inputs of a summing stage. Since the pulses are applied in opposing polarity the pulses of the third control pulse train will tend to cancel those of the nrst control pulse train. However, for amplitudes of zero or unit magnitude in the rst control pulse train, nopulses are present in the third, while for pulses of triple magnitude in the rst, the presence of the double amplitude pulse in the third control train produces a partial cancellation which results in a pulse of unit amplitude in the output. When the pulse in the rst control train is of double amplitude the cancellation is complete. The output of the summing stage is the fourth pulse train and represents the binary sum.

Apparatus for ladding pulses Referring to Figure 6 of the drawing, a voltage pulse train illustrated by Fig. 7a, corresponding to the number 59 expressed in terms of the binary number 111011, is applied to the input terminals |02 which are connected to the input of a first amplifier tube |03. A voltage pulse train y, corresponding to the quantity 25 in terms of the corresponding binary number 11001, is applied to a second group of input terminals |04 which are connected to the input of a second amplier tube ll |05. The anode circuits of the first and second amplifier tubes |03, |05, respectively, include a common load resistor |06 which is connected to a source of operating potential (not shown). The anodes of the ampliiler tubes |03, |05 are connected, through an isolating capacitor. |01, to the control electrode of an amplifier tube |08, which inverts the polarity of the combined pulse train derived from the amplifier tubes |03, |05 and the output of the delay network H5. The output of the amplier tube |08 is applied to the control electrode of a rst limiter-inverter tube |09. The control electrode bias potential of tube |09 is selected so as to provide a threshold which will permit pulses of double and triple amplitude lmpressed on the input to produce an output in the plate circuit but discriminates against pulses of unit amplitude, The plate circuit of tube |09 is chosen so as to limit the amplitude of the pulses in the output to a fixed amplitude for all input pulses of double amplitude or greater. Figs. 3 and 4 of applicants copending application Ser. No. 598,7 01 show the mutual characteristic of tube |09 and illustrate the clipping and limiting action of this tube. The plate current limiting is realized by employing a very high resistance ||4 in the plate circuit. Other methods, such as reducing the applied plate voltage could be used.

The control electrode bias potential may be derived from a battery connected, through a grid resistor to the control electrode of the limiter-clipper-inverter tube |09. As an added refinement to accommodate wide variation in pulse rate without shifting of the location of the pulse peaks on the mutual characteristic, a means of maintaining the base line of the input pulses may be employed. This means may take the form of a rectifier or similar locking circuit. One form of this circuit is shown in Fig. 7 of the above copending application which has the same ling date as the present application. This refinement is not essentialif the pulse width is small compared to the spacing or if the width of the mutual characteristic is small compared to the pulse amplitude, i. e., if the shift in the A.C. axis of the pulse train is not suiclent to cause a change in the limiting clipping action of tube |09. The output of tube |09 represents the carryover count in the binary addition and will henceforth be designated as the second control pulse train c.

The second control pulse: train c is applied to the control electrode of an inverter amplifier tube ||2. This amplification of this tube is established by selection of the values of its associated circuit components so that the pulse train in its output signal has a constant magnitude of double amplitude. This may -be further insured by providing limiter-clipper action similar to tube |09 but is not essential to the fundamental operation of the circuit. The output of tube ||2 represents the cancellation terms in the binary addition and will henceforth be designated as the third control pulse train d.

The second control pulse train c also is applied, through a conventional delay circuit ||5, to the control electrode of the rst inverter tube |08. The delay provided in the delay circuit I corresponds to the period of the pulses of the applied voltage pulse trains. The resultant pulse train applied to the control electrode of the first inverter tube |08 will, therefore, represent the sum of the applied pulse trains and the delayed second control pulse train, and will hereinafter be designated as the rst control pulse trarn a.

The rst control pulse train a is applied to a delay circuit H6, which delays the pulse train an amount equivalent to the total delay in the circuits associated with the inverter and limiter tubes |08, |09 and ||2. The output of the delay circuit ||6 is applied to the control electrode of a triode The third control pulse train d is applied to the control electrode of a` triode H8. The triodes ||8, respectively, include common cathode and anode circuits and are selfbiased by means of a cathode resistor ||9 and cathode bypass capacitor |20 connected between the cathodes and ground. Any excessive delay which would tend to unduly separate the occurrence of pulses can be compensated by the addition of such delay in the delay networks between the separate addition circuits. Network ||6 is merely a corrective measure taken to insure the proper coincidence of pulses applied to the grids of tubes ||1 and I8. The anodes of the triodes lll, ||8 are connected through an output capacitor |2| to an output terminal |22. The other output terminal |23 may be connected to ground or any suitable indicator |24, for indieating the binary number corresponding to the sum of the applied quantities m, y may be connected to the terminals |22-|23.

The indicator |24, for example, may comprise, as shown in Figs. 8 and 9, a. conventional oscilloscope tube |25, the beam of which is normally blanked off and normally deflected just off the iiuorescent screen |26. The pulse train |21 to be indicated is derived from a source S such a's the circuit of Fig. 6, and is applied to the tube control grid |28 to unblock the cathode ray at each occurrence of apositive pulse characteristic of a binary 1 term. The initial pulse is applied to key a conventional sweep voltage generator |29 to provide a relatively slower sweep voltage which may be applied to the tube deection elements |30, |3| to sweep the ray across the fluorescent screen |20. The sweep voltage preferably should be of saw-tooth wave form |34 and the fluorescent screen |26 should be of the type providing sustained fluorescence. The indications on the uorescent screen will be ln the form of luminous dashes |32 separated by relatively wide dark spaces |33 corresponding to binary 0 terms.

Referring to Fig. '7, the first graph 7a illustrates the pulse train corresponding to the rst applier quantity Reading from right to left, the pulses of unit amplitude, and the absence of pulses, correspond to the binary number 111011, which equals 59. Graph 7b similarly illustrates the pulse train corresponding to the second applied quantity .11. Similarly reading from right to left, this pulse train corresponds to the binary number 11001, which equals 25. Graph 7c illustrates the first control pulse train a which is characteristic of the combined pulse trains :r-i-y-i-c delayed. The c delayed pulse train, l

shown at 7g, is characteristic of carryover pulses occurring whenever two or more unit pulses occur coincidentally.

Graph 7d shows the pulse train b derived from the output of the rst inverted tube |08, which is equivalent to the rst control pulse train a inverted in polarity. Graph 7e represents the second control pulse train c, which is equivalent to the pulse train b clipped at an amplitude of +1 and limited at an amplitude +2, and inverted in polarity. Graph 'if illustrates the third control pulse train d derived from the output of double the amplitude of the second control pulse 13 train c clipped at a magnitude of binary 1 and inverted in polarity. Pulses occur in the pulse train d only when two or more pulses coincide in the first control pulse train a. Sincethe a pulse train has been triple inverted, the d pulse train will be of opposite polarity thereto. When combined, in the tubes IIT, H8, the d pulse train will subtract double amplitude pulses from all double or triple amplitude pulses occurring in the a pulse train. Graph '7g illustrates the delayed second pulse train c. n

Graph 1h represents the output pulse train e characteristic of the binary sum to be derived, and is equivalent to the combined, relatively delayed control pulse trains a -ld inverted in polarity. Reading still from right to left, the graph 'lh indicates a pulse train corresponding to the binary number 1010100, which equals the sum 84.

Thus the invention described comprises two methods of and means for deriving the product of two quantities represented by groups of voltages or pulse trains, or combinations thereof, corresponding to the values of the binary 'numbers representative orA each of said quantities. The product may be derived in the form of pulse trains in which the pulses have magnitudes and time relations corresponding to the binary number representing said product.

I claim as my invention:

1. An electronic computer for deriving the product of two quantities represented by groups of voltages each of said groups being characteristic in magnitude and time relation of the binary values of different ones of said quantities including a plurality of thermionic tubes, means normally biasing all of said tubes to at least anode current cut-off condition, means for applying said voltage groups to each of said tubes in predetermined time relation to provide anode current in each of said tubes upon coincidence of predetermined magnitudes and time relations of the voltages of both of said groups, and means for deriving from said tube anode currents a voltage pulse train having pulses characteristic in magnitude and time relation of the binary value of said product.

2. The method of deriving electronically the product of two quantities comprising deriving separate voltage groups characteristic in magnitude and time relation of the binary values of each of said quantities, combining said voltage groups in predetermined time relation, deriving in response to said combined voltage groups currents characteristic of the coincidence of voltages of both of said groups, and deriving from said currents a voltage pulse train having pulses characteristic in time relation and magnitude of the binary value of said product.

3. An electronic computer for deriving the product of two quantities including means for deriving a voltage pulse train having pulses characteristic in magnitude and time relation of the binary terms of one of said quantities, a plurality of theremionic tubes, means for biasing diiferent ones of said tubes in accordance with the values of diiierent binary terms of the second of said quantities, means for applying said voltage pulse train to all of said tubes in predetermined time relation to provide anode current in each of said tubes upon coincidence of voltage pulses and predetermined tube bias voltages, and means for deriving from said anode currents a second voltage pulse train having pulses characteristic in magnitude and time relation of the binary value of said product.

4. Apparatus of the type described in claim 1 including means responsive to said pulse train for indicating the value of said product.

5. The method described in claim 2 including the step of indicating responsive to said pulse train the value of said product.

6. Apparatus of the type described in claim 3 including means responsive to said second pulse train for indicating the value of said product.

7. An electronic computer for deriving the product of two quantities represented by groups of voltages each of said groups being characteristic in magnitude and time relation of the binary values of different tones of said quantities including a plurality of thermionic tubes, means normally biasing all of said tubes to at least anode current cut-off condition, means including delay means for applying said voltage groups to each of said tubes in predetermined time relation to provide anode current in each of said tubes upon coincidence of predetermined magnitudes and time relations of the voltages of both o1 said groups, and means for deriving from said tube anode currents a voltage pulse train having pulses characteristic in magnitude and time relation of the binary value of said product.

8. An electronic computer for deriving the product of two quantities including means for deriving a voltage pulse train having pulses characteristic in magnitude and time relation o1 the binary terms of one or said quantities, a plurality of thermionic tubes, means for biasing different ones of said tubes in accordance with the values of diierent binary terms of the to all of said tubes in predetermined time relation to provide anode current in each of said tubes upon coincidence of voltage pulses and predetermined tube bias voltages, and means for deriving from said anode currents a second voltage pulse train having pulses characteristic in magnitude and time relation of the binary value of said product.

9. An electronic computer for deriving the product of two quantities including means for deriving a rst voltage pulse train having pulses characteristic in magnitude and time relation of the binary terms of one of said quantities, means for deriving a second voltage pulse train having pulses characteristic in magnitude and time relation of the binary terms of the other of said quantities, a plurality of thermionic tubes, means normally biasing all of said tubes to at least anode current cut-off condition, means for simultaneously applying said rst and said second pulse trains in predetermined time relation to each of said normally biased tubes to provide anode current therein upon coincidence of predetermined magnitudes and time relations of the pulses of both of said applied pulse trains, and means responsive to the anode currents in said tubes for deriving a third pulse train having pulses characteristic in magnitude and time relation of the binary value of said product.

10. Apparatus of the type described in claim 9 including means responsive to said third pulse .train for indicating the value of said product.

11. An electronic computer for deriving the product of two quantities including means for deriving a first voltage pulse train having pulses characteristic in magnitude and time relation of the binary terms of one of said quantities, means for deriving a second voltage pulse train having pulses characteristic in magnitude and time relation of the binary terms of the other of said quantities, a plurality of thermionic tubes, means normally biasing all of said tubes to at least anode current cut-oil. condition, a plurality of cascaded delay circuits each having a, period equivalent to one-half the pulse interval of said pulse trains, means including said delay circuits for simultaneously applying said iirst and said second pulse trains inpredetermined time relation to each of said normally biased tubes to provide 'anode current therein upon coincidence of predetermined magnitudes and time relations of the pulses of both of said applied pulse trains, and means responsive to the anode currents in said tubes for deriving a third pulse train having pulses characteristic in magnitude and time relation of the binary value of said product.

12. Apparatus of the type described in claim 11 including means responsive to said third pulse train for indicating the value of said product.

13. An electronic computer for deriving the product of two quantities including means for deriving a voltage pulse train having pulses characteristic in magnitude and time relation of the binary terms of one of said quantities, a plurality of thermionic tubes, means for biasing different ones of said tubes in accordance with the values of different binary terms of the second of said quantities, a plurality of cascaded delay circuits each having a period equivalent to the pulse interval of said pulse train, means including said delay circuits for applying said voltage pulse train to all of said tubes in predetermined time relation to provide anode current in each of said tubes upon coincidence of voltage pulses and predetermined tube bias voltages, andmeans for deriving from said anode currents a second voltage pulse train having pulses characteristic in magnitude and time relation of the binary value of said product.

14..An electronic computer for deriving the product of two quantities including means comprising a voltage discharge circuit including a plurality of delay elements for deriving a voltage pulse train having pulses characteristic in magnitude and time relation of the binary terms of one of said quantities, a plurality of thermionic tubes, means for biasing different ones of said tubes in accordance with the values of different binary terms of the second of said quantities, a plurality'of caseaded delay circuits each having a period equivalent to the pulse interval of said i pulse. train, means including said delay circuits for applying said voltage pulse train to all oi said tubes in predetermined time relation to provide anode current in each of said tubes upon coincidence of voltage pulses and predetermined tube bias voltages, and means vfor deriving from said anode currents a second voltage pulse train having pulses characteristic in magnitude and time relation of the binary value'of said product,

15. An electronic computer for deriving the product of two quantities including means comprising a ilrst voltage discharge circuit including a. plurality of delay elements for deriving a first voltage pulse train having pulses characteristic in magnitude and time relation of the binary terms of one of said quantities, means comprising a second voltage discharge circuit including a plurality of delay elements for deriving a second voltage pulse train having pulses characteristie in magnitude and time relation of the binary terms of the other of said quantities, a plurality of thermionic tubes,v means normally biasing all of said tubes to at least anode current cut-oi! condition, a plurality of cascaded delay circuits each having a period equivalent to one-half the pulse interval of said pulse trains, means including said delay circuits for simultaneously applying said first and said second pulse trains in predetermined time relation to each of said normally biased tubes to provide anode current therein upon coincidence of predetermined magnitudes and time relations of the pulses of both of said applied pulse trains, and means responsive to the anode currents in said tubes for deriving a, third puise train having pulses characteristic in magnitude vand time relation of the binary value of said product.

16. An electronic computer for deriving the product of two quantities represented by groups of voltages each oi said groups being characteristie in magnitude and time relation of the binary values of diierent ones of said quantities including a plurality of thermionie tubes, means normally biasing all of said tubes to at least current cut-off condition, means for applying said voltage groups to each of said tubes in predetermined time relation to provide anode current in each of said tubes upon coincidence of predetermined magnitudes and time relations of the voltages of both of said groups, and means including a plurality of pulse train combining circuits for deriving from said tube anode currents a .voltage pulse train having pulses characteristic in magnitude andtime relation of the binary value of said product.

17. An electronic computer for deriving the product of two quantities including means for deriving a voltage pulse train having pulses characteristic in magnitude and time relation of the binary terms of one of said quantities, a plurality of thermionic tubes, means for biasing different ones of said tubes in accordance with the values of different binary terms of the second of said quantities, a plurality of cascaded delay circuits each having a period equivalent to the pulse interval of said pulse train, means including said delay circuits for applying said voltage pulse train to all of said tubes in predetermined time relation to provide anode current in each of said tubes upon coincidence of voltage pulses and predetermined tube bias voltages, and means including a plurality of pulse train combining circuits for deriving from said anode currents a second voltage pulse train having pulses characteristicA in magnitude and time relation of the binary value of said product.

v18. An electronic computer for deriving the product of two quantities including means for deriving a rst voltage pulse train having pulses characteristic in magnitude and time relation of the binary terms of one of said quantities, means for deriving a second voltage pulse train having pulses characteristic in magnitude and time relation of the binary terms of the other of said quantities, a plurality of thermionic tubes, means `normally biasing all of said tubes to at least 19. 'In a device for deriving the product of two quantities represented by groups of potentials'- each group of which is representative o'f the binary value of a diilerent one of said quantities, the

combination of a plurality oi' delay elements connected in series, means for applying said potentials to said delay elements, a plurality of adding circuits connectedin series and each hav# ing first and second output terminals the first of which is connected to the input terminals of the next successive one of said adding circuits,y

a plurality of electron discharge devices having their input circuits connected at points each separated Iby a dlierent one of said delay eiements, means connecting the output circuits of the first two of said electron discharge devices to the input terminals of the rst of said adding circuits, meansconnecting the output circuits of successive ones of said electron discharge devices to the second ofthe input terminals of successive ones of said adding circuits, and means for deriving from said adding circuits a voltage pulse train having pulses which are characteristic in magnitude and time relation of the binary value of said product.

20. In a device for deriving the product of two quantities represented by groups .of potentials each group of which is representative of the binary value of a diierent one of said quantities, the combination of a plurality of delay elements connected in series, means for applying said poten- 3o tiais to said delay elements, a plurality of adding circuits connected in series and each having iirst and second'output terminals the iirst of which is connected to the input terminals of the next successive one of said adding circuits, a plurality of electron discharge devices having their input circuits connected at points each separated by a different one of said delay elements, means connecting the output circuits of the first two of said electron discharge devices to the input terminals 'of the rst of said adding circuits, means connecting the output circuits of successive ones of said electron discharge devices to the second of the input terminals of successive ones of said `adding circuits, and means for deriving from said adding circuits a voltage pulse train having pulses which are characteristic in magnitude and `time relation of the binary value of said product.

- PHILIP J. HERBST.

.REFERENCES CITED The following references are of record in the ille of this patent:

UNITED STATES PATENTS

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US1957672 *Jul 25, 1928May 8, 1934Associated Electric Lab IncTelephone system
US2350551 *Dec 22, 1941Jun 6, 1944Fish Edwin LElectric switch apparatus
US2401527 *Mar 30, 1943Jun 4, 1946Rca CorpElectromechanical multiplying device
US2403561 *Nov 28, 1942Jul 9, 1946Rca CorpMultiplex control system
US2404250 *Jan 22, 1944Jul 16, 1946Rca CorpComputing system
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US2571680 *Feb 11, 1949Oct 16, 1951Bell Telephone Labor IncPulse code modulation system employing code substitution
US2609143 *Jun 24, 1948Sep 2, 1952Stibitz George RElectronic computer for addition and subtraction
US2635229 *Nov 17, 1950Apr 14, 1953Electronique & Automatisme SaOperating circuits for coded electrical signals
US2643820 *Dec 12, 1949Jun 30, 1953Nat Res DevCircuit for adding binary numbers
US2659072 *Jan 13, 1949Nov 10, 1953Coales John FData transmission system for digital calculating machines or the like
US2672283 *Sep 3, 1948Mar 16, 1954IbmElectronic multiplier
US2685407 *Dec 12, 1949Aug 3, 1954Nat Res DevCircuit for multiplying binary numbers
US2693907 *Jan 3, 1950Nov 9, 1954Nat Res DevElectronic computing circuits
US2729811 *Jan 22, 1951Jan 3, 1956Electronique & Automatisme SaNumeration converters
US2761621 *Nov 24, 1950Sep 4, 1956Int Standard Electric CorpElectric calculating circuits
US2771244 *Apr 23, 1951Nov 20, 1956Electronique & Automatisme SaCoded pulse circuits for multiplication
US2785854 *Mar 26, 1952Mar 19, 1957Bull Sa MachinesElectronic calculating device
US2792987 *Jul 28, 1949May 21, 1957Stibitz George RDecimal-binary translator
US2812134 *Jun 22, 1953Nov 5, 1957Int Standard Electric CorpBinary electrical counting circuit
US2841328 *Mar 6, 1950Jul 1, 1958Northrop Aircraft IncDigital differential analyzer
US2845219 *May 31, 1951Jul 29, 1958Electronique & Automatisme SaRepresentation translation of electric magnitude
US2851219 *May 18, 1951Sep 9, 1958Bell Telephone Labor IncSerial adder
US2881979 *Jun 7, 1956Apr 14, 1959Burroughs CorpBinary adder
US2892588 *Jan 29, 1953Jun 30, 1959IbmMultiplying arrangements for digital computing machines
US2913175 *Mar 16, 1954Nov 17, 1959IbmComputer storage data handling control apparatus
US2934269 *Nov 23, 1954Apr 26, 1960IbmProduct generator
US2958465 *Jul 22, 1957Nov 1, 1960IbmElectronic adder
US2961160 *May 28, 1956Nov 22, 1960Toledo Scale CorpElectronic multiplier
US3014662 *Jul 19, 1954Dec 26, 1961IbmCounters with serially connected delay units
US3018958 *Aug 31, 1956Jan 30, 1962IbmVery high frequency computing circuit
US3021062 *Aug 8, 1955Feb 13, 1962Digital Control Systems IncMethods and apparatus for differentiating difunction signl trains
US3120606 *Jun 26, 1947Feb 4, 1964Sperry Rand CorpElectronic numerical integrator and computer
US3229080 *Oct 19, 1962Jan 11, 1966IbmDigital computing systems
US4984073 *Sep 15, 1986Jan 8, 1991Lemelson Jerome HMethods and systems for scanning and inspecting images
US5119190 *Oct 24, 1989Jun 2, 1992Lemelson Jerome HControlling systems and methods for scanning and inspecting images
US5144421 *Apr 23, 1992Sep 1, 1992Lemelson Jerome HMethods and apparatus for scanning objects and generating image information
US5283641 *Jun 16, 1993Feb 1, 1994Lemelson Jerome HFor automatically inspecting three-dimensional objects
US5351078 *Sep 16, 1993Sep 27, 1994Lemelson Medical, Education & Research Foundation Limited PartnershipApparatus and methods for automated observation of objects
US5889691 *Jan 6, 1997Mar 30, 1999Texas Instruments IncorporatedApparatus and method for a multiplier unit with high component utilization
Classifications
U.S. Classification708/626
International ClassificationG06F7/52, G06F7/48
Cooperative ClassificationG06F7/525, G06F7/5277
European ClassificationG06F7/525, G06F7/527B