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Publication numberUS2799637 A
Publication typeGrant
Publication dateJul 16, 1957
Filing dateDec 22, 1954
Priority dateDec 22, 1954
Publication numberUS 2799637 A, US 2799637A, US-A-2799637, US2799637 A, US2799637A
InventorsWilliams Richard A
Original AssigneePhilco Corp
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method for electrolytic etching
US 2799637 A
Abstract  available in
Previous page
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Claims  available in
Description  (OCR text may contain errors)

y 6, 1957 R. A. WILLIIAMS 2,799,637

METHOD FOR ELECTROLYTIC ETCHING Filed Dec. 22, 1954 2 Sheets-Sheet l mama F/QnZ.

iA\\\ vv IN V EN TOR.

y 1957 R. A. WILLIAMS I 2,799,637

METHOD FOR ELECTROLYTIC wcamc Filed D80. 22, 1954 2 Sheets-Sheet 2 INVENTOR. R/CHHRO H. LU/LL/fl/TJS 2,799,637 METnon non ELECTROLYTIC ETCHING Richard A. Williams, Collingswood, N. J., assignor to Philco Corporation, Philadelphia, Pa., a corporation of Pennsylvania Application December 22, 1954, Serial No. 477 ,034 Claims. (Cl. 204-143) The present invention relates to etching and, while of broader applicability, is particularly concerned with an improved method for utilizing jet etching to shape semiconductive bodies or structures suitable for use in electrical circuit devices, the method being particularly characterized in that the configurations of said struc- Important advances have recently been. made in this art and, specifically, in the use of electrolytic jet etching to provide the aforesaid regions, or laminae, of very minute and accurately controlled thickness. For example in the co-pending application of Tiley and Williams, entitled, semiconductive Devices and Methods for the Fabrication Thereof, bearing Serial No. 472,824, filed December 3, 1954, and assigned to the assignee of the present invention, there are described and claimed processes for shaping semiconductive bodies by electrolytic jet etching;

Contemplated by the teaching of said co-pending application is a method which includes the steps of utilizing a jet in the etching of a semiconductivev structure until perforation of the structure by said jet occurs, and producing the desired lamina by utilizing a jet, directed at another portion of said structure, for a predetermined period of time slightly less'than that required to produce the perforation. While this technique represents a significant advance in the art it is subject to certain limitations, principally in that the first etching step, commonly known as the pilot etch may result in undesired etching of adjacent portions of the semiconductive structure. Such undesired etching has several disadvantages. Ithas been found, for example, that even slightw uncontrolled etching of the area which is to be subjected to the final etching step and which is adjacent to the area of pilot etch, disturbs the geometric configuration of the body. The result is that even if the surfaces of the body were substantially plane-parallel, prior to the pilot etching step, carrying out of said step may causesaid surfaces to depart from plane-parallelism, with the consequence that the final etching step does not result in production of a residual lamina of the desired controlled thickness. If, on the other hand, the pilot etch technique is not employed and the structure is etched directly in the first etching step, random etching of portions of the semiconductor which it is not desired to etch may yet constitute a substantial difliculty, particularly if certain structural weaknesses, or faults, are present in the material being operated upon. Not infrequently such random etching results in penetration, and possible piercing, of the semiconductive body in an undesired region spaced from the nited States Patent region of jet impingement. In brief, to fabricate reproducibly laminae of the requisite controlled thickness in semiconductive bodies has continued to present problems.

With the foregoing in mind it is, broadly, the objective of my invention to provide an improved jet-etching method in which the possibility of random, undesired etching is substantially eliminated, and in accordance with which method it is possible to produce restricted regions of extreme thinness and accurately controlled configurations.

More specifically, my invention has as an objectprovision of an improved method for producing cavities of ac curately controlled depth and of limited area, in semiconductive bodies having parallel opposed surfaces.

In accordance with one aspect of the present invention it is an. objective to provide a method by which it is possible to fabricate diodes and transistors, characterized by extremely low resistance between the semiconductive base structure and the element which makes ohmic contact therewith. It is a feature. of the invention that this, and the other advantages referred to above, are achieved in such manner as to result in protecting the surface of the semiconductive body against contamination.

To the foregoingv general ends, my invention contemplates a method'in which a jet of electrolytic etchant is directed against a surface portion of a body of semiconductivematerial, which portion has been provided with a coating of metal the etching of which can be controlled and prevented by the application of suitable electrical potentials. In accordance with the method, and during passage of an electric current between the body and the jet in the direction to produce etching, the difference in potential between the. etchant and the. body is controlled in such manner that, in the region of jet impingement, the potential difference is of a magnitude sufficient to cause removal of the metal and etching of the underlying body, whereas the potential difference between the etchant and said body, in regions adjacent tov the region of impingement, is insufficient to cause substantial etching or removal of the metal. The consequence is that the coating of metal serves as a protective surface or sheet limiting the etched area and preventing the undesired or random etching referred to above.

The manner in which the foregoing and other objects and advantagesv of my invention may best be achieved, will be completely understood from a consideration of the following detailed description taken together with the accompanying drawings, in which:

Figure 1 is a flow-type diagram representing, schematically and sequentially, the steps of the method as practiced in accordance: With one aspect of the invention;

Figure 2. is a flow-type diagram illustrative of the sequential steps contemplated by the invention in accordance with the practice of another aspect of the method concept;

Figure 3 is afragmentary, sectional view illustrative of the flow of etchant across a semiconductive body during etching thereof, the view illustrating the manner in which the etchant normally spreads from the region of jet impingement toward an adjacent annular zone or region;

Figure 4 is a fragmentary, sectional view illustrating the problem which has been referred to as random etching; and,

Figure 5 is a schematic representation of apparatus suitable for practicing a method in accordance with this invention.

As suggested above the technique of this invention may be utilized in the production of a variety of articles or devices, but since the principles of the invention are of particular applicability in the field of semiconductors, the following detailed description and the accompanying drawings are illustrative of the use of the invention in the shaping of semiconductive bodies.

Now making more detailed reference to the drawings, and initially to Figures 1 and 5 thereof, it will be seen that the practice of my invention results in production of a body or wafer 16 of semiconductive material (it being understood that the drawings illustrate said body or wafer on a greatly enlarged scale) in which body are are formed depressions or cavities 11 and 12. In the illustrated embodiment the cavities are disposed in confronting relation, being separated by a residual lamina 13 of known and accurately controlled thickness. As appears in Figure 2, and as will be considered in detail hereinafter, a single cavity may be formed, if desired, in which case the residual lamina is formed by extension of said cavity nearly to the opposite surface of the wafer or body. It is to be understood that the opposed surfaces of the body are substantially plane and parallel, and that the very thin web or lamina 13, which remains, is the desired end product of the practice of my inveniton in its primary aspect.

In the production of a wafer of semiconductive material suitable for use, for example, as a surface barrier transistor, as is contemplated by the schematic showings of Figure 1, the apparatus of Figure 5 may conveniently be employed. It will be understood that this figure is presented for explanatory purposes and that the various components thereof are not necessarily to the same scale; in particular the semiconductive body or wafer 16 is, in the interest of clarity, greatly magnified as compared with the other elements appearing in the figure. The water 10 may be composed of any suitable semiconductive material, as for example N-type germanium, it being understood that other materials such as silicon may also be used. Such materials are now well known in the art and, since the invention is not concerned with the ma terials per se except insofar as they are modified by the operation of the method of the invention, description of said materials is not required herein.

In describing the technique illustrated in Figure 1 reference will be made to the separate portions of that figure in a flow sequence beginning with the left-hand sub-portions of the figure and progressing toward the right-hand sub-portions thereof. However, prior to detailed consideration of the showings of Figure 1, it is desirable to refer to Figures 3 and 4 in order that the problems which are overcome by the method of this invention may be fully understood.

In Figure 3 there is illustrated, fragmentarily, a semi conductive body or water 10a, the wafer being shown during the etching of a cavity therein. As illustrated the wafer, which is of the unplated type utilized prior to the present invention, is etched through the agency of a jet 14 of suitable etchant, said jet being formed by a nozzle represented diagrammatically at 15.

As is apparent from Figure 3 the etchant impinges against the wafer and flows outwardly from the region of impingement in a flattened, generally annular pattern, as is represented at 16. Ultimately the etchant drains from the surface ofthe wafer and flows back to the reservoir or bath, in accordance with the representation shown at 17 in Figure 3. The etching of the semiconductive body is dependent, in large part, upon the magnitude and polarity of the current which flows from the jet to the body being etched, as will be explained in greater detail with respect to Figure 5. For present explanatory purposes it is sufficient to draw attention to the fact that whereas etching occurs primarily in a rather limited region beneath and immediately around the jet 14, the etchant also flows across and is in contact with a considerable part of the adjacent surface of the wafer 10a. Since the semiconductive material is etchable to some extent, even in the absence of high current flow from the jet to the body, undesired and uncontrolled etching of areas adjacent to the region of jet impingement takes place.

As referred to hereinabove such undesired etching may interfere with the geometry necessary to completion of the final etch, or it may result in the etching of a random passage or cavity, as appears at 18 in Figure 4. In the latter figure the jet 14a is illustrated as etching a desired cavity 19 in a block of semiconductive material 1% and, due to a fault or imperfection in the material, an undesired passage has opened up at 18, leading through the wafer from a wafer surface portion which underlies the etchant as it spreads from the cavity 19.

Now referring to Figure 5 there is illustrated, for exemplary purposes, a pumping circuit adapted to form opposed jets 2t) and 21, the conduits which define the circuit being comprised, for example, of glass and including identical nozzles 22 and 23 having a substantially circular aperture of a very small diameter, for example 6 or 8 mils. The nozzles 22 and 23 are, respectively, fed by conduits 24 and 25 which comprise branched extensions of a conduit 26 within which is disposed a fluid pump 27, of any suitable type. As shown the apparatus includes a reservoir 28 arranged to serve as a source of the electrolyte 29 impingent upon the wafer 10. Preferably all portions of the apparatus which come in contact with the electrolyte are substantially non-reactive therewith, in order to avoid contamination of the solution. If, as is contemplated in the present instance, it is desired to provide electrolytic etching of germanium, the electrolyte 29 may comprise any of a large variety of readily ionizable metal salt solutions. Preferably I employ a 0.1 normal solution of indium trichloride, this being a material which will also etch the gold or other noble metal utilized as a coating for the wafer or body, as will presently be described.

Electric current is supplied between the jets 20 and 21 and the wafer 10, by means of potential source 30, a current regulating resistor 31, a switch 32, and leads 33 and 34. The electrical circuit is completed by connecting lead 33 to the wafer 10 and by attaching lead 34 to an electrode 35 which is disposed within the conduit 26, said electrode being non-reactive with the etchant and, suitably, comprising by way of example a small platinum block or sheet.

While the present invention is concerned with the etching of body or wafer 10, it will be understood that in the preferred practice of the complete method for fabri eating semi-conductive circuit devices it may be desired to utilize the same electrolyte which is used for etching, in the plating of metal within the cavity formed by the etching process. In such cases the electrolyte will ordinarily be a salt of the metal deposited, for example indium trichloride as referred to above. The plating proc ess necessitates reversal of the current flowing in the above described circuit and, if such plating is to be resorted to, switch means suitable for reversing the flow of current may be provided. For the purposes of this invention it is not necessary to illustrate such switch means in the accompanying drawing.

In particular accordance with the present invention, and now referring again to Figure 1, a method is provided by the practice of which it is possible to etch the desired cavities within a semiconductive block or Wafer, produce the requisite lamina of controlled thickness, and yet substantially eliminate uncontrolled or random etching. Broadly, these results are achieved by providing the body or Wafer with a coating of gold, platinum, or some other noble metal which is not readily subject to electrolytic etching and which will not contaminate the semiconductive material.

Beginning at the left-hand portion of Figure 1 (station 1 of the flow diagram) there is illustrated a germanium block or wafer 10 of the kind required for practice of the present invention. To this wafer there is soldered or otherwise aflixed a suitable base contact 36 (station 2) and, at station 3, there is represented the providing of a plating of metal upon the wafer 10, which metal is of a type the etching of which can be controlled by the application of a suitable potential. This coating or plating is illustrated at 37 and, in the preferred practice of the in-.

vention, comprises a layer of gold about 0.0002 inch in thickness. Application of the coating can be accomplished by any one of a number of known techniques. If plating is resorted to I prefer to employ a solution including ethylene glycol, hydrochloric acid, and auric chloride. While certain advantages of the invention may be achieved by' effecting less than complete plating or coating of the Wafer, it will be appreciated that, in addition to preventing undesired etching during the pilot step, a complete overall coating has the advantage of resulting in extremely low resistance between the semiconductive base material and the ohmic contact element 36. Additionally a complete coating results in protecting the surface of the semiconductive body against contamination.

As shown at station 4, the next step in the method illustrated in Figure 1, that is, a method involving the pilot etch technique, is to subject the wafer to the initial or pilot etch, directing the etchant against the wafer until perforation of the wafer occurs, as is indicated at 38. Preferably, although not necessarily, a pair of opposed jets 20a and 21a are used, with the result that the wafer is perforated in the region of its mid-plane.

Due to the protective coating of gold, etching is limited to a relatively restricted region underlying and closely adjacent to the jets, with the result that the plane-parallel relation of the opposed surfaces of the wafer is maintained.

The precise mechanism of gold removal has not been completely established, but it is clear that the gold, which is removed only in a restricted region beneath and adjacent the jet, the potential diiference maintained between the etchant and the germanium which underlies the gold. The term etching, as applied to removal of the gold plating, should be understood as having a broad connotation herein, covering removal of the gold layer regardless of the precise nature of the physical or chemical phenomena which may be operative.

Since the solution which comprises the etchant has a relatively high electrical resistance most of the current which flows from the jets to the wafer passes into and through the protective metal layer in the region of the jet stream and does not flow through or attack the outlying sections of metal surrounding the region referred to. For this reason removal of the gold and consequent etching of the underlying germanium is limited to an area which can be predetermined by controlling the current flow through the agency of the current-regulating resistor 31.

After completion of the pilot etching step, and as is illustrated at station in the flow diagram, jets 39 and 40 are formed and directed against the opposite faces of the wafer in a region spaced somewhat from the region of the pilot etch, and etching by said jets 39 and 40 is continued, as appears at station 6, for a predetermined period of time somewhat shorter than the time required to produce the substantial perforation referred to above, and shown at 38.

Due to the fact that the protective metal layer has prevented undesired etching of the wafer in the region of the final cavities 11 and 12, it is possible to form residual laminae of known and controlled thickness, reproducibly and on a mass-production basis. The transistor is completed, as shown at the final station 7, by depositing at the base of each of the final cavities a small dot of indium to which is attached a suitable conductor. These indium dots are shown at 41 and 42, and as indicated above they may be provided by the simple expedient of reversing the current flow through the indium trichloride solution.

The techniques of the invention may also be utilized is removed or etched in accordance with inthe manufacture. of a diode, for example a Zener diode and; to accomplish this purpose, a single jet is employed as appears in Figure 2.

Again, a block or Wafer of germanium, shown at 43, is employed, this wafer being subjected to the method steps of providing a suitable base contact shown at 36a, (station 2), and by providing a coating 37a of gold (station 3) against which is directed a-jet 44 (see station 4, Figure 2). This single jet is employed, to etch a cavity 45 (station 5) withinwhich may be deposited (station 6) a minute dot of germanium 46, comprising one electrode of the diode.

In the method of Figure 2, which does not include the pilot etching step, the presence of the gold coating is nonethe-less advantageous since it results in confining the area of etch to a smaller region. If a similar jet were applied to uncoated germanium there would result a material reduction in the thickness of the wafer throughout a substantially greater area.

The extended and undesired etching of the wafer would occur by virtue of the fact that the etching current would be applied throughout a relatively large area, since the electrical resistance of the uncoated germanium, and of the etchant, are more nearly equal than are the resistance values of the gold coating as compared with that of the etchant.

In practicing the method as explained with reference to Figure 2, it will be recognized that apparatus similar to that shown in Figure 5 could be used, with the modification that only a single nozzle would be required.

From the foregoing description it will be understood that by this invention there is provided an improved method for producing, in semiconductive bodies, cavities not only of accurately controlled depth, but also of predetermined limited area. Limitation of the area of the etch will now be understood to be highly advantageous in that it overcomes the difficulties and disadvantages resulting from uncontrolled or random etching.

I claim:

1. A method for producing localized electrolytic etching of a body of semiconductive material, comprising the steps of coating a surface portion of said body with a layer of a noble metal less susceptible to electrolytic etching than said material, forming a jet of electrolytic etchant and jet-electrolytically etching through said layer and into said body, whereby the area of the opening of the cavity formed in said body is substantially equal to the area of the opening etched in said layer.

2. A method in accordance with claim 1, and further characterized in that the coating which is formed in accordance with the claimed method, is a coating of gold.

3. A method in accordance with claim 1, and further characterized in that the coating which is formed in accordance with the claimed method, is a coating of platinum.

4. In the art of electrolytically etching a cavity of predetermined limited configuration in a body of semiconductive material, the method which comprises: coating surface portions of said body of semiconductive material with a noble metal substantially less susceptible to electrolytic etching than said semiconductive material; forming a jet of electrolytic etchant; directing said jet against a coated surface portion of said body while applying a suitable potential between said jet and said body to produce etching of the metal coating and subsequent perforation thereof in the region of jet impingement and etching the underlying body to produce the desired cavity, the lesser susceptible of said metal to etching insuring that etching of the body is substantially limited to the region bounded by edge portions of the perforation formed in the metal coating.

5. In the art of electrolytically etching a predetermined surface portion of a body of semiconducting material, the steps which comprise: providing a body of such material surface portions of which have been coated with a noble metal substantially less susceptible to electrolytic etching than said semiconductive material; forming a jet of electrolytic etchant; directing said jet against a coated surface portion of said body; applying a suitable potential be tween said jet and said body to produce etching and subsequent perforation of said metal in an area substantially corresponding to the predetermined surface portion of the underlying body to be etched; and continuing to direct the jet of etchant against said semiconductive material to etch the latter, the lesser susceptibility of said metal coating insuring that etching of said material is substantially limited to that region underlying the perforation in the metal coating.

References Cited in the file of this patent UNITED STATES PATENTS OTHER REFERENCES Tiley et a1: Proceedings of The Institute of Radio Engineers, vol. 41, No. 12, December 1953, pages 1706 through 1708.

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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US2963411 *Dec 24, 1957Dec 6, 1960IbmProcess for removing shorts from p-n junctions
US3012921 *Aug 20, 1958Dec 12, 1961Philco CorpControlled jet etching of semiconductor units
US3039514 *Jan 16, 1959Jun 19, 1962Philco CorpFabrication of semiconductor devices
US3039515 *Feb 24, 1959Jun 19, 1962Philco CorpFabrication of semiconductor devices
US3041225 *Jun 15, 1959Jun 26, 1962Siemens AgMethod and apparatus for surface treatment of p-n junction semiconductors
US3058478 *Oct 9, 1959Oct 16, 1962Carman Lab IncFluid treatment apparatus
US3072514 *Jan 12, 1959Jan 8, 1963Philips CorpMethod of producing semi-conductor electrode systems
US3135638 *Oct 27, 1960Jun 2, 1964Hughes Aircraft CoPhotochemical semiconductor mesa formation
US3138503 *Aug 12, 1960Jun 23, 1964Electronique & Automatisme SaPrinted circuit manufacturing process
US3303085 *Feb 28, 1962Feb 7, 1967Gen ElectricMolecular sieves and methods for producing same
US3335278 *Sep 11, 1963Aug 8, 1967Gen ElectricHigh level radiation dosimeter having a sheet which is permeable to damage track producing particles
US3630795 *Jul 25, 1969Dec 28, 1971North American RockwellProcess and system for etching metal films using galvanic action
US3867272 *Jan 23, 1973Feb 18, 1975Hughes Aircraft CoElectrolytic anticompromise apparatus
US4497692 *Jun 13, 1983Feb 5, 1985International Business Machines CorporationLaser-enhanced jet-plating and jet-etching: high-speed maskless patterning method
US4599154 *Mar 15, 1985Jul 8, 1986Atlantic Richfield CompanyElectrically enhanced liquid jet processing
DE1118888B *Apr 6, 1960Dec 7, 1961Philips NvDiffusionstransistor und Verfahren zu dessen Herstellung
EP0194734A1 *Jan 9, 1986Sep 17, 1986Atlantic Richfield CompanyElectrically enhanced liquid jet processing
EP2560196A1 *Aug 15, 2011Feb 20, 2013Nederlandse Organisatie voor toegepast -natuurwetenschappelijk onderzoek TNOMethod and system for forming a metallic structure
WO2013025097A1 *Aug 14, 2012Feb 21, 2013Nederlandse Organisatie Voor Toegepast-Natuurwetenschappelijk Onderzoek TnoMethod and system for forming a metallic structure
U.S. Classification205/665, 257/E21.216, 438/748, 257/E21.175, 205/221, 205/670, 205/157
International ClassificationH01L21/3063, H01L21/288, C25F3/00, C25F3/14, H01L21/02, C25F3/12
Cooperative ClassificationH01L21/3063, H01L21/2885, C25F3/12, C25F3/14
European ClassificationH01L21/3063, C25F3/12, H01L21/288E, C25F3/14