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Publication numberUS3087141 A
Publication typeGrant
Publication dateApr 23, 1963
Filing dateMay 22, 1958
Priority dateMay 22, 1958
Publication numberUS 3087141 A, US 3087141A, US-A-3087141, US3087141 A, US3087141A
InventorsHermann Endres, Karl Steinbuch
Original AssigneeInt Standard Electric Corp
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Postage stamp detecting circuit arrangement
US 3087141 A
Abstract  available in
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Claims  available in
Description  (OCR text may contain errors)

April 23, 1963 K, sTElNBUcH ETAL POSTAGE STAMP DETECTING CIRCUIT ARRAGEMENT Filed May 22. 1958 muti] moDJmE mmh-Ej monk-Jas?.

TNVENTOS Ktsnbuch Hfndres ya fl' ATTORNEX United States Patent O 3,087,141 POSTAGE STAMP DETECTING CIRCUIT ARRANGEMENT Karl Steinbuch, Felibach, Wnrttemberg, and Hermann Endres, Stuttgart-Muhlixausen, Germany, assignors to International Standard Electric Corporation, New York,

N.Y., a corporation of Delaware Filed May 22, 1958, Ser. No. 737,099 4- Claims. (Cl. S40-146.3)

The present invention relates to a circuit arrangement for detecting a postage stamp on mail items, by means of photo-electric scanning.

In some of the methods of locating the stamp, hitherto proposed, it is only possible to detect either the dark or the light-coloured mail items. In the case of dark letters, for example, the white edges of the postage stamps are evaluated during the scrutiny, so that either the brightness value of the edges is compared with the brightness value of the remaining portion of the respective mail item, or the pulses which are produced at the respective transitions from the letter to the edge of the stamp or vice versa owing to the jumps in brightness, are employed to indicate the position of the stamp. In the case of light mail items, on the other hand, it has been proposed to compare the direct current component of the stamp location with the direct current component of the remaining portion that has been examined. In another case, it has also been proposed to compare the deg-ree of the light reflection of letters and postage stamps, or of the edges of the stamps with each other, since it has been found that the light refiection-capacity of all conventional postage stamps is at about 4() to 60%, assuming the reflection capacity of the white surfaces to be 100%.

All these methods of evaluation have in common that, in order to detect light letters, the scanning has to be effected over the surface and the detection of dark letters has to be effected column-wise. In order to evaluate all types of mail items, therefore, it is usually necessary to provide two `separate scanning devices, in order to be able to switch over from the one to the other if so required. Before switching-over, it would therefore, be necessary to determine first of all whether a light or a dark-coloured mail item is to -be scanned, or both detecting systems must be arranged in series and the mail items successively passed through both systems. The latter, of course, involves increased expense.

It is the object of the present invention to provide a circuit arrangement capable of detecting the presence or absence of stamps on all letters without the necessity for previous examination of the brightness of the surfaces of the mail items, and which does not consist of a simple series arrangement of the systems for evaluation of light and dark mail items. The invention is a circuit arrangement for detecting a postage stamp on a mail item by means of photo-electric scanning wherein, according to the lightness ofthe envelope, two basic evaluation methods are employed, one of which (for light mail items) consists of comparing the characteristic values of the stamp, appearing during the scanning process, with the scanning signals of the envelope, while the other (for dark mail items) consists of comparing the characteristic values of the edge of the stamp, as obtained in the course of the scanning process, with the scanning signals of the envelope.

According to the invention for both of the evaluation methods, one common photocell which scans columnwise and with the corresponding amplifier arrangement is provided, and the remaining arrangements or devices for carrying out the two methods are so connected in two parallel paths between the photocell device and the output Mice that the path corresponding to the brightness of the examined letter or the like is selected automatically.

The circuit arrangement according to the invention can be simplified by arranging only those circuit elements used in the two methods, and which mutually exclude each other in parallel paths and that the parts of the same kind are used in common. In certain cases, it is also an advantage to use the one path only for the evaluation of the light components and the other path only for the evaluation of the dark components. This is particularly desirable, for example, in those methods in which the degree of the light reflection is evaluated. In that case, the path for evaluating the light components comprises an amplitude lter or limiter, the pass-band of which is designed for a current corresponding to the reflecting power of lighter surfaces than that of the postage stamp, and a flip-dop circuit which is tilted by the output signal of the amplitude filter into a predetermined position, and in this position produces an output signal, while the path for evaluating the dark components comprises in series an amplifier, a low-pass filter and an amplitude filter or limiter, the pass-band of which is dimensioned for a current corresponding to the reflecting power of the postage stamp. In the case of coincidence between the output signals of the iiip-ffo-p circuit and of the second amplitude filter, an identification signal is produced. For this purpose, these two output signals control a coincidence gate which, in the known manner, delivers lan output signal if a predetermined potential appears on both inputs.

The invention is described in particular with reference to the drawing, as an example.

In this example it can be assumed that the reflecting power of the letter envelope and stamp is to act as criterion for the identification of the stamp.

The letters travel past the photocell 1 and the photocell 2, and it is advisable for both devices to be arranged vertically over each other with respect to the direction of movement of the letter. 'I'he letter is scanned by a column-type photocell I2, i.e. the letter is illuminated at an angle of 45 and the reflected light picked-up by the photocell. The photocell 2 current so produced then acts as a measure for the refieotion power of the area just scanned. The photocell 2 current is amplified by the amplifier 3, which is adjusted to a predetermined value. In the condition wher-e no letters are to be scanned, the light striking photocell 1 is detected and the flip-op reset lead 4 is energized keeping fiip-flop circuit 4 in its G position, i.e. the flip-flop circuit is prevented from being tilted into its position l1. This blocking of the flip-flop circuit is eliminated when the light striking photocell 1 is interrupted at the time a letter travels between photocell 1 and the light source L.

The amplified photocell 2 signal then arrives at the branching point 5 and is fed to the low-pass iilter 6 over one path and over a different path to the amplitude iilter 7. The output of filter 7 is coupled to the input of stage 1 of the flip-flop 4. Filter f6 may be any well-known lowpass filter of the simple inductance-capacitor type wherein the inductance is in series with the input and output leads of the filter and the condenser is connected from the junction point of the inductance and output lead to the common or ground lead. In order to distinguish between the light reflected from the edge of a stamp and the variations in light resulting from scanning printed matter and the like, the filter `6 is limited to passing frequencies up to cycles per second. This frequency may vary according to the scanning rate. Thus, light variations from printed matter occur much more frequenltly than the light variations from the stamp and ilter 6 then can distinguish therebetween.

The amplitude filter or limiter 7 may be any wellknown limiter of the biased-diode type wherein a rectifier diode is in series with the signal path and biased against conductivity until an input signal exceeding the bias voltage is fed to the diode. In the instant case, the limiter 7 conducts when the photocell signals representing at least 75% reflectivity are fed thereto. Examples of such lirniters may be found in Radar Electronics Fundamentals, NAVSHIPS 900,016, pages 159 and 1612, 1944 edition, and Radar System Engineering, MIT Series, volume I, page 505. Between the branching point and the low-pass filter 6', a cut-ofi amplifier 8 can also be arranged intermediate point 5 and the input of filter 6l. This amplifier may be of any well-known conventional design which functions to prevent the frequency-dependent input resistance of filter 6 from reacting upon the branching point 5. Since filter 6 is a simple low-pass filter, the high frequencies which are to be fed through limiter 7 are likely to be cut off unless it is isolated therefrom by a buffer or cut-off amplifier. The low-pass filter y6 is tuned to a frequency ranging from about 0 to about 100 c./s., while the amplitude limiter 7 only passes voltages corresponding to a reflection power of more than 75 is noted. Assuming a light-coloured letter, reset lead 15 is de-energized and a photocell voltage which corresponds to a reflection value of about 100%, passes through the amplitude limiter 7 since the input voltage is sufficient to overcome the biasing voltage. This causes the [tilting of the flip-flop storage device 4 and prepares the coincidence gate 9. Amplitude filter or limiter is similar to the noted limiter 7 except that it will pass signals between 40% and 60% reflectivity only. This limiter is also of the well-known type wherein ltwo parallel diodes are provided with each biased to a different level. The output of the 60% limiter branch is fed to any well-known inverter whose output is coupled to the output of the 40% branch. In this way, the signals passing through limiter 10- are restricted to the noted 40% to 60% level.

When the stamp edge is scanned, experience has proven that the photocell 2 receives signals between 40% and 60% of the signal reflection resulting from a white envelope. Examples of this parallel type limiter configuration may be found on the same pages of the above referenced publications. The photocell signal corresponding to the postage stamp therefore passes through the lowpass filter 6 and the amplitude limiter 10, which only passes signals corresponding to a reflecting power of 40 to 60%, to the other input of fthe coincidence gate 9, which is thereby opened and delivers an output signal. The coincidence gate 9 operates only when pulses are applied to its inputs leading from the "1 stage of liipflop y4 and from the filter 110 and then on condition that there is no pulse applied to its inhibiting input leading from filter 14.

In this arrangement, a photocell is employed which scans in columns, which is done, for example, by means of a slotted diaphragm. The slotted diaphragm serves Vfor the scanning of the edge of fthe postage stamp, While for the detection of the surface of the stamp a square diaphragm is suitable. In order to reduce the cost, one 'slotted diaphragm is used for both scanning operations; in that case, however, care must be `taken that the slotted diaphragm can also carry out surface scanning. For this purpose, the low-pass filter 6 is provided which carries out the corresponding integration.

If a relatively dark letter appears in front of the photocell and has a reflecting power of about the same order as the postage stamp, then the edge of the stamp is 'scanned as a criterion. In that case, only one White edge is evaluated because many stamps are not printed exactly in the center, so that one white edge might be lost. The photocell signal produced by the stamp or letter is fed through the amplitude limiter 10 and opens the gate 9, if the flip-flop circuit has already been tilted by a vfront edge of the stamp. In the other case, the output signal of the amplitude limiter only prepares the gate 9 and the white pulse, produced at the rear edge of the stamp, tilts the flip-flop circuit into position 1, so that the second criterion for the gate 9 is present. Since the signal from the amplitude limiter 7 is in practice applied immediately to the flip-flop circuit, and, consequently, to the gate 9, and the signal of the amplitude limiter 101, due to the cut-off frequency of c./s. of the low-pass filter 6, is present for a relatively long time on the gate 9, lthe coincidence is ensured in any case. rIhe output pulse of the coincidence gate is sent on to the control device.

In practice, it is possible for the Writing or the like (advertisement printing) on the envelope is of such kind that in the scanning process simulates a stamp signal which, would cause faulty evaluations. In the case of white letters, for example, the printing characters may, after passage through the low-pass filter 6, give rise to a mean refiection, ranging between 40 and 60%, so that this might cause a signal to pass .through the limiter 10 and operate the gate 9, the effect of which would beassuming the the flip-flop circuit has already been tiltedto release the process, which actually should only take place after a stamp has been identified.

For this reason, an arrangement is provided which in these cases precludes the appearance of any output signal at the gate 9. This arrangement consists of the rectifier 11, the input amplifier 12, the low-pass filter 113 for frequencies from about 0 to 100 c./s., and the amplitude limiter 14, which has similar properties to the limiter 7.

The output of the limiter -14 is applied to the gate 9. The circle on this input indicates that the gate is closed. The print elimination is effected by integrating the signals coming from ,the amplitude limiter 7 and capacitor C by means of the rectifier 11 and low-pass filter 113, the latter having the same characteristics as previously described filter 6. If the integration value reaches a certain predetermined value, the gate 9 is closed. This predetermined value is such .that it is not reached when the signals produced at the scanning of a postage stamp are integrated but is reached when printing characters are scanned. The value of capacitor C is such that it passes signals which correspond to the sharp variations in light values, i.e. from black to white. Unless these sharp variations reach a suflicient number or that their amplitude is below a predetermined value, they will not pass through filter 141 and no signal will be derived from the output thereof. As the low-pass filters 6 and 13 have the same time constants the gating circuit is acted upon simultaneously by the amplitude limiter 10 and the amplitude limiter 14.

Of course, it is also possible to employ the suggested arrangement in the path, for the evaluation of dark letters, and this arrangement responds to the presence of double pulses, the spaced relation of which corresponds to the width of the postage stamps.

After the identification of a postage stamp, a signal is therefore obtained on the output of the gating circuit 9, which can be used to convey the letter to a corresponding storage compartment. If no output signal is received, the letter can assume three different positions until it is in the position in which the postage stamp passes in front of the scanning device. In order to prevent the letter being scanned four times, and the manual or mechanical turning over of the let-ters involved, the letters can also be simultaneously scanned at four different places, i.e. at the top and bottom on the front and rear sides. Thus, four of the arrangements described are needed, and that particular arrangement which detects a stamp is used to control the letters.

The filters and time-determining elements used in the circuit must be tuned to the travelling speed of the letters.

In the example described, [these elements are adapted to a travelling speed of 2 metres per second.

a1-Lise The arrangement according to the invention is not restricted to the detection of stamps on letters. It can be used with advantage whenever it is necessary to detect identication marks on documents which can be electrically characterized in any suitable manner with respect to the documents themselves.

What is claimed is:

1. A circuit arrangement for the detection of the presence or absence of a postage stamp on light-colored and dark-colored envelopes comprising scanning photo-electric means for detecting the intensity of light reflected from the surface of said stamp, the edge of said stamp and the surface of said dark-colored envelope and said light colored envelope and for generating respective signals of amplitudes corresponding to the intensity of light reected, the signals corresponding to the intensity of light reflected from the edge of the stamp and from the surface of the light-colored envelope both being of an amplitude in excess of a predetermined value and the signals corresponding ,to the intensity of light reflected from the surface of the said stamp and from the surface of the said dark-colored envelope both being of an amplitude lying within a predetermined range of values, a rst circuit path connected to said photoelectric means for passing all of said signals having an amplitude in excess of the said predetermined value, a second circuit path connected to said photoelectric means for passing all signals having an amplitude lying Within the said predetermined range of amplitude values, and coincidence means responsive to the passing of signals over said first and second circuit paths for indicating the presence of a postage stamp.

2. In a circuit arrangement as set forth in claim 1, a bi-stable device connected to the rst of said circuit paths and operable responsive to the passage of said signals thereover to prepare the said coincidence means for operation, and means responsive to the passage of signals over `the second of circuit paths for operating the said coincidence means.

3. In a circuit arrangement as set forth in claim 2, means for detecting the absence of an envelope in operative relationship with said scanning photoelectric means, and means controlled thereby for restoring the operated bi-stable device.

4. A circuit arrangement as set forth in claim 1 wherein said envelopes contain address markings on their surface and wherein said markings cause the generation of corresponding marking signals by said photoelectric means, an integrator circuit connected to said photoelectric means and operable to integrate the said marking signals and to pass said integrated signals to said coincidence device, and means in said coincidence device responsive [to the said integrated signals for blocking said device from providing the said indication.

References Cited in the le of this patent UNITED STATES PATENTS 2,731,621 Sontheimer Jan. 17, 1956 2,794,974 Bagno et al. June 4, 1957 2,925,586 Levy Feb. 16, 1960 2,931,916 Sinn Apr. 5, 1960

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US2731621 *Apr 1, 1952Jan 17, 1956C G S Lab IncCounterfeit detector
US2794974 *Jan 24, 1955Jun 4, 1957Kidde & Co WalterCompensation for turbulence and other efects in intruder detection systems
US2925586 *Jun 9, 1953Feb 16, 1960Moise Levy MauriceMethod of, and apparatus for, electronically interpreting a pattern code
US2931916 *Sep 30, 1955Apr 5, 1960Rca CorpDocument transcriber
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US3808447 *Jul 19, 1973Apr 30, 1974Wilkata Codes IncPhotoelectric scanning device using diffuse and specular reflection
US7181062Aug 30, 2002Feb 20, 2007Lockheed Martin CorporationModular classification architecture for a pattern recognition application
Classifications
U.S. Classification382/101, 356/448, 340/568.1, 250/559.4
International ClassificationB07C3/10, B07C3/14
Cooperative ClassificationB07C3/14
European ClassificationB07C3/14