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Publication numberUS3114894 A
Publication typeGrant
Publication dateDec 17, 1963
Filing dateOct 30, 1959
Priority dateOct 30, 1959
Publication numberUS 3114894 A, US 3114894A, US-A-3114894, US3114894 A, US3114894A
InventorsArneth Jr August Philip
Original AssigneeIbm
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Signaling system
US 3114894 A
Abstract  available in
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Claims  available in
Description  (OCR text may contain errors)

Dec. 17, 1963 A. P. ARNETH, JR

SIGNALING SYSTEM Filed oct. so, 1959 ATTORNEY United States Patent C) ldQ-i SiGlt-.TALYG SYSTEll/l August Phillip Arneth, fir., Wappingers Fails, NX.,

assigner to international Business Machines Corporation, New Yorin NKY., a corporation or' New York Filed er. 3d, i959, Ser. No. 849,93@ 19 Claims. (Cl. 34h-ledit) This invention relates generally to a signaling system, and more particularly to a system for generating a signal when a predetermined number of particular events have occurred during the occurrence of a number of other, continuing events.

It is the practice to represent each of a number of normal events in a system by a first, normal signal eminating from the source, the signal being serially related in time to other such signals. The nature of the system may be such that other, special signals which represent abnormal events and which also are serially related to each other, are produced from time to time by the same or another source. It is desired to ltnow when the ratio of the number of special signals to a iixed number of the last occurring normal signals exceeds a predetermined value.

In the past, the solution to this problem traditionally has included providing apparatus for counting the number of special signals, and means repetitively effective during the time intervals in which the fixed number of normal signals may occur for making the counting apparatus operative. The counting apparatus is made to drive alarm apparatus upon the registration of a predetermined count within the counting apparatus.

Such a system offers several disadvantages. For instance, where the serially-occurring normal signals are not regularly spaced apart in time from each other, the accuracy or the ratio of special signals to normal signals may not be accurately determined. Further, this batch lot approach to comparing the number of special signals to the number of normal signals occurring in each of successive time intervals or frames is only a sample of the total number of possible cases which may be checked. Stated differently, the ratio of special signals to normal signals is determined only with reference to a particular frame of normal signals, whereas conditions sufficient to justify operating the aforementioned alarm apparatus might be met by making a comparison of special signals occurring during a time interval of the same length as the aforementioned frame, but taken out of portions of two successive frames.

Accordingly, it is an object of this invention to provide a new and improved signaling system.

Another object of this invention is to provide a new and improved signaling system for comparing the number of signals of a particular nature to the number of signals of a different nature.

Another object of this invention is to provide a new and improved signaling system for comparing the number of signals of a particular nature to the number of substantially continuously occurring signals of a different nature.

Another object of this invention is to provide a new and improved signaling system for comparing the number of signals of a particular nature to a last-occurring, fixed number of signals of a different nature, where the lastnamed signals are substantially continuously generated.

Another object of this invention is to provide a new and improved signaling system for comparing the number of signals of a particular nature to a last-occurring, fixed number of signals of a different nature, where the lastnamed signals are substantially continuously generated but are randomly spaced apart from each other.

This invention is made to work in conjunction with a source of normal signals and a signal utilizing device.

ICC

While the invention is not to be limited to practice specically with such a system, the normal signal source and signal utilizing device might be a pulse generator and a word formation register, respectively, of the type shown and described in patent application Serial No. 741,545, filed June l2, 1958, by I ames S. Crosby, Ir., now Patent No. 2,969,522, entitled Data Transmission and Storage System, and assigned to the same assignee as the present invention. In FIGS. 14a, 14h, 14C and in appropriate parts of the written description of that application there is set forth a word formation register adapted to receive and store signals from an external source, such as a telephone line, and to relay the stored signals to succeeding apparatus Within the system upon the receipt of a signal from the pulse generator. Such utilized pulse generator signals occur at random time intervals, and can be brought out to a normal signal output. The register also is operative for performing other functions within itself, such as operations to check the stored signals for errors introduced by their transmission over the telephone lines, and for producing, under certain conditions, other impulses at a special output. These other signals occur less frequently than and correspond to only some of the utilized pulse generator impulses.

According to the invention, there is provided delay means, such as a shift register, coupled to the aforementioned normal signal and special outputs. Accordingly, the shift register has a shift input coupled to the pulse generator, a first or input stage of the shift register coupled to the aforementioned special output of the word formation register, and includes a fixed number of stages. The aforementioned delay means, therefore, is effective for reconstructing signals from the special output of the word formation register after an interval marked by the occurrence of a fixed number of pulse generator impulses has passed. In the case provided, this iixed nurnber of impulses is equal to the number of stages in the shift register. Also provided is a comparing means, such as a bi-directional counter, effective for comparing the number of special output impulses to the the number of irnpulses reconstructed by the delay means. Accordingly, the aforementioned counter has add and subtract inputs coupled to the special output of the word formation register and to the last or output stage of the: shift register, respectively. The counter is operative in response to the application of signals to the add and subtract inputs for counting in rst and second opposite directions, respectively. The system also includes alarm means coupled to the comparing means (i.e., counter). When the count registered within the counter at any one time, which represents the difference between the number of signals applied to the add and subtract inputs, reaches a predetermined value the comparing means is effective to operate the alarm means, in order to indicate the occurrence of a particular event. With the above-described arrangement, the particulm event referred to is the occurrence of a predetermined ratio of the number of special output impulses over an interval marked by the last-occurring number of pulse generator signals which is equal to the number of stages in the register to the number of impulses from the pulse generator.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawing. This drawing shows in block schematic form a signaling system in accordance with the principles of the present invention.

Throughout the following description and in the accompanying drawings there are certain conventions employed which are familiar to those skilled in the art.

i a Additional information concerning these conventions is as follows:

In the drawing, a conventional, solid arrowhead is employed to indicate (l) a circuit connection, (2) energization with standard pulses and (3) the direction of pulse travel which also indicates the direction of control. A solid, diamond-shaped arrowhead indicates (l) a circuit connection and (2) energization with a DC. level. The input and output lines of the block symbols are connected to the most convenient side of the block. An input connected to a corner of a first block symbol may be continued along an edge of that block to a point on an adjacent block symbol, in order to illustrate the fact that the inputs of such blocks are intended. to be energized in parallel from a common source. Bold-face character symbols appearing within a block symbol identify the common name of the circuit or element represented. For instance, FF indicates a ilip-ilop, G a gate or logical AND circuit, OR a logical OR circuit, and so on.

For simplicity of description, all pulses or levels hereinafter referred to are considered to be positive. The iiipflops, gates, OR circuits and pulse ampliers referred to in the following description may be of any suitable type, but preferably are of the type shown and described in co-pending application Serial No. 414,459, filed March 5, 1954, by D. L. Sarahan et al., entitled Electronic Digital Computer, and assigned to the saine assignee as the present invention. The delay units or lines, indicated in the drawing by the letter D, also may be of any suitable type, but preferably are of the same general construction as shown in co-pending application Serial No. 471,002, filed November 24, 1954, by Harold D. Ross et al., entitled Electronic Data Processing Machine, and assigned to the same assignee as the present invention.

A iiip-lop of the aforementioned type, when in or l state, produces a positive, DC. level signal on its corresponding output. ln accordance with the particular use to which it is put, the flop-hop may have a binary l or set and a binary (l or Lreset inputs shown connected to the l and 0 sides, respectively, of the flip-flop. In further accordance with particular use, the hip-flop may have another complement input shown connected between the O and l sides of the flip-flop. Energization of the aforementioned 0 and l inputs of any such hip-flop causes the flip-hop to assume its 0 or l state, respecti ely, while energization of the complement input shifts or complements the dip-flop from the existing to opposite state.

Turning first to the apparatus with which the preferred embodiment of this invention cooperates, input line l conveys groups or words of time-sequential binary data signals to termination The signals of each group represent message bits and a redundant, parity bit. The message bits are received and store-.i within word formation register l2. As set forth in the aforementioned Crosby application, when the bits of a complete word have been received and assembled in register l2, apparatus (not shown in the drawing) associated with register l2 applied a pulse to the readout section of the word formation register which also appears on conductor i3, so that the assembled message bits normally are read out in signal form to succeeding apparatus over conductors collectively indicated as l?. Such impulses are hereafter referred to as word formation impulses. @ther apparatus (also not shown) associated with register l2 compares the parity of the message bits stored in register l2. with the received parity bit. ln the event that the check operation indicates a parity error, an error indicating impulses is produced on conductor ld substantially in coinidence with the above described word formation impulse appearing on conductor 13. VJith the above described arrangement, it is seen that impulses appear on conductor i3 at intervals determined by the traiiic rate on incoming line ll, and further, that error indicating impulses appear on conductor l/-iin predetermined time relationship to certain ones of the word formation impulses on conductor i3. It is desired to determine when the ratio of the number of error indicating impulses to a ixed number of the last-occurring word formation impulses exceeds a pre etermined minimum. The next described apparatus is directed to eiecting a comparison of such numbers of word formation and error indicating impulses.

Error indicating impulses appearing on conductor 14 pass through pulse amplier l and shift input conductor l@ to the irst stage which inc.udes element 2l of shift register 2u. Shift register Ztl may be of any suitable type, but preferably is of the type described generally on pages 425-427 of the book entitled Pulse and Digital Circuits by Jacob Millman and Herbert Taub, published in 1956 by McGraw-Hill Book Compan, inc. r:The impulse applied to signal input i9 is stored in first stage element 2li by shifting that element to its l state. The subsequent application of an impulse to input 2d (in the manner yet to be described) causes an impulse or signal stored within the first element Zi or any intermediate register stage, which includes a storing element such as 22, to be shifted one place to the right into the element of the next-adjacent stage. The continued application of signals to shift input 24 causes a signal stored within the register to be moved progressively to the right until it is stored in element 23 f the last or output stage of register 2i). The next following impulse applied to shift input 24 causes the signal stored element 23 to be shifted out of that element onto output conductor 25.

Word formation impulses appearing on conductor 13 pass through pulse amplifier l5, delay line 26, OR circuit 2S, and pulse ampliiier 29 and then are applied to shift input conductor 24 in order to cause impulses stored in the elements of register Ztl to be shifted to the right in the previously described manner. The delay in transmitting impulses to input 21% which is introduced by delay line Z6, is sucient to allow any element within register 'Ztl to be shifted from its normal to l state prior to the arrival of a shift impulse at input 24.

Any error indicating impulse stored within register Zt) eventually is shifted into last element 23 of register Ztl, and, thereafter, to output conductor 25 upon the receipt of the next-occurrinfy impulse on conductor 2d. With the above described arrangement, any error indicating impulse appearing on conductor 119 is passed to conductor 25 upon the occurrence of the number of word formation impulses equal to the number of elements in register ln addition to being applied to input 19 of register Ztl, the aforementioned error indicating impulses on conductor lfialso are applied to add input terminal 47 of bi-directional counter 3G. Output conductor 25 of shift register Ztl is coupled to subtract input terminal 48 of counter 30. The operation of counter 3d in conjunction with shift register 2li is next described.

Bi-directional counter 3Q may be of any of a number of well-known types, including the one indicated in the drawing. Counter 3th has a iixed number of stages, each stage including a flip-flop, such as El, 32, or 33, and one of a first set of carry gates such as 37, 313, and 39. Flipflops and first set carry gates are arranged in a normal binary counting fashion with the l output of each ilip-lop connected to and effective for conditioning the first set gate of the same stage. impulses applied to add input terminal if? pass through Ol?. circuit Tilt of the counter Sti first stage to the complement input or" first stage iiipfiop 3l and are applied to the input of lirst stage carry gate 37. Other stages of counter Si? are similarly arranged, ie., the output of the first Set carry gate of the preceding stage is coupled directly to the input of the lcarry gate and by way of an Ol?. circuit to the complement input or" the flip-liep individual to the stage under consideration. With the add section elements of counter Sil disposed in the above described manner, each incoming impulse applied to terminal d'7 complements flip-flop 31 and is passed through gate 37 if the impulse on terminal 47 nds flip-flop 31 in its 1 state and gate 37 consequently conditioned. Such an impulse continues to pass through the rst set carry gates to complement the fliptlops of the next succeeding stages until a stage is in counter in which the flip-hop is in condition and its corresponding, first-set gate consequently is unable to pass the impulse. in the absence of impulses applied to the aforementioned subtract input terminal 48, continued application of impulses to terminal 47 causes the counter stages to be driven and the counter flip-flops to indicate the number of pulses incoming to terminal 47.

Counter 36 also has a subtract section which includes a second set of gates such as 4:6, 41, and 42. Each such second set gate is individual to a particular register stage, and is conditioned by the 0 side of the flip-flop of that stage. The output of each second set gate is directly coupled to the input of the second set gate of the next succeeding counter stage and coupled to the complement input of the lli -fiop of its own stage by the appropriate one of the aforementioned OR circuit, such as 34, 35, or 36. A signal applied to subtract terminal 4S is passed through OR circuit 34 of the first counter 36 stage to complement flip-flop 31 and, only if flip-flop 31 is in its 0 state, the impulse also is passed to the next succeeding stage of counter 36. The impulse applied to terminal 48 is passed successively through the aforementioned second set gates to complement inputs of the iiip-iops of the next succeeding stage until a stage is encountered where the flip-flop is in its l state, and the corresponding second set gate accordingly is deconditioned. In this manner, each impulse applied to terminal 4S of counter 3@ drives that counter to register the count which is one less than the count existing prior to the receipt of the signal at terminal 4S.

With loi-directional counter 30 coupled to conductors 14 and 25 in the above described manner, it is to be seen that error indicating pulses applied directly to add input terminal 47 drive counter 30 in an upward direction, while each error indicating pulse passed through and subsequently emerging from shift register 2u subtracts one count from the count registered within counter 30. It is also to be seen that the count registered at any time in counter 30 represents the number of error impulses received from word formation register 12 during the formation of a particular number of last-occurring words in register 12, that number being equal to the number of elements in shift register 2li. It can be said that the ratio of errors to the above-defined number of words last formed in register 12 is the ratio of the count registered in counter 30 to the number of elements in shift register 2t). Further, the point at which this ratio is to become critical can be fixed in terms of a particular count registered within counter 39. Accordingly, counter 3@ is arranged to control alarm apparatus in the manner next set forth.

Counter 30 may be arranged to control alarm apparatus in either of two ways. The first of these is in the case where the aforementioned critical ratio is said to occur on the count succeeding the number required to drive counter 30 to capacity. From the above description, it is to be seen that when a full count has been registered in counter 36, and all the aforementioned first set gates accordingly conditioned (by virtue of the flip-flops of all stages being in l state), the next succeeding impulse arriving on terminal i7 passes through all iirst set gates including 39 to output conductor 43, which couples the output of gate 39 to the l input of a bi-stable device, such as flip-flop 61. Application of an impulse to its 1 input shifts flip-flop 61 from its normal O state to its l state. Consequently, dip-flop 61 produces a steady signal at its 1 output, which is coupled by OR circuit 64 and cathode follower 65 to the input of alarm indicating apparatus 68. Alarm indicating apparatus 66 may be of any suitable type and operative in response to the receipt of the aforementioned signal from flip-flop 61 to produce audible, visual, or other signals, depending on the requirements of the system, and thereby show an alarm condition in the above-described equipment. The signal to the input of alarm apparatus 63 continues until the alarm reset apparatus is conditioned in the manner next set forth.

When the alarm condition has been noted, the alarm indicating apparatus is reset by any suitable means such as element 66. Element 66, which may be manually operable, is effective upon such operation to produce a momentary impulse on reset conductor 67. Reset conductor 67 is coupled directly to the 0 input of flip-flop 61 so that the impulse thereon shifts that flip-flop to its (l state to remove the signal from the input of alarm apparatus 68. Conductor 67 also is coupled by means including delay line 69 to the 0 inputs of all flip-flops such as 31, 32, and 33 of counter 36, so that those flip-flops are reset to indicate 0 count Within counterl 31B. The purpose of delay line 69 is to delay the resetting of counter 3i) until shift register Ztl has been emptied in the manner next explained. Conductor 67 also is coupled to the input of single shot pulse generator 27, which is operative in response to the receipt of a signal conveyed over conductor 67 for producing a signal at its output. The signal produced by single shot generator 2,7 is applied through OR circuit 28 and pulse amplifier 29 to shift input conductor 24 of counter Ztl. The signal produced by generator 27 is of sumcient duration to erase any impulse stored in a rst or an intermediate stage of shift register 26 in the manner Well known in the art and as described in United States patent application Serial Number 557,925; entitled Magnetic Core Storageg filed January 9, 1956, by Richard G. Counihan; and assigned to the same assignee as the present application. While an impulse stored in the last stage element 23 may be spilled from shift register Ztl to the subtract input of counter 3u at this time, the registration of this impulse is erased by the subsequent resetting operation of the counter 3l) flip-flops, which is carried out in the manner described above.

The aforementioned alternative apparatus for energizing alarm 68 includes a matrix 62, which has inputs appropriately connected to 1 side of the various flip-flops within counter 3@ in accordance with the count of error signals considered to be critical. Matrix 62 may be of any type suited to carry out a logical AND function, such as the AND circuit described on pages 37 through 39 of the book entitled: Digital Computer Components and Circuits; by R. K. Richards; D. Van Nostrand Company, Inc.; reprinted 1958. When the conditions of aforementioned selected flip-flops with the counter 36 reflect the count at which it is desired to start the alarm apparatus, and accordingly a significant level is present on each of the various inputs of matrix 62 by virtue of the presence of a level on each of conductors fidi, 45, and 46, matrix 62 is operative to produce an output on conductor 63. Such a steady set output signal is passed through OR circuit 64 and cathode follower 65 to the input of alarm apparatus 63. However, unlike the previously described alarm actuating apparatus which required resetting in order to clear an alarm condition, the presently considered apparatus is effective for causing alarm apparatus 68 to operate only so long as counter 36 flip-flops are in condition to satisfy the conditions on the inputs of matrix 62 required to produce an output signal on conductor 63. Should subsequent signals applied to terminal 47 or 48 of counter 36 change the count therein in the manner previously described, the conditions for an output on conductor 63 would no longer exist, so that the signal is removed from conductor 63 and the input signal is removed from alarm apparatus 68. Alarm apparatus 6d thereupon stops operating.

While the invention has `been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein Without departing from the spirit and scope of the invention.

What is claimed is:

1. In a signaling system having a first source for producing impulses at randomly spaced apart time intervals and a second source for producing other impulses, wherein the impulses from said second source correspond only to some of the impulses from said first source, the combination comprising: delay means coupled to said first and said second sources operative for reconstructing each impulse produced by said second source at an interval marked by the occurrence of a fixed number of said first source impulses, and comparing means coupled to said second source and said delay means for comparing the number of impulses produced by said second source to the number of impulses reconstructed by said delay means.

2. The signaling system set forth in claim 1 and having in add. on alarm means effective for indicating the occurrence of a particular condition, and wherein said comparing means is operative in response to the occurrence of a particular ratio of said second source impulses to impulses reconstructed by said delay means for operating said alarm means.

3. ln a signaling system having first and second sources capable of producing signals at random time intervals, a shift register having a shift input coupled to said first source and a fixed number of stages, said register also including an input stage coupled to said second source and an output stage, a bi-directional counter having add and subtract inputs coupled to said second source and to said shift register output, respectively, said counter being operative in response to the application of signals to said add and said subt'act inputs for counting in first and opposite directions, respectively, and alarm means coupled to said counter operative for indicating the occurrence of an event, said counter being effective in response to the registration therein of a predetermined count for making said alarm means operative.

4. The signaling system set forth in claim 3 wherein said alarm means includes a bi-stable device having a first, normal condition operative to a second, operated condition, and indicating means coupled to the output of said bi-stable device operative for showing an alarm condition, and wherein the input of said bi-stable device is coupled to said counter, said counter is operative in response to the registration of a predetermined count therein for shifting said bi-stable device to its operated condition, and said bi-stable device in operated condition is etfective for operating said indicating device.

5. The system set forth in claim 4 and having in addition means operative for resetting said bi-stable device to its normal condition.

6. The system set forth in cl-aim 4 and having in addition means operative for resetting said bi-stable device to normal condition and for resetting said counter to O count.

7. The system set forth in claim 4 and having in addition means operative for resetting said bi-stable device to normal condition, for resetting said counter to count, and for applying an erase impulse to said shift input of said shift register.

S. ln a signalling system having a first source capable of producing signals at random intervals and a second source capable of producing signals substantially in synchronism with certain ones of said first source signals, a shift register having shift and signal inputs, an output, and a fixed number of stages, means for coupling said second source to said register signal input, means including a delay line for coupling said first source to said register shift input, a bi-directional counter having add and subtract inputs coupled to said second source and to said .shift register output, respectively, said counter being opcrative in response to the application of signals to Said add and said subtract inputs for counting in first and opposite directions, respectively, and alarm means coupled to said counter operative for indicating the occurrence of an event, said counter being effective in response to the registration therein of a predetermined count for making said alarm means operative.

9. The signaling system set forth in claim 8 wherein said alarm means includes a bi-stable device having a first, normal condition operative to a second, operated condition, and indicating means coupled to the output 0f said bi-stable device operative for showing an alarm condition, and wherein the input of Said bi-stable device is coupled to said counter, said counter is operative in response to the registration of a predetermined count therein for shifting said bi-stable device to its operated condition, and said bi-stable device in operated condition is effective for operating said indicating device.

10. The system set forth in claim 9 and having in addition means operative for resetting said bi-stable device to its normal condition.

11. The system set forth in claim 9 and having in addition means operative for resetting said bi-stable device to normal condition and for resetting said counter to O count.

12. The system set forth in claim 9 and having in addition means operative for resetting said bi-stable device to normal condition, for resetting said counter to 0 count, and for applying an erase impulse to said shift input of said shift register.

13. In a signaling system which has a word formation register including a plurality of elements capable of storing each word of serially-related message signals and a parity bit incoming from a line; a first source operative upon the registration of a word in said register for producing word formation impulses for application to said formation register storing elements in order to cause a word stored therein to be read out to succeeding apparatus; parity checking means operative for performing a comparison between the received parity bit and the parity of signals stored in said word formation register elements; and a second source operative in the event that said parity checking means indicates a difference between the received parity bit and the parity of the corresponding word stored in said word formation register elements for generating an error indicating impulse substantially in coincidence with a particular one of the impulses generated by said first source, the combination comprising: a shift register having shift and signal inputs, a fixed number of stages, and an output; means for coupling said error impulse source to said shift register signal input; means including a delay line for coupling said word formation impulse source to said Shift register shift input in order to make word formation-indicating impulses arrive at said shift register at times subsequent to the arrival of corresponding error indicating impulses; a multistage, bi-directional counter having add and subtract inputs; each of said counter stages including a bi-stable element; said counter stages being operative in response to the application of signals to said add and said subtract inputs for counting in first and opposite directions, respectively; means for coupling said error impulse source to said counter add input; means for coupling said shift register output to said counter subtract input; alarm means operative for indicating the occurrence of an event; and means for selectively coupling said counter to said alarm means; said counter being operative upon the registration of a particular count therein for operating said alarm means.

14. The signaling system set forth in claim 13 wherein said means selectively coupling said counter to said alarm means includes an AND gate having multiple inputs selectively coupled to particular ones of said counter bistable devices and an output coupled to said alarm means, said matrix device being operative in response to the application of signals in particular combination to said multiple inputs for passing a signal to said AND gate output, in order to cause said counter to operate said alarm means at a time when a particular count less than the capacity of said bi-directional counter is registered therein.

15. The signaling system set forth in claim 13 wherein said alarm means is operative in response to the application of an impulse, each of said lai-directional counter stages also includes a carry gate, and said means selectively coupling said counter to said alarm includes said gates serially connected between said add input and said alarm means, in order to cause an error indicating impulse to operate said alarm means subsequent to the registration of a full count Within said lui-directional counter.

16. The signaling system set forth in claim 13 wherein said alarm means includes a bi-stable device having a first normal, condition operative to a second, operated condition; and indicating means coupled to the output of said lai-stable device operative for showing an alarm condition; and wherein said serially connected gates couple said counter add input to said alarm bi-stable device; said counter is operative in response to the registration of a predetermined count therein for shifting said bi-stable de- 1t) vice to its operated condition; and said loi-stable device in operated condition is effective for operating said indicating device.

17. The system set forth in claim 13 having in addition means operative for resetting said alarm bi-stable device to its normal condition.

18. The system set forth in claim 13 and having in addition means operative for resetting said alarm bi-stable device to normal condition and for resetting said counter to 0 count.

19. The system set forth in claim 13 and having in addition means operative for resetting said alarm bi-stable device to normal condition, for resetting said counter to 0 count, and for applying an erase impulse to said shift input of said shift register.

References Cited in the tile of this patent UNITED STATES PATENTS 2,789,759 Tootill Apr. 23, 1957 2,798,156 Selmer July 2, 1957 2,799,450 Johnson July 16, 1957 2,823,855 Nelson Feb. 18, 1958

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US2789759 *Jun 21, 1950Apr 23, 1957Nat Res DevElectronic digital computing machines
US2798156 *Dec 17, 1953Jul 2, 1957Burroughs CorpDigit pulse counter
US2799450 *Dec 30, 1953Jul 16, 1957Hughes Aircraft CoElectronic circuits for complementing binary-coded decimal numbers
US2823855 *Nov 26, 1952Feb 18, 1958Hughes Aircraft CoSerial arithmetic units for binary-coded decimal computers
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US3376408 *May 31, 1962Apr 2, 1968Sperry Rand CorpHole count checker
US4103149 *Mar 28, 1977Jul 25, 1978Telefonaktiebolaget L M EricssonArrangement for the performing seizure statistics for a device belonging to a group of devices
Classifications
U.S. Classification714/811, 377/54, 340/146.2, 377/28, 377/19
International ClassificationG01R23/00, H04L1/00, G01R23/09
Cooperative ClassificationG01R23/09
European ClassificationG01R23/09