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Publication numberUS3152250 A
Publication typeGrant
Publication dateOct 6, 1964
Filing dateJul 20, 1962
Priority dateJan 8, 1962
Also published asUS3197626
Publication numberUS 3152250 A, US 3152250A, US-A-3152250, US3152250 A, US3152250A
InventorsPlatzer Jr George E
Original AssigneeChrysler Corp
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Circuit for performing the combined functions of the extraction of roots, multiplicaton, and division
US 3152250 A
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Description  (OCR text may contain errors)

Oct. 6, 1964 G. E. PLATZER, JR 3,152,250

CIRCUIT FOR PERFORMING THE COMBINED FUNCTIONS OF THE EXTRACTION UF ROOTS, MULTIPLICATION, AND DIVISION Filed July 20, 1962 4 Sheets-Sheet 1 E z ym Oct. 6, 1964 e. E. PLATZER, JR 3,152,250

, CIRCUIT FOR PERFORMING THE COMBINED FUNCTIONS OF THE EXTRACTION OF ROOTS, MULTIPLICATION, AND DIVISION Filed July 20, 1962 4 Sheets-Sheet 2 is I 4?; V83 V91 E E E I L Ah W INVENTQR. 660738 I. 7 47767; J)?

Oct. 6, 1964 G. E. PLATZER, JR 3,152,250

THE COMBINED FUNCTIONS OF THE CIRCUIT FOR PERFORMING EXTRACTION OF ROOTS, MULTIPLICATION, AND DIVISION 4 Sheets-Sheet 3 Filed July 20 1962 INVENTOR. sar e Z. fidizezJi' ITTQFMF/ T 2 IZHZI? 1964 G. E. PLATZER, JR 3,152,250

CIRCUIT FOR PERFORMING THE COMBINED FUNCTIONS OF THE EXTRACTION 0F ROOTS, MULTIPLICATION. AND DIVISION Filed July 20, 1962 4 Sheets-Sheet 4 /0y'z dfiz 9 PM i g I d p /ia/ A94": q 6 INVENTOR eayye Z, 7 74720; 75'. BY

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United States Patent 3,152,250 CIRCUIT FOR PERFORMING TIE CQIt IBINED FUNCTIONS 6F THE EXTRACTIGN 0F RGUTS, MULTIFLICATION, AND DIVISION George E. Platzer, J12, Birmingham, Mich., assignor to Chrysler Corporation, H ghland Park, Mich a corporation of Delaware Filed July 20, 1962, Ser. No. 211,261 16 Claims. (Cl. 235-193) This invention relates generally to analog computers and, more particularly, to a circuit for the extraction of roots While performing the combined and simultaneous functions of multiplication and division.

The present application is a continuation-in-part of my copending US. application Serial No. 164,873, filed on January 8, 1962, entitled Multiplier Circuit and of common ownership herewith.

There is a need for a simple yet reliable root extracting computing circuit for a variety of industrial control applications such as turbine fuel control, welding input power control and in direct analog computer applications. A circuit which performs the combined functions of root taking, multiplication and division is of particular usefulness in these fields.

Accordingly, it is an object of this invention to provide an improved analog computing circuit for the extraction of roots which is simple with respect both to the components required and the operational requirements of the circuit.

It is an additional object of this invention to provide a circuit for the extraction of roots which is made temperature stable by the incorporation of a minimum but precisely determined number of temperature compensating elements.

It is a further object of this invention to provide an improved circuit for performing simultaneous root extracting, multiplication and division.

It is a still further object of this invention to provide a circuit for performing simultaneous root taking, multiplication and division in which the components utilized are so constituted and so connected that they have substantially identical exponential, current-voltage characteristics in operation to provide a high degree of accuracy in computation.

The foregoing statements are merely illustrative of the various aims and objects of the present invention. Additional objects and advantages will become apparent from the following specification when considered in conjunction with the accompanying drawings, in which-- FIGURE 1 is a graph plotted on semi-logarithmic coordinates showing the diode and transistor current-voltage characteristics;

FIGURE 1A is a schematic of a diode from which is derived its forward current-voltage characteristics as shown in line 1a of the graph of FIGURE 1;

FIGURE 1B is a schematic of a basic transistor circuit from which is derived its collector current versus emitterbase voltage characteristic as shown in line 1b of the graph of FIGURE 1;

FIGURE 1C is a schematic of a transistor having base and collector connected together from which is derived its emitter current versus emitter-base voltage characteristic as shown in line 1d of the graph of FIGURE 1;

FIGURE 1]) is a schematic of a second transistor cir cuit with its collector circuit open from which is derived its emitter current versus emitter-base voltage characteristic as shown in line 1d of the graph of FIGURE 1;

FIGURE 2 is a schematic of the basic multiplying circuit employing two input diodes and one transistor;

FIGURE 3 is a schematic of the multiplying circuit of FIGURE 2 modified to prevent temperature drift inac- 3,152,25fi Patented Get. 6, 1984 curacies, equalize current densities, and to provide compensation for collector saturation current in the output circuit;

FIGURE 4 is a schematic of a modification of the basic multiplying circuit of FIGURE 2 with transistors utilized as input or logarithmic translating devices in place of diodes;

FIGURE 5 is a schematic of a four quadrant multiplying circuit;

FIGURE 6 is a schematic showing the circuit of FIG- URE 2 modified to provide for the root extraction process;

FIGURE 6A shows a modification of the circuit of FIGURE 6 to provide fractional root taking;

FIGURE 7 shows a modification of the circuit of FIG- URE 6; and

FIGURE 8 shows a circuit operable to perform the combined operations of root taking, multiplication and division.

The invention, as herein illustrated among the several embodiments in the drawings, utilizes diodes and transistors with substantially the same exponential characteristics which operate entirely in the logarithmic domm'n, i.e. as logarithmic translating devices. It will be appreciated by those skilled in the art that the invention is not necessarily limited to solid state devices but may be practiced with other types of switching devices such as, for example, with variable-mu tubes which produce a plate current proportional to the logarithm of the grid input voltage within a limited range of the input voltages. Similarly, by operating a variable-mu tube with the input voltage applied to the plate and current withdrawn at the grid, the output current is proportional to the antilogarithm of the voltage input to the plate.

The principle of operation of the circuits of the present invention is best explained with reference to the graph of FIGURE 1 which shows the current-voltage characteristics of a silicon FD 200 diode and a 2N1711 junction transistor. Under optimum conditions and to give perfect accuracy the lines 1a and 1b should be straight and parallel in slope. It is well known that semi-conductor junction diodes have the current-voltage characteristic as exhibited by diode 10 in FIGURE 1A and shown by line 1a in FIGURE 1 and as theoretically described by the following equation:

1 QY I=I (e 1)=I e wherein I =diode saturation current (amperes), q=electron charge (coulombs), V diode voltage (volts), k=Boltzmanns constant, and T =temperature.

The above approximation is quite good when V is greater than about 0.1 volt.

The saturation or reverse current of the diode is itself temperature dependent and is of the form (Equation 1) wherein I =saturation and at T E =energy gap of the material q I (Equation 3) Therefore, it may be seen that the voltage across a diode is proportional to the logarithm of the current through it. If two semiconductor diodes are connected in series in the manner shown hereinafter in FIGURE 2, the sum of the voltages is proportional to the logarithm of the product of the two current inputs and we have the basic elements of a multiplying circuit in which wherein the subscripts relate to the first or second diodes connected in series.

It will then be apparent that the product of 1 x1 can be determined by simply taking the antilogarithm of V +V in Equation 4 so that V 111921811526 kT (Equation 5) The limitations for the antilogarithmic translating device are that it must have the same exponential characteristic as the diodes and it must not appreciably disturb the signal currents flowing in the diodes. A junction transistor fills this requirement since its emitter-base diode has the same type of exponential characteristicas any other junction diode. Furthermore, the base current can be made a small fraction of the current flowing into the two input diodes.

FIGURE 2 shows a simple multiplying circuit utilizing a pair of input diodes a, 10b, and a transistor 14 having a base, 14b, a collector, 14c, and an emitter, 14e. The emitter-base diode of transistor 14 has a voltage-current characteristic like Equation 1 and may be expressed as follows:

(Equation 7) Equation 7 shows that the emitter current of the transistor 14 is proportional to the input diode current products. If the collector cut-off current is low and the current gain h is nearly unity, this is also true of the collector current since C fb E+ C0 (Equation 9) wherein h =common base forward current gain I =collector saturation current.

Thus the actual output current may be taken from the collector 140 or an output voltage may be taken from the collector load resistor 16. The circuit of FIGURE 2 is operative to perform the multiplication process but its accuracy is not high enough for many applications and the circuit is also subject to temperature drift.

FIGURE 3 shows the circuit of FIGURE 2 modified to eliminate the two principal sources of error present therein. Temperature drift could be anticipated because the saturation currents I I and 1 in Equation 7 are all of the form shown in Equation 2. With one more temperature dependent quantity in the denominator than Since and by substitution we derive the equation Equation 10 shows that variations of the saturation currents with temperature are now balanced and essentially cancelled out with two each ,in the numerator and denominator. Since FIGURE 3 also shows a resistor 17 in the emitter circuit and a current source 19 supplying a current through resistor 16 flowing in a direction opposite to the collector current. Thefunction of emitter resistor 17 is to modify the shape of curve 1b of the transistor characteristic in FIGURE 1 to make it more nearly match that of the diode 1a. The purpose of the current source is to supply a current through the load resistor which is equal in magnitude but of opposite direction to the collector cut-ofl? current. Resistor 16a in the current source circuit must be temperature sensitive and have characteristics such that its current is always equal to the temperature sensitive collector cut-oft current. It will be seen that by the circuit of FIGURE 3, I have provided a multiplying circuit which is workable within practical operation limits to accomplish the multiplication process. An accuracy within the limits of approximately 2% is possible with this circuit even in the absence of a perfect match of the transistor 14 to the diodes 10a and 10b as is illustrated by the current conducting characteristics shown in FIGURE 1.

The compensating diode .18 could be replaced by a resistor and temperature sensitive means to maintain the voltage across the resistor in such a manner so to simulate diode 18. In an isothermal environment, the temperature sensitive means could even be eliminated.

FIGURE 4 shows a circuit employing transistors 22 and 23 as the input or logarithmic translating devices of the circuit. Transistor 24 is included in the circuit to minimize the effect of temperature drift and high currents in the same manner in which diode 18 functions in the circuit of FIGURE 3. The collectors 22c and 230 of each of the aforementioned transistors are connected back to their bases 22b and 23b, respectively. The result of the coupling arrangement is to much improve the match between the current-voltage characteristics of the input elements 22 and 23 and those of the output or antilogan'thmic translating transistor 14 as indicated by the line 1b and 1c of FIGURE 1. The circuit of FIGURE 4 yielded much improved accuracies of the order of .25

(Equation 10) FIGURE 5 shows a four quadrant multiplying circuit which is formed by essentially combining two multiplying circuits of the type shown and described in connection with FIGURE 3, hereinbefore, and operating with an initial bias on each of the multiplying circuits. A four quadrant multiplier is desirable in some applications since it is capable of accepting positive and negative factors and of producing positive and negative products therefrom. An initial bias I and I is applied over each of the input terminals to input diodes a, 10b, 10a, and 10b. The same signal voltages or currents I and 1 are sent to the input diodes of each multiplier but the polarities of the signals are reversed in the manner illustrated by FIGURE 5. Load resistor 16 is common to both transistors 14 and 14. In operation, one multiplier produces a current in load resistor 22 of (Equation 11) wherein I =bias current in diode 10a, I =-bias current in diode 10b, I =signal current in diode 10a, and l =signal current in diode 10b.

The other multiplier produces a current of 'm- 1') 'B2 2') 'B1 'B2 '1 'B2 '2 'B1+ '1 2' (Equation 12) Since load resistor 16 is common to both transistors 14 and 14', Equations ll and 12 may be added and the load current may be expressed as The above relationship holds true so long as all bias currents I I 1' and 1' are equal. The product of the 13.0. bias 1 I is a constant which may be subtracted from the output.

This may be accomplished by means of resistors 22 and 21 to form a voltage cancelling network and with the output voltage taken across E. Alternately, a current cancelling network could be formed with a resistor and another voltage supply to supply a current through resistor 16 which is equal in magnitude to 21 1 but of opposite direction. In the latter case, the output would appear across resistor 16. In both cases, the output voltage would be representative of the product of the input currents to the multiplier regardless of their polarity. While the four quadrant multiplying circuit of FIGURE 5 is combined from two multiplying circuits substantially similar to the one shown in FIGURE 3, it will be appreciated that two multiplying circuits as shown in FIGURE 4 may similarly be incorporated in a four quadrant multiplier.

The ability to perform division is another function of the basic circuit as shown in FIGURE 3. If 1 is a variable signal current and I is made a constant current, it will be seen that I or I of the transistor 14 is proportional to 1 /1 This is best illustrated by the rearrangement of terms in Equation 10 as follows:

I E0121 s2 A It will thus be seen that I have provided an analog multiplying circuit which is readily converted into a divider circuit by the interchange of variable signal current and constant current. By making I I and I all variable currents, the circuits of FIGURES 3 and 4 will perform the combined function of multiplication and division.

By modifying the basic circuit of FIGURE 2, but still employing the principle of using the exponential charac acteristics of diodes or transistors for computation, a circuit which will extract roots can be constructed. An example of such a circuit is shown in FIGURE 6. In FIG- URE 2, two diodes and a transistor were used to produce V33: V1 V2- V3 (Equation Substituting in Equation 6 From Equation 1 it is seen that each oi the exponential terms is the ratio of the diode current to its saturation current. Hence,

I1 12 Iss If it is assumed that diode 6% has characteristics identical to the output transistor 15,

(Equation 16) sn ss 2 I sl .821 1 Lumping the constants and taking the root,

I A/E (Equation 18 Note that the saturation currents in Equation 17 are balanced in numerator and denominator. In this case, no temperature compensation is required.

FIGURE 6a shows a modification of the circuit of FIGURE 6 which provides for selecting fractional root taking. This is accomplished by shunting a variable resistor such as that of potentiometer 62 across root taking diode 6%. As has been explained in connection with FIG- URE 6, the incorporation of a diode 641 permits square root taking. By the simple expedient of moving the slider of potentiometer 62 between its left and right hand limits, fractional roots intermediate the one-half power and the first power may be extracted.

It may be desirable to have a temperature invariant voltage source in the series loop to adjust the output current to a desired level. For example, if 1 and I are both set for full scale at one milliampere, the collector current in the output transistor 14 will be one milliampere only if all four of the devices have exactly identical characteristics. Because of manufacturing variations, this will not usually be the case, and small differences Will exist. If it is desirable, for example, to set the output current to one milliampere when each of the inputs is one milliampere, it will be necessary to use a voltage source in the emitter-base series loop. FEGURE 7 shows such a circuit in which this voltage source is a simple resistive voltage divider including resistors 79 and 72 and battery 74. The placement of battery 74 is such that the emitter current does not flow through it, and the divider current is large compared to the base current.

FIGURE 8 shows a circuit using the exponential characteristics of its components to multiply, divide, and extract roots. The generalized form of the equations which (Equation 17) can be solved by such a circuit is:

1 X X X Z (Equation 19) Where X X X are multiplying factors; Y Y Y are dividing factors; and

r is the order of the root to be taken. A generalized form of circuit for solving Equation 19 can be specified. If m is the number of multiplying factors, there must be m logarithmic translating devices xsl xs2 IE:IES

the signal current increases. If r is the order of the root to be taken, there must be (r-l) logarithmic translating IYSI Ive? Again, from Equation 1 it is seen that each of the exponetial terms is the ratio of the diode current to its saturation current. Note particularly the effect of the sign of the exponent in inverting the ratio upon substitution. Hence,

. 10a]? Yn ss1 csz csq (Equation 23) Grouping the constant current terms,

E= EJ devices in the emitter circuit of the output transistor connected in such a manner that the emitter current flows in the forward direction for those devices. The number of compensating diodes or transistors required for temperature stabilization will be equal to (n+r-m). If this sum is positive, the compensators are to be connected with the same polarity as the multipliers. If the sum is negative, they are connected as dividers. The magnitude of the constant current through the compensators is made suflicient to assure that the active elements are working in their logarithmic range and at the desired current level. If the number of temperature compensating elements is zero, it may be desirable to insert in their place a temperature invariant voltage source to set a desired level of output current after the manner shown in FIGURE 7, hereinbefore. The polarity of the voltage source will be a function of the desired output current and the variations existing among the active elements. Such a generalized circuit in combined schematic-diagrammatic form is shown in FIGURE 8. Di odes IC -10 represent multiplier input diodes. Diodes 10 7 -10 represent divider input diodes and diodes 60 -60 represent root taking diodes connected in the emitter of transistor 14. Compensating diodes are connected in the manner illustrated and identified by the numerals l8 l8 That the circuit of FIGURE 8 will perform the function indicated in Equation 19 can easily be shown. Again writing Kirchoiis law around the emitter-base loop of transistor 14:

(Equation 20) Where V =voltage across a multiplying element m=number of multiplying factors V =voltage across a diving element n=number of dividing factors V =voltage across a root taking elment p=number of root elements:rl V =voltage across a compensating elment q=number of compensating elements If it is assumed that the output transistor 14 and root extracting diodes are substantially identical, in their ex ponetial, current-voltage characteristics, Equation 20 may be re-written as:

Vy iVcliI cz iV (Equation 21) Substituting Equation 21 in Equation 6, and noting the (p+1)=r, the order of the root,

1 I 'IG1'IC2 IC 11 IX1.IX2 I ]r I 5 -I s .Icsg I I I I (Equation 24) Where Lumping constants,

1 (Equation 25) ly lyz Hence, the circuit of FIGURE 8 is seen to yield an output current of the form of Equation 19.

In Equation 24 the first term is seen to contain all of the constants, i.e., the saturation currents and the compensating element bias currents. The saturation currents must appear an equal number of times in both numerator and denominator to achieve temperature stability. The number of saturation currents appearing in the numerator due to the computing elements is r+n. In the denominator, the number is m. It can be seen that the number of saturation currents, q, provided by the compensating elements must be r-l-n-m.

q=r+nm (Equation 26) Furthermore, it can be seen that if q is a positive numher, the compensating saturation currents must appear in the denominator. This means they must be connected with their polarity the same as that of the multiplier factors. If q is negative they must be connected with their polarity the same as that of the dividing factors.

The modification suggested in connection with FIG- URE 6A is likewise applicable to the circuit of FIGURE 8. It should be noted that, in the event of the incorporation of a plurality of root taking diodes 60 in the circuit the shunt resistor would be mounted across only one of the root taking diodes. This modification permits selective adjustment to take fractional powers over intermediate ranges.

It will thus be seen that I have provided a novel circuit for simultaneous performance of the combined functions of multiplication, division and root taking. While the circuits of FIGURES 6-8 employ semiconductor diodes as the multiplying, dividing or compensating elements, substitution may be made of transistors, each having its collector coupled to its base, for these elements. The advantages and manner of such an alternate embodiment has been thoroughly explained and illustrated hereinbefore in connection with FIGURES 3 and 4. When used in this manner, the input current flows into the base- (Equation 22) 9 collector terminal and out the emitter terminal for an NPN transistor.

The foregoing disclosure and showings made in the drawings are merely illustrative of the principles of this invention. It will be appreciated by those skilled in the art that this invention may be subject to modifications in its details through substitution of other types of electronic or electrical devices for the logarithmic and antilogarithmic translating devices indicated, and that this invention may be further modified in the organization of its details, all Without departure from the spirit and scope of this invention.

I claim:

1. A circuit for extracting the desired root of a quantity represented by a current input comprising a first logarithmic translating device for producing a voltage output proportional to the logarithm of its current input, an antilogarithrnic translating device connected to the output of said first logarithmic translating device for producing a current output proportional to the antilogarithm of the output of said first logarithmic translating device, and at least one root determining logarithmic translating device connected in the output circuit of said antilogarithmic translating device and operatively connected to said first logarithmic translating device, the number of said root determining devices being equal in number to the root desired less one, all the aforesaid translating devices having substantially the same exponential, current-voltage characteristics.

2. The combination as set forth in claim 1 wherein said logarithmic translating devices comprise semiconductor diodes and said antilogarithmic translating device comprises a transistor.

3. The combination as set forth in claim 2 wherein said first logarithmic translating diode and said root determining diodes are connected in series across the emitter base diode of said transistor, said first logarithmic translating diode being oppositely poled from said root determining diodes.

4. The combination as set forth in claim 1 wherein said logarithmic translating devices comprise transistors, each having its collector coupled to its base.

5. A circuit for extracting the root of a product of quantities represented by current inputs comprising a plurality of logarithmic translating devices for producing a voltage output proportional to the logarithm of the current inputs thereto and being similarly poled and coupled in series, an antilogarithmic translating device operatively connected to the combined outputs of said plurality of logarithmic translating devices, and at least one root determining logarithmic translating device connected in the output circuit of said antilogarithmic translating device and operatively connected to said logarithmic translating devices to provide a current output proportional to the desired root of the product of the current inputs, the number of said root determining devices being equal to the root desired minus one, all the aforesaid translating devices having substantially the same exponential, cnr-= rent-voltage characteristics.

6. The combination as set forth in claim 5 in which said logarithmic translating devices comprise semiconductor diodes and said antilogarithmic translating device comprises a transistor.

7. The combination as set forth in claim 6 wherein said root determining diodes are oppositely poled to said first plurality of diodes and connected in series therewith across the base emitter diode of said transistor.

8. The combination as set forth in claim 7 wherein a voltage source is included in the emitter base loop whereby the output current is set at a predetermined level relative to a given input current.

9. The combination as set forth in claim 5 in which said logarithmic translating devices comprise transistors, each having its collector coupled to its base.

10. The combination as set forth in claim 5 wherein a variable resistor is connected in shunt with one of said root determining logarithmic translating devices for computation of a fractional root.

11. The combination as set forth in claim 5 wherein a means is included for calibrating the output current relative to the input current.

12. A circuit for combined multiplication, division and extraction of roots of quantities represented by current inputs comprising a plurality of multiplying and dividing means of the logarithmic translating type connected in series, said multiplying means having one polarity and said dividing means having the opposite polarity, a plurality of root taking means of the logarithmic translating type connected in series with the aforesaid multiplying and dividing means, the number of said root taking means being equal to one less than the order of the root to be taken and an antilogarithmic translating device having said multiplying and dividing means connected in its input circuit and said root taking means mutually connected in its input and output circuits and poled to pass an output current proportional to the desired root of the combined products and quotients of the input currents applied to said multiplying and dividing means.

13. The combination as set forth in claim 12 wherein a variable resistor is connected in shunt with one of said root determining logarithmic translating devices for computation of an intermediate fractional root.

14. A circuit for combined multiplication, division and extraction of roots of quantities represented by current inputs comprising a plurality of multiplying and dividing means of the logarithmic translating type connetced in series, said multiplying means having one polarity and said dividing means having the opposite polarity, a number of temperature compensating means of the logarithmic translating type conneoted in series with said multiplying and divi ing means, the number of said compensating means being equal to the sum of the number of said dividing means plus the order of the root to be taken minus the number of multiplying means, the polarity of said compensating means connection being determined by the sign of the sum, said compensating means being connected with the polarity of the multiplying means if the sum is a positive number and with the polarity of the dividing means if the sign of the sum is negative, a plurality of root taking means of the logarithmic translating type connected in series With the aforesaid multiplying, di viding and compensating means, the number of said root taking means being equal to one less than the order of the root to be taken, and an output means of the antilogarithmic translating type operatively connected to all the aforesaid means and operable to produce a current output proportional to the root taken of the combined products and quotients of the input currents.

15. A circuit for combined multiplication, division, and extraction of roots of quantities represented .by current inputs comprising a plurality of multiplying and dividing input diodes connected in series, said multiplying diodes having one polarity and said dividing diodes having the opposite polarity, a number or" compensating diodes connected in series with said multiplying and dividing diodes, said number of compensating diodes being equal to the sum of the number of dividing diodes plus the order of the root to be taken minus the number of multiplying diodes, the polarity of the compensating diode connection being determined by the sign of the sum, said compensating diodes being connected with polarity of the multiplying diodes if the sum is a positive number and with the polarity of the dividing diodes if the sign of the sum is negative, a number of root taking diodes connected in series with the aforesaid multiplying, dividing, and compensating diodes, said number of root taking diodes being equal to one less than the order of the root to be taken, and an output transistor having its base and emitter connected across all of the aforesaid diodes, said root taking diodes being connected in the emitter circuit of said output transistor and of polarity to pass the output transistor emitter current, said output transistor operable to produce through its collector a current proportional to the root of the combined products and quotients of the input currents flowing in said multiplying and dividing diodes.

16. A circuit for combined multiplication, division, and extraction of roots of quantities represented by current inputs comprising a plurality of multiplying and dividing input transistors, each having its collector connected to its base, said input transistors connected in series, said multiplying transistors having one polarity and said dividing transistors having an opposite polarity, a number of compensating transistors, each having its base connected to its collector and connected in series With said multiplying and dividing transistors, said number of compensating transistors being equal to the sum of the number of dividing transistors plus the order of the root to be taken minus the number of multiplying transistors, the

polarity of the compensating transistor connection being 20 determined by the sign of the sum, the compensating transistors being connected with the polarity of the multiplying transistors if the sum is a positive number and with the polarity of the dividing transistors if the sign of the sum is negative, 21 number of root taking transistors, each having its base connected to its collector and connected in series with the aforesaid multiplying, dividing, and compensating transistors, said number of root taking transistors being equal to one less than the order of the root to be taken, and an output transistor having its base and emitter connected across all of the aforesaid transistors, said root taking transistors being connected in the emitter circuit in said output transistor and of polarity to pass the output transistor emitter current, said output transistor operable to produce through its collector a current proportional to the root of the combined products and quotients of the input currents flowing in the multiplying and dividing transistors.

No references cited.

Non-Patent Citations
Reference
1 *None
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US3293450 *Sep 16, 1963Dec 20, 1966Beckman Instruments IncTransfer circuit having wide range antilogarithm response
US3344263 *Feb 24, 1964Sep 26, 1967Bell Telephone LaboraAnalog dividing circuit with a dual emitter transistor used as a ratio detector
US3353012 *Oct 1, 1963Nov 14, 1967Allis Chalmers Mfg CoTransistorized multiplication circuit
US3369128 *Feb 10, 1964Feb 13, 1968Nexus Res Lab IncLogarithmic function generator
US3393306 *Nov 7, 1963Jul 16, 1968Panchanan KunduMultiplier and divider with logarithmic and exponential stages coupled together
US3599013 *Feb 7, 1969Aug 10, 1971Bendix CorpSquaring and square-root-extracting circuits
US3612902 *Oct 16, 1968Oct 12, 1971Bell Telephone Labor IncTemperature-independent antilogarithm circuit
US3638050 *Apr 1, 1970Jan 25, 1972Texas Instruments IncPreamplification circuitry for photoconductive sensors
US3743949 *Jul 23, 1971Jul 3, 1973Westinghouse Electric CorpRms sensing apparatus
US4001602 *Jul 24, 1975Jan 4, 1977The United States Of America As Represented By The Administrator Of The National Aeronautics And Space AdministrationElectronic analog divider
US4004141 *Aug 4, 1975Jan 18, 1977Curtis Douglas RLinear/logarithmic analog multiplier
US4316107 *Feb 28, 1979Feb 16, 1982Dbx, Inc.Multiplier circuit
US6448855Apr 13, 2000Sep 10, 2002Koninklijke Philips Electronics N.V.Accurate power detection circuit for use in a power amplifier
WO2001080421A2 *Apr 3, 2001Oct 25, 2001Koninkl Philips Electronics NvAn accurate power detection circuit for use in a power amplifier
Classifications
U.S. Classification708/843, 327/346, 327/362, 327/360, 327/350, 708/807, 327/356
International ClassificationG06G7/00, G06G7/24
Cooperative ClassificationG06G7/24
European ClassificationG06G7/24
Legal Events
DateCodeEventDescription
Feb 10, 1981ASAssignment
Owner name: FIDELITY UNION TRUST COMPANY, 765 BROAD ST., NEWAR
Free format text: MORTGAGE;ASSIGNOR:CHRYSLER CORPORATION;REEL/FRAME:003832/0358
Effective date: 19810209
Owner name: FIDELITY UNION TRUST COMPANY, TRUSTEE,NEW JERSEY