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Publication numberUS3165644 A
Publication typeGrant
Publication dateJan 12, 1965
Filing dateDec 26, 1961
Priority dateDec 26, 1961
Publication numberUS 3165644 A, US 3165644A, US-A-3165644, US3165644 A, US3165644A
InventorsClapper Genung L
Original AssigneeIbm
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Electronic circuit for simulating brain neuron characteristics including memory means producing a self-sustaining output
US 3165644 A
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Description  (OCR text may contain errors)

2 Sheets-Sheet l G. L. CLAPPER ELECTRONIC CIRCUIT FOR SIMULATING BRAIN NEURON CHARACTERISTICS INCLUDING MEMORY MEANS PRODUCING A SELF-SUSTAINING OUTPUT Jan. 12, 1965 Filed Dec. 26, 1961 INVENTOR GENUNG L. CLAPPER ATTORNEY Jan. 12, 1965 G. L. CLAPPER 3,165,644

ELECTRONIC CIRCUIT FOR SIMULATING, BRAIN NEURON CHARACTERISTICS INCLUDING MEMORY MEANS PRODUCING A SELF-SUSTAINING OUTPUT Filed Dec. 26, 1961 2 Sheets-Sheet 2 FIG. 2

Unitcd States Patent ELECTRGNTC CHECUH FUR SEMULATING BRAEI NETJRQN CHARAQTERHSTICS Th1- CLUDTNG MEMQRY MEANS PRQDUCBIG A SELF-SUSTARNENG @UTPUT Geuuug L Clapper, Vestal, N.Y., assignor to International Business Machines (Iorporation, New York, N.Y., a corporation of New York Filed Dec. 26, 1961, Ser. No. 162,127

2 (Ilairns. (Cl. 30788.5)

The present invention relates to an adaptive logic device and in particular to a device which simulates a physiological neuron.

A neuron is that element of the brain which is the memory cell for intelligence. While the organization of neurons contained in the brain and their method of storing intelligence is not at present understood, some of their characteristics are known.

The present invention has an objectthe simulation of the neuron of the brain by electronic circuitry. By usage of such a circuitry in'experiments in the laboratory and study of the results, insight into how the brain functions and how electronic circuitry may be developed to implement the same may be developed. Thus the primary object of the present invention is to provide apparatus which simulates most of the known characteristics of the neuron cells contained in the brain.

These characteristics are as follows:

(1) Excitation by multiple inputs nonselectively (2) Inhibition over-rides inputs Adaptive threshold changes with neuron usage Refractory period-insensitive after firing Summationinputs integrate Output frequencythe function of inputs and Unit may function in a closed loop Output is binary (all or none) (9) An ability to learn from experiences built in.

While the principal usage of the present invention may at present he in the laboratory as a teaching tool in the study of brain cell activity, it is, at present, also useful in transmission network where bilateral characteristics are desirable.

It is therefore an object of the present invention to provide apparatus which simulates a neuron.

A further object of the present invention is to provide apparatus which generates an output when a given threshold is reached and which contains inhibit means for preventing an output for a predetermined time after the output is generated.

Another and further object of the present invention is to provide apparatus responsive to an input of a given magnitude for generating an output of predetermined frequency in which an input over a given value will be stored and added to the input to increase the output frequency.

Still a further object of the present invention is to provide a device having bilateral transmission characteristics.

Another and further object of the present invention is to provide apparatus which may be set by conditioning the input and output and will remain in this condition until input conditions are reduced below a predetermined minimum.

The foregoing and other objects, features'and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings.

' In the drawings:

FIG. 1 is a circuit diagram of the electronic neuron of the present invention.

FIG. 2 is a system of electronic neurons. e i

The input 11 of the neuron unit, FIG. 1, consists of a 3,165,644 Patented Jan. 12,1965

series of input terminals'lfi, 12, 13, 14, and 15 to which inputs are applied. For the present these inputs shall be considered as DC. Also in the present example an input is considered to be present when the voltage at any terminal rises to ground potential. When there is no input, the voltage thereon will drop to 12 volts. It should be understood here, as in all other instances Where resistances, voltages and other'elements are described particularly, that they may be varied to suit the requirement as to signal levels, time constants, etc.

The network 11 formed by resistances 2630 sums the input voltage signals across a resistor which applies the sum voltage to the base of a transistor 39. The transistor has applied to its emitter a voltage E When the sum of the voltages at input 11 is greater than E the transistor 39 will conduct; This voltage E could for example be 6 volts where the inputs are D.C. signals. In this general situation, approximately 2%. inputs are required to initiate conduction in transistor 39, practically this would necessarily be three inputs, if all are D.C. For pulse inputs, a value such as 8 volts might be desirable, as will be explained subsequently.

The circuit 19 is an integrating pulse shaper and operates to accept signals in pulse or DC. form; integrate the same; and generate a sharply rising and falling output pulse.

When the transistor 39 is biased to conduction by the applied signal at its base, the collector will drop in voltage to E A transistor 43 is normally biased to nonconduction by the 6 volt collector voltage of transistor 39. When the voltage on the collector of transistor 39 drops, the transistor 43 will be biased to conduction, and the collector voltage of transistor 4-3 will rise to ground potential to generate a positive-going output pulse.

The output pulse at the collector of transistor 43 will be reflected across a capacitor 45 to reinforce the bias already applied to the base of transistor 39.

The positive-going output pulse at 25 is applied through a loop 49 to an inhibit circuit 21. This pulse is applied across capacitor 51 through a diode 55 and across a resistor 57 to the base of a transistor 59. A capacitor is charged and will retain the charge after the output 25 drops. The positive voltage applied to this normally'nonconducting transistor causes the same to conduct and drop the collector voltage. The collector of transistor 59 is tied to the input circuit and thus drops the input voltage to 12 volts and isolates the intergrating pulse shaper 19 by back-biasing diode 33. An inhibit input 17 is provided When desired to activate inhibitcircuit 21 to reset the entire adaptive logic unit, FIG. 1. i

The voltage biasing transistor 39 to conduction is thus allowed to decay across resistor 35 to the '12 volt supply. As the voltage at the base of transistor 39 drops below E volts, the transistor current is cut oif, and the collector rises toward +6 volts. As the collector voltage of transistor 39 rises to ground potential or above, the transistor 4-3 connected thereto is cut oif, and the collector of the same drops toward 12 volts and applies this negative-going excursion across capacitor 45 to drive tranhowever desirable to have the inhibit circuit 21 exercise control over the pulse generator 19, and thus the time constants have been chosen-accordingly.

As the inhibit circuit 21 cuts oif, inputs at 11 will reestablish the voltage at point 37 by charging the capacitor 41 until conduction is resumed in transistor 39, and the cycle is repeated' As an illustration of the operation of this portion of the circuit and with 3 DC. inputs applied, the output pulse will be of approximately 2 ms. duration, 'while the time period between pulses, during which the voltage at point 37 is approaching the conduction potential of transistor 39, will be approximately 15 ms. The time period that transistor 59 is conducting is knownas the refractory period and is that period of time in which nooutputs will be generated regardless of the inputs applied. This is about 2 ms. for the present example.

Also connected to the output 25 of pulse generator 19 is a memory circuit 23. As the pulse on output 25 rises from l2 volts to ground, the 12-volt excursion will berefiected across capacitor 83 through diode 31 to charge the capacitor 91. The capacitors 83 and 5 1 are so proportioned that a single pulse from output 25 will charge the capacitor 91 approximately A volt. The A volt bias on the base of a transistor 77 will initiate conduction in the same. When the transistor 77 conducts, the capacitor 91 will discharge through the base emitter connection, resistor 93, diodes 6'7 and 69 to the 12 volt supply. The effective time constant for the capacitor 91, resistor 93 combination is approximately six times as long as the time constant for the pulse generator 19. During this period, therefore, the charge on capacitor 91 caused by a single pulse of output 25 will have time to leak oil and allow the transistor to resume a nonconducting status.

As the circuit has been implemented, the memory 23 contributes approximately the same Weight in input signals that all other inputs together contribute. This, of course, may be varied to suit the circumstances.

In this particular instance where it has been assumed that three inputs have a signal applied thereto, the memory will have substantially no effect on the circuit. This is based on the following considerations. With three inputs present, the signal oil period will be approximately 15 ms, and the transistor 77 drops rapidly from full conduction to nonconduction as the charge on capacitor leaks oil. Based on the time constants, the transistor 77 will be completely nonconducting after approximately 12 ms.

If, however, the number of inputs is increased to four, the sum of input voltages will tend to rise at a higher rate, and the signal oil period will decrease to approximately 10 ms. without memory. In this case, the memory output will be effective during its short time and aid in decreasing the signal off period by adding its input during this period. Thus when four inputs are applied, the memory unit 23 will be elfective to increase the frequency to a higher value over a period of time.

This results from the fact that the output 25 will increase .in frequency and apply charge to the capacitor 11 to build the charge to higher values over a period of time. If it is assumed that during the first 10 ms. signal olf period, the volt charge on capacitor 91 discharges to a voltage of approximately .1 volt, the next pulse from output 25 will raise the charge to .35 volts. As more pulses are generated, the voltage on capacitor increases as a result of these additive charges. Further, of course, the input voltage applied through diode 37, resistor 89 becomes more effective for longer periods and thus increases the frequency of generator 19 which further charges the capacitor 91 at a faster rate.

The charging arrangement for capacitor 91 may be found described in detail in US. patent application, Serial No. 76,263 to Genung L. Clappen.

When the number of inputs are increased to five, the signal off period is decreased to approximately 5 ms. without the memory unit, and the memory will be effective to increase the output 25 to its maximum frequency.

At. this point, all save one input may be removed, and

the unit of FIG. 1 will continue to generate output pulses. This output will be self-sustaining, and the frequency will be somewhere equivalent to three inputs or four inputs. If the last input is discontinued, the output 25 will cease.

While the apparatus of FIG. 1 has been described using DC. inputs to simplify the explanation, it should be understood that pulse inputs are contemplated as equally if not more desirable. This is particularly important since the inputs to the circuit of FIG. 1 will be later described as being of the same time as that generated by the output 25.

As mentioned previously, the pulse generator 19 is an integrating pulse shaper, and the input pulses will be integrated by the capacitor 41 in combination with transistor In determining the effect of pulses applied to each input wherein the excursion is l2 volts to ground, it is only necessary to consider the duty cycle of the input pulses. Thus for a pulse having a 50% duty cycle, the efifect will be 50% of the DC. signal having a magnitude of zero volts. For signals having a lesser frequency, the same criteria may be applied.

In this connection, the voltage -E applied to the emitter of transistor 39 should be lowered somewhat. For example, 8 volts might be dseirable where the inputs applied at 11 are received from outputs 25 from similar devices. This is based on the fact that the fre quencies of the inputs of these devices have been arbitrarily chosen in the present example to run from 50 cycles to 240 cycles per second with a duty cycle of 2 ms. for the output pulse.

The details of the integratin pulse shaper 19 are described and claimed in application Serial No. 161,181 to Genung L. Clapper, now Patent 3,098,939.

Representative values for some of the capacitors shown in FIG. 1 are:

Capacitor: Mfd

In FIG. 2, a plurality of neurons as shown in FIG. 1 have been arranged in a transmission circuit.

For this example consider neuron 111 which will have all the characteristics of the others shown. Five inputs, 123, 127, 14-1, 143, and 1.45, are shown, and these correspond generally to the input at 11, FIG. 1. The word generally is used advisedly since this number is not fixed. Further the input 127, labeled set, must be of a magnitude in combination with an additional input 123, 1351, 143 or 145 sufiicient to activate the memory, such as 23 of FIG. 1, so that the neuron 111 will generate output pulses at on a self-sustaining basis and allow the set input to be removed. It should be noted that an output 157 is shown at both sides of the neuron for convenience. An inhibit line 129 is shown for terminating operation of the neuron.

As the neuron network is arranged, each output from each neuron is connected as an input to three other neurons. For example, the neuron 111 has its output 157 connected as an input to the neurons 113, 115, and 117. Neuron 1119 has an output 159 connected as an input to neurons 113, 115, and 117. Neuron 121 has an output 161 connected as an input to neurons 113, 115, and

117. The neurons 113, 115, and 117 have outputs 141,

143, and which form the inputs of neurons 111, 119, and 121 in a similar manner.

In operation, if the neuron 117 is always conditioned by raising the voltage at input 123 and set input 127, the neuron 111 will generate a self-sustaining series of output pulses on output 157 so long as these inputs are held up. If the neuron 115 is similarly conditioned by raising inputs 133 and 153, the neurons 111 and 115 will exchange pulse outputs. Thus the output 157 of neuron 111 is connected as an input to neuron 115 while the output 143 of neuron is an input to neuron 111. Thus once the neurons have been conditioned to generate a self-sustaining output with only one input, as by set 127 and input 123 of neuron 111, two neurons each activated will sustain the other.

With neurons 111 and 115 in'an activated condition, any input at 123 of neuron 111 or input 133 of neuron 115 will be reflected by an increased output frequency at the output of each. With this arrangement, it can be appreciated that a bilateral transmission network has been created.

If, for example, the neuron 121 was now activated, the sustaining input would be created by output 143 of neuron 115. Neuron 115 would now be conditioned by two inputs 157 and 161 and would have a higher frequency output than either neuron 111 or 121. However, it will be remembered that both neurons 111 and 121 will be efiecte'd by this higher frequency output to' in turn generate a higher frequency output. When this process has stabilized, it can be seen that any input change at 123, 167 or 133 will be suitably reflected in the others. Y

While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by thoseskilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and med voltage must be applied to reach said predeter-' mined summation of voltage for generating an out- P ((1) an inhibit circuit connected-to said integrating pulse shaper and responsive to an output therefrom to become operative to reduce the summed voltage to a predetermined low value, wherein said integrat ing pulse shaper terminates its output; and

(e) a storage circuit included in said inhibit circuit for retaining said inhibit circuit in an operative state to a time subsequent to the termination of the output pulse from said integrating pulse shaper;

(f) a memory responsive to an output from said integrating pulse shaper for generating an output voltage;

(g) means for connecting the output of said memory to said input whereby the condition of memory aids in establishing the output to which .it is responsive, whereby the frequency output of said integrating pulse shaper may be increased;

(It) means contained in said memory unit for establishing the time period through which said output voltage will be generated;

(i) wherein said last-mentioned means is responsive to the frequency of pulse output from said integrating pulse shaper for establishing said time period.

2. A bilateral transmission circuit including'a first and second electronic neuron comprising:

(a) a first input for summing voltages;

(b) a first integrating pulse shaper for generating an output in response to a predetermined summation of voltage;

V (c) a first inhibit circuit for terminating the output from said pulse shaper in response to the output of'said first pulse shaper whereby an output pulse is formed; 1

(d) a first memory circuit responsive to the outputof said first pulse shaper for applying an output voltage to said first input of a substantial magnitude in comparison with said summed voltage;

(e) means contained in said first memory circuit for in dependence on the output frequency of said first pulse shaper; V I (f) whereby a voltage will be established at said first input sufiicient to keep said pulse output from said first pulse shaper self-sustaining by said memory;

(g) .a second input for summing voltages;

(h) a second integrating pulse shaper for generating an output in response to a predetermined summation of voltage;

(i) a second inhibit circuit for terminating the output from saidpulse shaper in response to the output of said second pulse shaper whereby an output pulse is formed; V

(j) a second memory circuit responsive to the output of said second pulse shaper for applying an output volt-age to said second input of a substantial magnitude in comparison with said summed voltage; V V

(k) means contained in said second memory circuit for establishing the time during which the output from said second memory will be available to said second input in dependence on the output frequency of said-second pulse shaper;

(l) whereby a voltage will be established at said second input sutficient to keep said pulse output from said second pulse shaper self-sustaining by said memy; (m) means for connecting the output of the first pulse shaper to the second input; (It) means for connecting the output of the second pulse shaper to said first input;

(0) means for setting said first neuron to generate'a self-sustaining output; and 1 (p) means for setting said second neuron to generate a self-sustaining output, wherein the input of said first or second neuron will be reflected inthe output of said second or first neuron.

References Cited in the file of this patent UNITED STATES PATENTS PutZrath et a1. July 9, 1963 OTHER REFERENCES Two Theorems of Statistical separability in the Perceptron, Cornell Aeronautical Laboratory, Inc., Report No. VG-ll96-G-2, dated 1 September 1958. ASTIA AD No. 203854, pages 6-1l and FIGURE 1.

An Electronic Model of a Nerve Cell, byHarmon and Wolfe, Semiconductor Products,-August1959, pages 36-40.

Bionics Symposiumj WADD Technical Report 60- 600, dated 13-15 September 1960, pages 395-406 and FIG. 1.

Electronics Learns From Biology, by Alan Corneret- 38-54 (page 40 particularly relied on).

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US3097349 *Aug 28, 1961Jul 9, 1963Rca CorpInformation processing apparatus
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US3218475 *Oct 2, 1962Nov 16, 1965Hiltz Frederick FArtificial neuron
US3237025 *Dec 28, 1962Feb 22, 1966IbmComparator circuit
US3317753 *Jun 29, 1964May 2, 1967Rca CorpThreshold gate
US3321639 *Dec 3, 1962May 23, 1967Gen ElectricDirect coupled, current mode logic
US3341821 *Oct 30, 1964Sep 12, 1967Rca CorpAdaptive semiconductor device
US3351773 *May 31, 1963Nov 7, 1967Mc Donnell Douglas CorpElectronic circuit for simulating certain characteristics of a biological neuron
US3496382 *May 12, 1967Feb 17, 1970Aerojet General CoLearning computer element
US3558978 *May 14, 1969Jan 26, 1971Borg WarnerElectronic circuit breaker with gradual and instantaneous cutoff
US3579191 *Oct 27, 1967May 18, 1971Int Standard Electric CorpNetwork using adaptive elements
US3737675 *Dec 15, 1971Jun 5, 1973Lear Siegler IncLatched gating circuit
US3790820 *Sep 27, 1971Feb 5, 1974Texas Instruments IncAutomatically adjustable switching circuit
US4017746 *Jul 18, 1975Apr 12, 1977Nartron CorporationTiming circuit means
US4479241 *Aug 6, 1981Oct 23, 1984Buckley Bruce SSelf-organizing circuits for automatic pattern recognition and the like and systems embodying the same
US4518866 *Sep 28, 1982May 21, 1985Psychologics, Inc.Method of and circuit for simulating neurons
US5293459 *Oct 23, 1991Mar 8, 1994U.S. Philips CorporationNeural integrated circuit comprising learning means
US5355438 *Apr 26, 1993Oct 11, 1994Ezel, Inc.Weighting and thresholding circuit for a neural network
US5361328 *May 7, 1993Nov 1, 1994Ezel, Inc.Data processing system using a neural network
US5504839 *Aug 29, 1994Apr 2, 1996Caterpillar Inc.Processor and processing element for use in a neural network
Classifications
U.S. Classification706/38, 703/3, 326/35, 382/158, 706/26
International ClassificationG06N3/00, G06N3/063
Cooperative ClassificationG06N3/0635
European ClassificationG06N3/063A