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Publication numberUS3171122 A
Publication typeGrant
Publication dateFeb 23, 1965
Filing dateApr 22, 1963
Priority dateApr 22, 1963
Publication numberUS 3171122 A, US 3171122A, US-A-3171122, US3171122 A, US3171122A
InventorsHumpherys Bernarr H
Original AssigneeHumpherys Bernarr H
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Iff system defruiter modification
US 3171122 A
Abstract  available in
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Claims  available in
Description  (OCR text may contain errors)

Feb.- 23,- 9 B. H. HUMPHERYS 3,171,122

IFF SYSTEM DEFRUITER MODIFICATION Filed April 22, 1963 FROM I TO SYNC C RCUIT SYNC CIRCUIT BRACKET 4.000 P DECODE DECODER MODE SEPARATOR DECODER DECODER 1N VEN TOR. BER/VAR H. HUMPHERYS United States Patent 3,171,122 IFF SYSTEM DEFRUITER MODIFICATION Bemarr H. Hnmpherys, Escondido, Calif., assignor to the United States of America as represented by the Secretary of the Navy Filed Apr. 22, 1963, Ser. No. 274,881 5 Claims. (Cl. 3436.5) (Granted under Title 35, U.S. Code (1952), sec. 266) The invention described herein may be manufactured and used by or for the Government of the United States of America for governmental purposes without the payment of any royalties "thereon or therefor.

The present invention relates to an improvement on a system for reducing the adverse effects of interference on IFF display visibility and more particularly, to an improvement on a system for rejecting non-synchronous replies in an IFF system and specifically, to an improved and modified IFF system defruiter.

Co-pending application Serial No. 181,209 filed March 20, 1962, IFF System Defruiter of Bernarr H. Humpherys sets forth a problem facing the users of IFF systems and the manner in which the problem is overcome through the use of the invention set forth in co-pending application Serial No. 181,209.

Briefly, the tdefruiter of co-pending application 181,209 operates to remove the IFF interference by first bracketdecoding wideband IFF signals to produce a relatively narrow-band pulse. This pulse is set down a delay line to form a gate signal delayed by the amount of the interpulse. The gate then swings open for the next expected wide-band response but remains closed for all others. In such a narrow-band application it is possible to use a much less expensive magnetostriction type of delay iine.

In using the aforementioned system of co-pending application 181,209 it was noted that the IFF system de fruiter implementation required an inordinately large number of interconnecting cables and made the defruiter equipment fairly incompatible for use with existing switch board equipment. In order to obtain compatibility with existing switchboard equipment other systems were tried which sent the bracket decode pulse "through a delay line to produce a finger-gate Le. 14 pulses and then coincidized the output of this delay line with the input IFF train which is delayed one train length to obtain an output. In such a system a high cost delay line is needed in that the delay line must be one having very high fidelity in order to preserve the intelligence contained in the IFF train.

In the system of co-pending 181,209 the output of the emitter follower 19 of FIG. 1 was utilized to enable the various decoders in the system. This required an output be taken from the emitter follower to each of the decoders which led .to the large number of interconnecting cables and made the system incompatible with existing switchboard equipment now in use.

An object of the present invention is to provide a modified and improved IFF system defruiter.

A further object of the present invention is to provide an IFF system defruiter which is compatible with existing switchboard equipment.

Another object of the present invention is to provide a modified IFF system defruiter which is compatible with switchboard equipment and which utilizes low cost noncritical components.

A further object of the present invention is to provide an IFF defruiting system which is-compatable with conventional IFF systems and is easy and practical to adapt to radar systems now in existence.

Other objects and many of the attendant advantages of this invention will be readily appreciated as the same ice becomes better understood by reference to the following etailed description when considered in connection with the accompanying drawings wherein the accompanying figure is a block diagram of the IFF system modification.

In order to better understand the present invention a brief rsum of the system of co-pending application Serial No. 181,209 is presented. In that system the technique for reducing the adverse effects of fruit on IFF display visibility is based on utilizing a bracket decode technique and a conventional delay line. All replies which do not change position in time with respect to the challenging pulses from one interrogation cycle to the next are accepted as legitimate replies. Conversely, replies which change their relative time position by a predetermined amount from interrogation cycle to cycle are rejected as being non-synchronous.

To separate locked and unlocked replies in accordance with the preceding basis, all bracket decoded signals received in reply to one interrogation are delayed for at least one interrogation period and compared in a coincidizing gate with replies received during a second or later interrogation period. Output signals derived from the coincidizing gate represent locked replies and thereby reduced unlocked replies and fruit.

In the technology of the art fruit is considered to be unsynchronized replies from associated transponders as well as the replies to the other interrogators operating in the vicinity of the associated transponders. In that the latter replies are not synchronous, they constitute a.

form of interference generated by the system itself. These unsynchronized replies appear as interference on the face of the A scope in the IFF system and as previously stated are referred to as fruit.

In the operation of the invention as set forth in the accompanying figure, unseparated video from an IFF receiver is brought in at input 10 and coupled into a bracket decode 1 1. The bracket decode 11 is a delay line having taps thereon spaced apart a distance corresponding to the start and stop pulses of the reply train coupled in at input 10. The bracket decode 11 decodes and coincidizes start and stop pulses to produce a single output pulse.

The output pulse from the bracket decode 1 1 is coupled through an OR gate 12 to a 4,000 microsecond magnetostric'tive delay line 13. The length of delay line 13 may vary, however, in this instance the choice of 4,000 microseconds is an arbitrary one in that the repetition rate of the radar system is 250 cycles per second. However, it is to be understood that the magnetostric'tive delay line 13 may have various output taps thereon which may be utilized so that it may be used with radar systems having pulse repetition rates other than 250 rates.

The output of the delay line 13 is then amplified in an amplifier 14 before being coupled to another delay line 15. Delay line 15 is used in this instance to compensate for circuit characteristics and may be adjustable to provide a fairly wide range of compensation. The output of the delay line 15 is coupled through an amplifier 16 for further amplification and then forms one input to AND gate 17.

In addition, another input to AND gate 17 comprises the output from bracket decode :11. Thus, when outputs from the amplifier 16 and bracket decode 11 are present at the input of the AND gate 17 an output pulse will be coupled to an amplifier emitter follower 18. The output of the amplifier emitter follower 18 comprises defruited bracket decode pulses which are used as enabling pulses further on in the system.

The unseparated video is also coupled from input 10 as one input to an inhibit gate 19 the other input to which comprises the output of the bracket decode 11. The output from bracket decode 11 comprises an inhibit pulse for the gate 19 so that in the presence of the decoded start stop pulse from decode 11 which in eifect is the stop pulse of the reply train the output of gate 19 will be inhibited. The output of gate 19 and the output of amplifier emitter follower 18 are coupled through OR gate 20, amplified in an emitter follower 21 and coupled to a mode separation circuit 22. The mode separated video is coupled then to decoders 23-25 and the outputs of the decoders displayed or utilized in any suitable fashion.

In addition, in order to synchronize the IFF system with an associated radar system it is necessary that some sort of synchronization be attained between the two. In order to provide this the output from the amplifier 14 is coupled through a synchronization circuit comprising a pulse separator trigger generator, differentiator and some amplification stages, not shown, as set forth in the co-pending application Serial No. 181,209. The output of the synchronization circuit is coupled back to the input of the OR gate 12 and in this fashion the IFF defruiter is synched to the radar system in that the defruiter supplies the trigger pulses for the radar.

Operation In operation, the unseparated video comprising a pulse train having start stop pulses spaced therebetween is coupled in at input and the start and stop pulses coincidized in the bracket decode 11 to provide an output pulse in the stop position. The output pulse from decode 11, corresponding to the stop pulse, is then coupled through the OR gate and delayed one repetition period in delay line 13 and coupled back to the input of the AND gate 17. The bracket decoded start stop pulse from the bracket decode 11 from the next pulse train also coupled to the AND gate 17 and when the delayed stop pulse is in coincidence with a stop pulse from the bracket decode 11 the AND gate produces an output which is coupled through the emitter follower amplifier 18 and through the OR gate 29 to the mode separator.

At the same time that this is happening unseparated video is coupled through the gate 19. However, the stop pulse is removed from the unseparated video due to the fact that the stop pulse, i.e. the bracket decoded start and stop pulses is used as an inhibit pulse for the gate 1 9. In that the decoders require a stop pulse before decoding will take place, even though the unseparated video is coupled through the emitter follower and the mode separator no decoding takes place. However, whenever a stop pulse appears at the output of the AND gate 17 and is coupled through the amplifier 18 and buffer to the mode separator the stop pulse is in effect reinserted. Due to the fact that the stop pulse which is reinserted indicates a synchronous return defruiting is also accomplished.

In the present system, as in co-pending application Serial No. 181,209 the bracket pulses are examined only to determine whether a locked reply has been received and whether the reply is synchronous.

In addition, in that the bracket decode pulses are available at the output of emitter follower 17 they might be displayed directly which would provide an all-mode presentation.

It is also to be understood that the delays might be cascaded to obtain 3, 4, 5 or any number of steps of comparison i.e. defruiting.

The modified defruiter systems advantage as set forth in the present invention over the prior systems is due to the fact that the system may be implemented and still be adaptable with present switchboard systems. In addition this adaptability is obtained without the use of high cost delay lines while retaining the advantageous features of the system as set forth in co-pending application Serial No. 181,209.

Another way of implementing the system would be to use the delay bracket decode pulse from AND gate 17 as an inhibit pulse for inhibiting bracket decodes which are fed to the inhibit gate 19.

Obviously many modifications and variations of the present invention are possible in the light of the above teachings. It is, therefore, to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described.

What is claimed is:

1. An IFF defruiter modification comprising:

bracket decode means for decoding selected pulses of an interrogation reply train and having inputs and outputs;

one of said inputs being adapted for receiving IFF video;

delay means operatively connected to an output of said bracket decode means for delaying the output of said bracket decode means by an amount comprising at least one reply train length; coincidizing means having inputs and an output; one input to said coincidizing means being operatively connected to the output of said delay means, another input of said coincidizing means being operatively connected to an output of said bracket decode means;

said coincidizing means being operable to produce an output pulse therefrom when outputs from said delay means and said bracket decode means are present at the inputs simultaneously;

another coincidence means having inputs and an output therefrom;

one input of said another coincidence means being adapted for receiving IFF video;

another input of said other coincidizing means being operativeiy coupled to the output of said bracket decode means and corresponding to an inhibit pulse on said coincidizing means;

said another coincidence means being operable to produce no output when an output from said bracket decode means is present at said input;

said output pulse from said first mentioned coincidizing means being operative to provide an enabling pulse for a decoding operation on said received IFF video.

2. A system for rejecting non-synchronous replies comprising;

input means adapted for receiving an input pulse train having start stop pulses;

bracket decode means for providing an output pulse when start stop pulses are present simultaneously in said bracket decode means;

delay means operatively coupled to the output of said bracket decode means for delaying the output pulse from said bracket decode means by one reply train interval;

coincidence means operatively coupled to the output of said delay means and said bracket decode means for producing an output pulse when pulses from said delay means and said bracket decode means are coincident therein;

gate means operatively coupled to said input means and the output of said bracket decode means; the output of said bracket decode means which is coupled to said other coincidence means operating to inhibit said other coincidence means when an output pulse from said bracket decode means is present;

said output pulses from said coincidizing means providing an enabling pulse for a decoding operation on pulse trains received on the input and coupled to said gate means.

3. A system for rejecting non-synchronous replies comprising;

input means adapted for receiving an input pulse train;

bracket decode means for providing an output pulse when a start and stop pulse of a pulse input train are present simultaneously in said bracket decode means;

delay means operatively coupled to the output of said bracket decode means for delaying output pulses therefrom a predetermined time interval corresponding to at least one reply train length;

coincidence means operatively coupled to the output of said delay means and said bracket decode means for producing an output pulse when pulses from said delay means and said bracket decode means are coincident therein;

gate means operatively coupled to said input means and also coupled to the output of said bracket decode means for receiving input pulse trains from said input and for receiving decoded start and stop pulses from said bracket decode means;

said gate means being operable to remove the stop pulse from said received input pulse train so that normally said pulse train received at said input could not be decoded;

buffer means operatively coupled to the output of said coincidence means and said gate means for receiving output pulses from said coincidence means corresponding to delayed coincidized start stop pulses from said bracket decode means and receiving pulses from said gate means corresponding to an input pulse train minus a stop pulse;

said buffer means being operable to restore said stop pulse by inserting the pulse from said coincidizing means corresponding to a delayed bracket decoded pulse;

said output pulse from said coincidizing means being operable as an enabling pulse for a decoding operation on said received pulse trains.

4. A system for rejecting non-synchronous replies as set forth in claim 3 and further including;

mode separation means having an input and outputs therefrom for separating the received pulse trains; said input to said mode separation means being operatively connected to the output of said buifer means.

prising;

input means adapted for receiving an input pulse train;

bracket decode means for providing an output pulse When a start and stop pulse from said input pulse train are coincident in said bracket decode means, said bracket decode means being connected to said input means;

delay means operatively coupled to the output of said bracket decode means for delaying output pulses from said bracket decode means a predetermined time interval;

coincidence means operatively coupled to the output of said delay means and said bracket decode means for producing an output pulse when pulses from said delay means and said bracket decode means are coincident at the input simultaneously;

the output of said coincidence means corresponding to a delayed stop pulse from the output of said bracket decode means;

means for removing the stop pulse from the received input pulse train operatively coupled to said input and also coupled to the output of said bracket decode means;

mode separation means operatively coupled to the output of said coincidence means and the output of said means for removing the stop pulse from said pulse train;

said mode separation means being operative to receive the input pulse train minus a stop pulse from said means for removing said stop pulse and also receiving a delayed stop pulse from said coincidence means;

said output pulse from said coincidizing means being operable as an enabling pulse for a decoding operation on said input pulse train.

No references cited.

CHESTER L. JUSTUS, Primary Examiner.

Non-Patent Citations
Reference
1 *None
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6819282 *Apr 3, 2002Nov 16, 2004Universta' Degli Studi Di Roma “Tor Vergata”Super-resolution processor/receiver to discriminate superimposed secondary surveillance radar (SSR) replies and squitter
US20040233095 *Apr 3, 2002Nov 25, 2004Gaspare GalatiSuper-resolution processor/receiver to discriminate superimposed secondary surveillance radar (ssr) replies and squitter
Classifications
U.S. Classification342/45, 455/296
International ClassificationG01S13/78, G01S13/00
Cooperative ClassificationG01S13/782, G01S13/784
European ClassificationG01S13/78B2, G01S13/78B3