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Publication numberUS3212203 A
Publication typeGrant
Publication dateOct 19, 1965
Filing dateFeb 12, 1963
Priority dateFeb 12, 1963
Publication numberUS 3212203 A, US 3212203A, US-A-3212203, US3212203 A, US3212203A
InventorsAtkinson John F
Original AssigneeRobert L Silber
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Test grading machines
US 3212203 A
Abstract  available in
Images(9)
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Claims  available in
Description  (OCR text may contain errors)

Oct. 19, 1965 F. ATKlNSON 3,212,203

TEST GRADING MACHINES Filed Feb. 12, 1963 9 Sheets-Sheet l I NVENTOR Oct. 19, 1965 J. F. ATKINSON TEST GRADING MACHINES 9 Sheets-Sheet 2 Filed Feb. 12, 1963 REESE 5555 5255 W EEEE D mun -m ums-mm m-m-mm 6 00 E fir 3 3 3 Oct. 19, 1965 Filed Feb. 12, 1963 NPUTS A5 B5 C5 D5 ABt 1. t

J. F. ATKINSON TEST GRADING MACHINES AND GATE

9 Sheets-Sheet 3 OUTPUT INVENTOR Oct. 19, 1965 J. F. ATKINSON 3,

TEST GRADING MACHINES Filed Feb. 12, 1963 9 Sheets-Sheet 4 INPUTS s 5 1. 1:

OUTPUT IN VENTOR Oct. 19, 1965 Filed Feb. 12, 1963 INPUTS J. F. ATKINSON TEST GRADING MACHINES PIC-3.5

9 Sheets-Sheet 5 OUTPUT INVENTOR Oct. 19, 1965 so 3,212,203

TEST GRADING MACHINES Filed Feb. 12, 1963 9 Sheets-Sheet 6 INPUTS INHIBIT GATE INHIBIT GATE INHIBH' GATE AND GATE.

FIE-3.6 2MM7W INVENTOR OUTPUT Oct. 19, 1965 J. F. ATKINSQN 3,212,203

TEST GRADING MACHINES Filed Feb. 12, 1963 9 Sheets-Sheet 7 SOLENOID INVENTOR INT Oct. 19, 1965 J. F. ATKINSON TEST GRADING MACHINES Filed Feb. 12, 1963 9 Sheets-Sheet 9 ZOE-500 INVENTOR United States Patent Q 3,212,203 TEST GRADING MACHINES John F. Atkinson, Arlington County, Va., assignor of one-half to Robert L. Silber, Takoma Park, Md. Filed Feb. 12, 1963, Ser. No. 258,273 Claims. (Cl. 3548) The present invention relates to test grading machines for processing test papers of the multiple-choice type, and more particularly to machines for grading answer forms selectively marked by the examinee.

The present invention utilizes novel digital data processing techniques to compare answer forms, selectively marked by the examinees, with a key answer form selectively marked by the examiner.

The present invention provides novel means for automatically imprinting error indicating marks on the examinees answer forms opposite each wrong answer, opposite each omission and opposite each redundant answer.

A novel arrangement of moving and stationary parts simplifies construction of the machines and makes them easy to operate.

Heretofore, test grading machines for automatically processing test papers were relatively complex and expensive, and because of these disadvantages they were never suitable for individual classroom use. Another disadvantage of such test grading machines is the time delay in getting test papers to and from remotely located machines. An interval of several days or weeks may sometimes elapse when the grading machine is located in another city. Still another disadvantage of such machines is that they do not identify the individual wrong answers, nor do they detect and identify redundant answers.

These disadvantages detract from the general effectiveness of the teaching and testing process, because many a student loses interest in the subject matter during the long interval between his taking the test and his reviewing the results.

Among the objects of my invention is to provide improved automatic test grading machines that are relatively simple and inexpensive. Another object is to provide test grading machines that can be kept and used in individual classrooms so that test forms can be graded and returned to the students immediately upon completion.

The above as well as still further objects of the present invention will become more readily apparent from the following description of its exemplification, reference being made to the accompanying drawings wherein:

FIGURE 1 is a pictorial view of the external embodiment of my invention.

FIGURE 2 shows an example of one type of selectively marked answer form used by the examinee and by the examiner.

FIGURE 3 is the logic diagram for processing the digital data through a machine equipped to accommodate eight input variables.

FIGURE 4 is the logic diagram for processing the digital data through a machine equipped to accommodate four input variables.

FIGURE 5 is the logic diagram for processing the digital data through a machine equipped to accommodate six input variables.

FIGURE 6 is the logic diagram for processing the digital data through a machine equipped to accommodate ten input variables.

FIGURE 7 is a schematic electrical diagram for the implementation of the logic process shown in FIGURE 3.

FIGURE 8 is a detail drawing of the error marking mechanism.

FIGURE 9 is a diagrammatic representation of the movable housing, the error marking mechanism, the

ice

ON-OFF switch, the slide stop, the switch interlock, the form alignment mechanism and the form ejector mechanism.

For the novel mechanical features and arrangement of parts, reference is specifically made to FIGURE 1, in which the baseboard 10 is a stationary member that supports a movable housing member 11 which slides forward and backward over the face of the baseboard along tracks 12 and 13 which consist of slots milled in the side edges of the baseboard. The directions of the sliding motion of movable housing 11 are shown by double arrow 28. Examinees form 15 and examiners form 16 are shown in their respective places prior to scanning. The examinees form is held in place by retainer guides 17 and 18. These guides prevent a sideward movement of the form, but will permit it to be ejected by a sliding motion to the rear. Form stop 19 prevents the examinees form from sliding forward beyond the form stop. Retainers 20 and 21 hold the examiners key form 16 in place and in alignment with form 15. Sliding motion of form 16 is prevented by form stops 22 and 23. Plate 24 is secured to the baseboard by pivotal screw 25. Direction of pivotal motion of plate 24 is shown by arrow 27. Plate 24 rests on top of the lower edge of form 16 preventing the form from curling up and interfering with the sensors during scan retrace. Stop 26 limits the forward motion of movable housing 11, and also serves to actuate a switch which will be explained later in this specification. Hole 27 passes through baseboard 10 and its purpose will be explained later also.

Movable housing 11 contains the entire digital data processing assembly comprising sensors for deriving digital input data from forms 15 and 16, transistor logic gates for processing the data, readout mechanism for recording errors detected and a battery-type power supply consisting of a small transistor-type battery and several flashlight-type cells. Compactness and economy are further achieved through the use of printed circuitry.

To operate the machine, the operator sits in front of the machine, grasps handle 37 and slides the movable housing 11 all the way to the rear of the baseboard where a rear slide stop, similar to front slide stop 26, stops movable housing 11 from further rearward travel and simultaneously operates a switch, mounted on the bottom of the movable housing, to turn on electrical circuits of the data processing elements. Next, the operator inserts examiners key form 16 in its place and then inserts examinees form 15, the first form to be graded, in its respective place. The operator then grasps handle 37 and slides movable housing 11 forward. A protruding leaf-spring member 32, attached to movable housing 11, momentarily engages the top edge 31 of form 15, pushing the form forward until its edge 29 rests against form stop 19. In this position the form is in proper alignment with key form 16 for simultaneous scanning. Upon further forward motion of movable housing 11, member 32 overrides edge 31 and the scanning operation is commenced. The sensors within the movable housing scan both forms simultaneously, one line at a time, beginning at the top of the form at line number 1 and ending at the bottom of the form beyond the last line. Errors detected are automatically marked with permanent-type ink on form 15 in the error column with a mark placed adjacent to each incorrect answer.

Upon completion of the scan, the movable housing is brought to rest against front slide stop 26 which, by resisting the scanning motion, also serves to actuate the switch to turn of} the electrical circuits of the data processing elements for the scan retrace operation.

The operator then slides the movable housing to the rear of the baseboard, thus performing the scan retrace operation. In so doing the bottom edge 29 of form 15 is engaged by protruding leaf-spring member 125 (shown in FIGURE 9), attached to movable housing 11, and form is pushed to the rear and ejected from the baseboard. The switch is again turned on by the scan retrace motion. The way is now cleared for insertion of the next form to be graded. The cycle is then repeated for each form graded.

When the last form has been graded, the operator pulls movable housing 11 all the way forward and brings it to rest against stop 26. This action again switches ofl the electrical circuits of the data processing elements. When movable housing 11 is resting against stop 26, the error marking ink pen is positioned directly above hole 27. The storage cap for the ink pen may be inserted from the bottom of the baseboard up through hole 27 and brought into engagement with the ink pen. The cap, when engaged, protrudes part way through hole 27, thereby locking the movable housing to the stationary baseboard and preventing further movement of movable housing 11 with respect to the baseboard. The ink pen cap thus serves as a mechanical interlock to prevent the switch being turned on or being left on during periods of storage.

Referring now to FIGURE 2, form 15 represents an examinees selectively marked answer form. Answer lines are serially numbered 1 through 30, each line con taining multiple-choice boxes designated by columns A, B, C and D.

The examinee designates the answer of his choice by completely filling-in the appropriate box, such as is shown in box 35, with a soft lead pencil, preferably one of the type known as an electrographic lead pencil. A space is designated and reserved opposite each numbered answer line in which errors may be automatically marked,

preferably'with permanent-type colored ink of the quick drying type, such as may be found in felt pen marking devices. Error marks are shown in spaces 38, 33 and 34.

Form 16 of FIGURE 2 represents the examiners key form on which the examiner marks the correct answers. Form 16 may be identical with that of form 15, but in use the examiner does not utilize the spaces designated for error marks. The examiner designates correct answers by marking a horizontal line through the center of the selected box, such as is shown in box 36, with a soft lead pencil, taking care not to completely fill in the box as must be done on the examinees card by the examinee. This method of marking, when sensed during scanning, will produce wide digital pulses from the examinees form and relatively narrow digital pulses from the examiners form. When the two forms are properly aligned, a pulse derived from the examinees form, for a given answer, will begin before the pulse derived from the corresponding answer on the examiners form begins, and will end after the pulse derived from the examiners form ends. The purpose of this arrangement being to simplify the logic circuitry, particularly with respect to the INHIBIT gates. This arrangement insures that an INHIBIT pulse, derived from the examinees form, begins before and remains after the error pulse derived from the examiners form. This arrangement also permits greater mechanical tolerances in the scanning equipment.

It should be particularly noted that error pulses are normally derived from markings on the examiners form, except that error signals may also be derived from redundant answers on the examinees form. INHIBIT pulses are derived from the examinees form.

A novel logic process for detecting errors on an examinees selectively marked form, by simultaneous comparison with a correctly marked examiners form, is shown by means of the following Boolean algebraic expression:

in which the variables A 3,, C and D, represent the binary states of digital signals simultaneously derived from markings on an examiners key form, a mark representing a binary one and no mark representing a binary zero. Similarly, the variables A B C and D represent the binary states or digital signals, also simultaneously derived, from corresponding markings, respectively, on the examinees form.

When the above expression is evaluated, the result is either unity or zero. If the result is unity, the examinees answer is in error. If the result is zero, the examinees answer is correct.

The four INHIBIT terms of the above expression account for errors of commission and errors of omission. An error of commission is an error resulting from the examinees marking a wrong answer. An error of omission is an error resulting from the examinees failing to mark any answer.

The remaining terms of the above expression account for error of redundancy. An error of redundancy is defined as an error resulting from the examinees marking two or more answers to a single question.

An application of this logic process is illustrated herewith, using the marks shown on form 15 and form 16 of FIGURE 2.

Expressing the binary states of the variables in accordance with the marks shown on form 15 and form 16, we have Examiuces Form 15 Examiner's Form 16 Line No.

A! B3 C; D; At B; Cg D;

a line at a time, and evalterm by term, we have for line 1,

The result of zero means that the answer given by the examinee on line 1 is correct. For line 2,

The result of one means that the answer given by the examinee on line 2 is in error. This is so indicated by the error mark shown in error column space 38. This error represents an error of commission. For line 3,

The result of one means that the answer g ven by the examinee on line 3 is in error. This is so indicated by the error mark in error column space 33. This error represents an error of omission. For line 4,

The result of one means that the answer given by the examinee on line 4 is in error, and the error mark in error column space 34 so indicates. This represents an error of redundancy. For line 5,

The'result of zero for line 5, line 6 and line 30 means that the examinees answers are correct on these lines.

The logic expression just described is illustrative of an eight-variable system. It can be expanded or contracted to n variables.

An eight-variable system will be explained in detail at length herewith, but in practice a similar ten-variable system, a four-variable system or a six-variable system may sometimes be preferable. They all utilize these same principles as described herein and can be readily understood from the description of the eight-variable system.

FIGURE 3 shows how logic function gates are combined to process input data derived from the examiners and the examinees marked forms. The processed data represent evaluations of the expression For example, an input pulse designated A derived by sensing the marked space in column A, line 1, form 16 of FIGURE 2, enters INHIBIT gate 41 by means of conductor 40. Input pulse A will pass through this IN- HIBIT gate unless inhibited by input pulse A derived by simultaneously sensing the marked space in column A, line 1, form 15 of FIGURE 2. A enters INHIBIT gate 41 by means of conductor 42. Likewise, INHIBIT gates 43, 44 and 45 will pass input pulses B 0, and 5, respectively, unless inhibited by input pulses B C and D respectively.

INHIBIT gate 41 performs the Boolean function A -Z INHIBIT gate 43 performs the functions B -F INHIBIT gate 44 performs the function C 6 and INHIBIT gate 45 performs the function D D OR gate 46 accepts and passes the outputs from any of the INHIBIT gates. The output of OR gate 46 may be represented by the expression t s-l t s lt' s lt' s OR gate 47 accepts input pulses B C and D and passes one or any combination of them to AND gate 48 where they are ANDed with input pulse A The function of OR gate 47, combined with AND gate 48, may be represented by the expression OR gate 49 accepts input pulses C and D and passes either or both to AND gate 50- where they are ANDed with input pulse B The function of OR gate 49, combined with AND gate 50, may be represented by the expression AND gate 51 ANDs input pulses C and D The function of AND gate 51 may be represented by the expression The outputs of AND gates 48, 50 and 51 are accepted and passed by OR gate 52, the resulting function being represented by the expression s( s+ s+ s) s( s+- s) i s' s The output of OR gate 46 is also accepted and passed by OR gate 52. The combined output of OR gate 52 may be represented by the desired expression When the evaluation of this expression is unity, an output pulse is emitted from OR gate 52. This output pulse is used to actuate an error marking device. No output pulse from OR gate 52 means no error has been detected.

FIGURE 4 shows similarly how logic function gates are combined to process input data for a system of four 6 variables. This represents the True-False species of test grading machine. The processed data represent evaluations of the expression Examinees errors of commission, errors of omission or errors of redundancy will result in evaluations of unity. Examinees correct answers will result in evaluations of zero.

FIGURE 5 shows similarly how logic function gates are combined to process input data for a system of six variables. This represents the three-multiple-choice species of test grading machine. The processed data represent evaluations of the expression Examinees errors of commission, errors of omisison or errors of redundancy will result in evaluations of unity. Examinees correct answers will result in evaluations of zero.

FIGURE 6 shows similarly how logic function gates are combined to process input data for a system of ten variables. This represents the five-multiple-choice species of test grading machine. The processed data represent evaluations of the expression s+ s) s( s+ s+ s) s( s+ s) s' s where the variables E and E represent the binary states of additional corresponding digital signals, also simultaneously derived, from markings on examiners and examinees answer forms, respectively.

Examinees errors of commission, errors of omission or errors of redundancy will result in evaluations of unity. Examinees correct answers will result in evaluations of zero.

FIGURE 7 shows the schematic electrical diagram for implementing the eight-variable logic process shown in FIGURE 3 and described above. Sensors 60, 61, 62, 63, 64, 65, 66 and 67 each are brush pairs designed to make contact with and complete a circuit through graphite pencil marks on the answer forms. One brush of each pair has a common connection to the negative terminal of transistor battery 68. During the scanning operation, when contact is made and circuit completed through a pencil mark on an answer form, a negative pulse is generated, said pulse representing an input signal. Pulses derived through sensors 60, 61, 62 and 63 originate from data on the examiners key answer form and are designated A B C, and D,,, respectively. Pulses derived through sensors 64, 65, 66 and 67 originate from data on the examinees answer form and are designated A B C and D respectively. Transistors 69, 70, 71 and 72 are the active elements in the INHIBIT gates associated with inputs A, and A B and B C and C and D and D repsectively. Transistors 73, 74, 75 and 76 are the active elements in the AND gate and OR gate combination associated with inputs A B C and D Transistors '77, 78 and 79 are the active elements in the AND gate and OR gate combination associated with inputs B C and D Transistors 80 and 81 are the active elements of the AND gate associated with inputs C and D Resistors 82, 83, 84 and 85 perform resistor OR logic for combining and passing the outputs of the INHIBIT gates, and transistor 86 amplifies said OR logic pulses to a level suitable for driving relay 87 which in turn drives error marking solenoid by means of solenoid battery 89. Combining or ORing of the AND gate outputs is accomplished by parallel connections which in turn are connected to relay 87. Protective diode 9t) protects transistors by suppressing inductively produced voltage spikes that originate in the operating coil of relay 87 All other resistors shown but not numbered serve primarily as current limiting resistors to hold down currents to within the ratings of the transistors.

Transistors 91, 92, 93 and 94 serve as current amplifiers to boost the input pulses A B C and D to insure that the INHIBIT transistors are driven into saturation. Switch 95 opens the transistor battery circuit for scan retrace and for storage. The logic circuitry is designed to draw very little current with switch on during standby operation, it drawing less than one milliampere. Error pulses may draw up to 60 milliamperes from the transistor battery for periods of 20 to 30 milliseconds, the approximate duration of the pulses. So it can be seen that long life may be expected from the transistor battery. Long life may also be expected from the solenoid battery, since the solenoid is pulsed only when an error is encountered.

Referring to the error marking mechanism shown in FIGURE 8, solenoid 88 is attached to bracket 101 which in turn is mounted within and attached to movable housing 11. Directions of motion of movable housing 11 are shown by double arrow 108. Solenoid plunger 102 is connected by linkage 103 to the body of felt-tipped ink pen 104. The connection to the body of the felt-tipped ink pen is made with a clamp-type connector 110, secured by screw 111 to facilitate easy removal and replacement of felt-tipped ink pen 104. The felt-tipped ink pen is supported by guides 105 and 106 which limit its relative movement to vertically sliding action with respect to movable housing 11. The vertical movement is activated downward by solenoid plunger 102 and upward by return spring 109. The felt tip 107 of the inking device is positioned about one-eighth inch above examinees form when the solenoid 100 is deenergized. When the solenoid is energized momentarily by an error signal pulse, the ink pen is drawn down momentarily and felt tip 107 makes contact with examinees form 15, producing an ink mark in a designated place on examinees form 15 opposite the incorrect answer. This ink mark signifies an error. The point of contact of the felt-tipped ink pen with the examinees form, and the points of contact of the sensor brush pairs with the examinees and examiners forms, lie in a straight line that is perpendicular to the direction of motion of movable housing 11 and parallel to the plane of the top surface of baseboard 10. This insures that the error mark imprint registers on the same line as that containing the incorrect answer.

Referring to FIGURE 9, a side view of movable housing 11 is shown in scanning position Y. Arrow 108 shows direction of forward motion of housing 11 during scan, relative to stationary baseboard 10. Shown attached to movable housing 11 are error marking pen 104, switch 95 with operating handle 122, card alignment mechanism 32 and card ejector mechanism 125. The movable housing assembly is also shown by dotted lines in position Z and in position X. These positions are the positions of movable housing 11 at beginning and end of scan, respectively. At the end of scan, switch operating handle 122 makes contact with stop 26. Stop 26 performs two functions: It stops the scanning motion of housing 11 and it bears against switch operating handle 122 turning of} switch 95. With switch 95 ofi, the machine is de-activated during scan retrace. Scan retrace is accomplished by the operators sliding movable housing 11 rearward in the direction shown by arrow 109. At the end of scan retrace, shown by position Z, operating handle 122 of switch 95 makes contact with stop 120. Here, two functions are performed by stop 120: Motion of movable housing 11 is stopped and operating handle 122, bearing against stop 120, turns switch 95 on, activating the machine for the scanning operation on the next examinees form.

Automatic alignment of examinees form with examiners form is accomplished in the following manner: Starting from position Z, movable housing 11 is slid toward position X. Leaf-spring member 32, protruding from the edge of movable housing 11, engages top edge 31 of examinees form 15, Continued movement pushes 0 examinees form 15 until it comes to rest against form stop 19.

Examinees form 15 is now properly aligned with examiners form, 16 shown in FIGURE 1. Leaf-spring member 32, being flexible, overrides edge 31 as movable housing 11 continues its motion toward position X.

Automatic ejection of examinees form 15 is accomplished in the following manner: Starting from position X, movable housing 11 is slid toward position Z. Leaf-spring member 125, protruding from movable housing 11, engages the bottom edge 29 of examinees form 15 and the scan retrace motion pushes it off the baseboard to the right of and beyond position Z.

The mechanical switch interlock works in the following manner: When movable housing 11 is in position X, switch is off and ink pen 104 is aligned directly above hole 27 in baseboard 10. Ink pen cap 124 can then be inserted from the bottom of the baseboard into hole 27 and into engagement with collar 123 of ink pen 104. When the cap is thus engaged, its partial protrusion into the hole 27 locks movable housing 11 to baseboard 10 in position X. The switch 95 is thus locked in the of} position and cannot be turned on until movable housing 11 is unlocked and slid into position Z.

Having described my invention, What I claim is:

1. A test grading machine comprising the combination: input means for producing binary digits of pulsed input data derived from examiners and examinees selectively marked answer forms; an array of Boolean logic function gates connected to said input means to accept said digital input data, said array being described by the Boolean expression where A B C D,, and E, are input variables representing the binary states of said digital input data, simultaneously derived from said examiners answer form, and

A B C D and E are input variables representing the binary states of corresponding digital input data, respectively, also simultaneously derived, from said examinees answer form; and readout means, connected to the output of said array of logic function gates to receive an actuating impulse when the evaluation of said Boolean expression is unity.

2. A test grading machine comprising the combination: input means for producing binary digits of pulsed input data derived from examiners and examinees selectively marked answer forms; an array of Boolean logic function gates connected to said input means to accept said digital input data, said array being described by the Boolean expression s+ s) 'i' s( s+ s)+ s' s where A 13,, C, and D are input variables representing the binary states of said digital input data, simultaneously derived from said examiners answer form, and A B C and D are input variables representing the binary states of corresponding digital input data, respectively, also simultaneously derived, from said examinees answer form; and readout means, connected to the output of said array of logic function gates to receive an actuating impulse when the evaluation of said Boolean expression is unity.

3. A test grading machine comprising the combination: input means for producing binary digits of pulsed input data derived from examiners and examinees selectively marked answer forms; an array of Boolean logic function gates connected to said input means to accept said digital input data, said array being described by the Boolean expression t' s'i t' s'i t' s'i sg si' s)+ s' s where A B, and C are input variables representing the b a y EE Of said digital input data, simultaneously derived from said examiners answer form, and A B and C are input variables representing the binary states of corresponding digital input data, respectively, also simultaneously derived, from said examinees answer form; and readout means, connected to the output of said array of logic function gates to receive an actuating impulse when the evaluation of said Boolean expression is unity.

4. A test grading machine comprising the combination: input means for producing binary digits of pulsed input data derived from examiners and examinees selectively marked answer forms; an array of Boolean logic function gates connected to said input means to accept said digital input data, said array being described by the Boolean expression where A and B, are input variables representing the binary states of said digital input data, simultaneously derived from said examiners answer form, and A and B are input variables representing the binary states of corresponding digital input data, respectively, also simultaneously derived, from said examinees answer form; and readout means, connected to the output of said array of logic function gates to receive an actuating impulse when the evaluation of said Boolean expression is unity.

5. In a machine of the class described, a base member adapted to have superimposed thereon an examiners selectively marked answer form and an examinees selectively marked answer form, said selectively marked answer forms disposed side by side for simultaneous scanning, a housing member attached to and which moves relative to and in sliding cooperation with said base member above said answer forms for scanning purpose, said housing member containing scanning sensors arrayed in scanning cooperation and in sensing cooperation with answer marks on said selectively marked answer forms, a digital logic answer comparing means having inputs connected electrically to said scanning sensors, a solenoiddriven error-marking readout means having its input connected electrically to output of said digital logic answer comparing means, said solenoid-driven error-marking readout means comprising a felt-tipped marking pen positioned to lie in line with said scanning sensors in marking cooperation with said examinces answer form in spaces thereon adapted to receive error-indicating marks, a battery power supply connected jointly to said scanning sensors and to said digital logic answer comparing means and to said solenoid-driven error-marking readout means, a limit switch connected electrically in series in circuit of said battery power supply, said limit switch mechanically disposed in actuating cooperation with stops attached to said base member at limits of sliding travel of said housing member, and including a mechanical interlock comprising an ink pen storage cap attachable to said felttipped marking pen, and a hole in said base member through which said storage cap protrudes in looking cooperation when said limit switch is in the OFF state.

References Cited by the Examiner UNITED STATES PATENTS 2,010,653 8/35 Warren 38-48 2,048,976 7/36 Sveda et al. 35-48 2,052,442 8/36 Black 3548 2,150,256 3/39 Warren 35-48 3,050,248 8/62 Lindquist 35-48 JEROME SCHNALL, Primary Examiner.

GEORGE A. NINAS, 111., LAWRENCE CHARLES,

Examiners.

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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US3284929 *Apr 6, 1966Nov 15, 1966Automata CorpTest grading machine
US3315377 *Jan 28, 1965Apr 25, 1967Rank Organisation LtdTest scoring machine
US3324576 *Jul 18, 1963Jun 13, 1967Acme Visible Records IncTest grading machine
US3408482 *Jul 5, 1962Oct 29, 1968Optical Seanning CorpMachine for sequentially scanning lines, as in test scoring
US3412484 *May 12, 1966Nov 26, 1968Loran S ClarkTest scoring and correcting machine
US3457391 *Jul 19, 1965Jul 22, 1969Mititaka YamamotoVending apparatus for use with credit cards
US3509324 *Mar 14, 1967Apr 28, 1970Acme Visible Records IncTest grading machine
US3527927 *Sep 3, 1965Sep 8, 1970Nederlanden StaatProcess and apparatus for producing and reading arabic numbers on a record sheet
US3601906 *Feb 10, 1969Aug 31, 1971Minnesota Mining & MfgTest grading device
US3648022 *Oct 20, 1969Mar 7, 1972Automatic Voting Machine CorpMethod for tabulating election returns
US3721807 *Oct 20, 1971Mar 20, 1973Miller Scient CorpCard grading machine
US3735505 *May 3, 1971May 29, 1973Instructional Ind IncResponse card and qualitative response analyzer and method
US3737628 *Jun 11, 1971Jun 5, 1973Automatic CorpAutomatically programmed test grading and scoring method and system
US3775594 *Oct 9, 1970Nov 27, 1973Polaroid CorpEncoded identification card system
US3909593 *Apr 1, 1974Sep 30, 1975Addressograph MultigraphApparatus for validating processed documents
US4044229 *Jan 14, 1976Aug 23, 1977Nikolay SamreusDevice for electroconductive connection and reading
Classifications
U.S. Classification434/356
International ClassificationG06K17/00
Cooperative ClassificationG06K17/0032
European ClassificationG06K17/00K