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Publication numberUS3258359 A
Publication typeGrant
Publication dateJun 28, 1966
Filing dateApr 8, 1963
Priority dateApr 8, 1963
Publication numberUS 3258359 A, US 3258359A, US-A-3258359, US3258359 A, US3258359A
InventorsFrances B Hugle
Original AssigneeSiliconix Inc
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor etch and oxidation process
US 3258359 A
Abstract  available in
Previous page
Next page
Claims  available in
Description  (OCR text may contain errors)

June 28, 1966 F. B. HUGLE 3,253,359

SEMICQNDUCTOR ETCH AND OXIDATION BROCESS Filed April 8, 1963 O O 0 O o O O O o O o ,0 in r0 0 O o I NA Q: -ON

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FRANCES B. HUGLE AGENT United States Patent 3,258,359 SEMICONDUCTOR E'ICll AND OXIDATION PROCESS Frances B. llugle, Santa Clara, Calif., assignor to Siliconix Incorporated, Sunnyvale, Calif., a corporation of California Filed Apr. 8, I963, Ser. No. 271,459 (.laims. (Cl. 117-413) My invention relates to the accomplishment of plural processes within a given enclosure and particularly to the processing of a semiconductor as to etching and oxidizing within a single enclosure.

. It is known that contamination is a significant factor in the processes involved'in the manufacture of semiconductor devices for electrical use, such as the wellknown transistor. The purity of the initial semiconductor material far cxcecds tha t in general chemical practice and purposely introduced'impuritie's must in themselves be equally pure. Consequently, even careful handling between one processing department and another'in a plant manufacturing semiconductor devices is not suflicient to eliminate incidental and unpredictable contamination by unwanted substances.

Contamination invariably experienced in handling between the etching and the oxidation processes is known to have unwanted effects upon the electrical characteristics of the completed devices. Although the art has long sought processing steps which would allow these two processes to take place within a given enclosure, a hydrogen furnace for example, this has not been possible.

Single crystal slices of semiconductor material are normally strongly etched as a first step in transistor manufacturing in an acid mixture such as the known CP4 or CP6 mixtures. These mixtures contain various proportions of hydrofluoric acid, HF, nitric acid, HNO and acetic acid, HCO CH This etching is performed prior to the thermal oxidation step, which is the start of the manufacturing process of a planar transistor, for example. Between the etching and the oxidizing steps the slices must be rinsed and dried, which handling gives rise to the possible contamination.

A more recently developed etching procedure employs hydrogen chloride, HCl, gas, usually diluted with hydrogen, H flowing over the heated semiconductor slices at a temperature within the range of from 900 C. to l300 L. for silicon, and several hundred degrees lower for gcrnumium, such as within the range of from 500" (Y. to sun" (1. This procedure gave rise to the hope that when the vapor etching was ctnnpletcd, the gas .l'low could he changed and oxidation effected without removing or in any way disturbing the freshly etched, and therefore clean, wafer slice.

However, oxidation is normally accomplished by employing water vapor, H O, or oxygen, at elevated temperatures; or the two combined at an elevated temperature.

Oxygen is undesirable in a hydrogen furnace for obvious reasons of safety.

-Water vapor combines safely with hydrogen and grows an excellent oxide if hydrogen chloride is not present. It has been found, however, that if even only a trace of hydrogen chloride is present when the water vapor is introduced the semiconductor surface becomes clouded and unusable. The reverse situation is also true; namely,

that if there is residual water vapor present the hydrogen chloride etching will not be satisfactorily accomplished.

Hydrogen chloride and water vapor arethus not compatible within a single system as required for semiconductor processing. Furthermore, water vapor contaminates the system and no amount of purging the same by lit) .' example.

3,258,359 I Patented June 28, 1966 ice means of inert gasesor the equivalent accomplishes compatible operation. Such contamination on the upstream, or inlet side, of such a gas flow furnace is serious. Contamination on the downstream," or outlet side, of such a furnace is not serious, since such contamination cannot reach the work in process.

After repeated attempts to accomplish etching and oxidizing successively in the same system, Idiscovered that if the water vapor is not chemically formed until the components thereof are at the semiconductor material being processed, all contamination problems are eliminatcd I accomplish this requirement by employing a form of the water gas reaction in reverse equilibrium. Instead of steam being one of the components, as it is in producing hydrogen at the known artificial gas works, steam is formed by combining hydrogen and carbon dioxide gases at the surface of the semiconductor, which surface is maintained at a high temperature in the furnace.

An object of my invention is to accomplish two heretofore incompatible processing steps within. one enclosure in semiconductor manufacturing.

Another object is to sequentially accomplish etching and oxidation of semiconductor material within one given enclosure.

Another object is to repeatedly sequentially accomplish etching and oxidation of semiconductor material within one given enclosure upon successive batches of such material.

Another object is to accomplish etching by hydrogen chloride and subsequent oxidation by water vapor Within a single furnace in semiconductor processing.

The single figure illustrates a typical furnace and the auxiliaries employed to accomplish the process.

-In the manufacture of single or multiple semiconductor devices of the nature of transistors, diodes and integrated circuits employing these devices it is necessary to initially form an oxide on the surface of the semiconductor material in order that this can be subsequently etched away in the configuration required to fabricate the device. For the semiconductor silicon, Si, the oxide, SiO is an example.

By the processing detailed below it is possible to etch a semiconductor surface clean and to subsequently form silicon oxide without the need for tedious and impractical precautions, by accomplishing both of these processes within a furnace enclosure. The oxide coating produced is free of pinholes and is of excellent quality for subscqucntly completing the nntnufncttu'e of transistor devices.

The etching process is accomplished within an enclosed gas flow furnace I, of which a glass tube 2 having a diameter of the order of two inches and located within the radio frequency coil 3 of an induction heater is an Provision is made by known glass-working techniques for introducing selected gases and for allowing the'exhaust of the same frotn the working volume. This is accomplished in the figure for nitrogen gas, N through flowmeter 4 and valve (stopcock) 5; for hydrogen gas, H through tlowmeter 6 and valve 7; for hydrogen chloride gas, HCl, through tlowmeter 8 and valve 9; and for carbon dioxide gas, C0 through flownteter l0 and valve 11. A selected sequential gas flow is accomplished by suitable manipulation of the valves, as will be described bclow. The selected gas or combination of gases flows through inlet manifold I2, through furnace 1 and out through exhaust 14 to the roof or other safe dissipation area. The semiconductor wafers I5 to be processed preferably lie on a silicon carbide coated carbon support 16. A ground glass joint 17. or equivalent means, is provided in tube 2 to allow the wafers I5 to be placed into and removed from furnace l.

. P is'con'tinu edi until a 'de'sired'thickne sso ox de reformed '.""-The are offorn'iation is ap- A gas flow of hydrogen of a few liters per minute is 7 established prior to heating the furnace and this flow is continued until the previously given operating temperatures for the semiconductor material being processed is reached. At such time a fiow of a few hundred milliliters is started of hydrogen chloride (milliliters per minute) in addition and this is continued for approximately thirty minutes in order to etch a preferred amount away for semiconductor processing.

At the end of this period the furnace is purged by continuing the hydrogen flow only for a period of five minutes. This five minute period may be reduced somewhat if rapidity in processing is important.

Thereafter, a flow of carbon dioxide, CO is started, of the order of-a few liters per minute. Preferably, this is equal in amount to the flow of hydrogen. The equation for this oxidation agent formation is:

CO H Z CO H 0 lt'is seen that the molal quantities of these reactants are'all unify. Although l prefer to introduce approxim'ately*equal' amounts-of carbon dioxide and hydrogen, thepropo'rtions maybedrastically varied, in which case the oxidation proceeds "prop'e'rly, but morjslowly. During this oxidation 'processirt a material is maintained at a tempera Wilh'lfl' th of from 900 C. to 1350 C.,'fo'r*'silic upon the silicon-f proximately 1000 om units of oxide thickness for 20 minutes of proce ss1ng;""

' In the above equation the equilibrium point shifts from left to right as the temperature'is increased. The high temperatures previously set forth are required for the formation of any water. Thus, there is present only the gases CO and H in the upstream, or inlet, side of my apparatus and only when the hot semiconductor is reached by this combined gas flow does water vapor form. This, of course, is immediately active in forming the oxide coating desired.

While a radio frequency furnace has been specified, this type is not essential. The diffusion furnace known to this art may be employed. For larger furnace sizes for proccssing more semiconductor material at one time the gas flows specified are increased proportionately and vice versa.

This invention has been disclosed by exemplary embodiments thereof. it will be understood that various modifications may be made in these specific embodiments without departing from the scope and spirit of the invention, as is set forth in the following claims.

Having thus fully described my invention and the manner in which it is to be practiced, 1 claim:

semissnducmr 1. In a method of manufacturing semiconductor devices wherein plural processes are successively accomplished in a single furnace the steps of (at) raising silicon semiconductor material to an elevated temperature within the range of from 900 C. to 1,300 C. in an atmosphere of hydrogen gas,

(b) etching said semiconductor material by introduc ing hydrogen chloride gas into said furnace,

(e) flushing said hydrogen chloride gas out of said furnace with hydrogen gas,

(d) introducing a mixture of carbon dioxide and hydrogen gases into said furnace,

(e) maintaining the temperature of said semiconductor material withinthe range of from 1,000 C. to 1,250 C. to accomplish the reaction of said carbon dioxide and hydrogen gases to car-hon monoxide gas and water vapor at the surface of said semiconductor,

(f) continuing the conditions of (e) above until said water vapor oxidizes said semiconductor to a selected depth determined by the temperature and the time interval of processing according to step (e).

2. The method of claim 1 in which the concentration of the hydrogen chloride gas in step (b) is in the range of'from 3% to 10%.

3.-The method of claim 1 in which the gaseous mixtur'e in step (d) is approximately half carbon dioxide and half hydrogen.

4. The method of claim 1 in which the duration of the etching step (b) is of the order of thirty minutes.

5. The method of claim 1 in which the time interval of step (f) to produce an oxide coating on silicon to a depth of 1,000 angstrom units is approximately twenty minutes.

References Cited by the Examiner OTHER REFERENCES A Diffusion Mask for Go, by Jordan. J. of Electro Chemical Society, vol. 108, No. 5, pp. 478 to 481.

Vapor, Plating by Powell et al., 1955, John Wiley and Sons, N.Y., Chap. 7, page 137.

MORRIS SUSSMAN, Irimury Emmi/rm.



Patent Citations
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US2744000 *Feb 19, 1954May 1, 1956Int Standard Electric CorpMethod of cleaning and/or etching semiconducting material, in particular germanium and silicon
US2983631 *Jan 30, 1959May 9, 1961Electronique & Automatisme SaMethod for making diodes and products resulting therefrom
US3168422 *Aug 24, 1960Feb 2, 1965Merck & Co IncProcess of flushing unwanted residue from a vapor deposition system in which silicon is being deposited
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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US3396052 *Jul 14, 1965Aug 6, 1968Bell Telephone Labor IncMethod for coating semiconductor devices with silicon oxide
US3498853 *Jan 7, 1966Mar 3, 1970Siemens AgMethod of forming semiconductor junctions,by etching,masking,and diffusion
US3518115 *Jun 30, 1966Jun 30, 1970Siemens AgMethod of producing homogeneous oxide layers on semiconductor crystals
US3742904 *Jun 3, 1971Jul 3, 1973Motorola IncSteam generator and gas insertion device
US3969164 *Aug 15, 1975Jul 13, 1976Bell Telephone Laboratories, IncorporatedNative oxide technique for preparing clean substrate surfaces
US4010290 *Jun 20, 1973Mar 1, 1977Motorola, Inc.Method of fabricating an ensulated gate field-effect device
US4139658 *Jun 23, 1976Feb 13, 1979Rca Corp.Process for manufacturing a radiation hardened oxide
US4196232 *Dec 18, 1975Apr 1, 1980Rca CorporationMethod of chemically vapor-depositing a low-stress glass layer
US6749687Jan 8, 1999Jun 15, 2004Asm America, Inc.In situ growth of oxide and silicon layers
US7105055May 6, 2004Sep 12, 2006Asm America, Inc.In situ growth of oxide and silicon layers
US7112538 *Nov 12, 2002Sep 26, 2006Asm America, Inc.In situ growth of oxide and silicon layers
US8317921May 6, 2005Nov 27, 2012Asm America, Inc.In situ growth of oxide and silicon layers
US20040206297 *May 6, 2004Oct 21, 2004Armand FerroIn situ growth of oxide and silicon layers
US20050205010 *May 6, 2005Sep 22, 2005Armand FerroIn situ growth of oxide and silicon layers
WO1999035311A1 *Jan 8, 1999Jul 15, 1999Asm America, Inc.In situ growth of oxide and silicon layers
U.S. Classification438/694, 257/E21.218, 65/111, 148/DIG.118, 438/770, 65/32.1, 48/31, 438/906, 65/31, 148/DIG.430, 428/446, 148/DIG.510, 257/E21.285
International ClassificationC30B33/00, H01L21/3065, H01L21/316
Cooperative ClassificationC30B33/00, Y10S148/043, H01L21/31662, Y10S148/051, H01L21/02238, H01L21/02312, Y10S148/118, Y10S438/906, H01L21/02255, H01L21/3065, C30B29/06
European ClassificationH01L21/02K2T2L, C30B33/00, H01L21/02K2E2B2B2, H01L21/02K2E2J, C30B29/06, H01L21/3065, H01L21/316C2B2