Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.


  1. Advanced Patent Search
Publication numberUS3271625 A
Publication typeGrant
Publication dateSep 6, 1966
Filing dateDec 9, 1963
Priority dateAug 1, 1962
Publication numberUS 3271625 A, US 3271625A, US-A-3271625, US3271625 A, US3271625A
InventorsEdward A Caracciolo
Original AssigneeSignetics Corp
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Electronic package assembly
US 3271625 A
Abstract  available in
Previous page
Next page
Claims  available in
Description  (OCR text may contain errors)

p 6, 1966 E. A. CARACCIOLO 3,271,625

ELECTRONIC PACKAGE ASSEMBLY Filed Dec. 9 1963 4 Sheets-Sheet 1 F I g 8 41w se 7 Fig. /2


INVENTOR. Edward A.Caracciolo Attorneys Sept. 6, 1966 E. A. CARACCIOLO ELECTRONIC PACKAGE ASSEMBLY 4 Sheets-Sheet 2 Filed Dec. 9, 1963 INVENTOR, Edward A. Caracciolo BY QZZQ 2 59 Attorneys Sept. 6, 1966 E. A. CARACCIOLO ELECTRONIC PACKAGE ASSEMBLY 4 Sheets-Sheet 5 Filed Dec. 9, 1963 INVENTOR. Edward A. Caracciolo BY 74% egg 5:33

Attorneys P 1966 E. A. CARACCIOLO ELECTRONIC PACKAGE ASSEMBLY 4 Sheets-Sheet 4 Filed Dec. 9, 1963 INVENTOR. Edward A. Caracciolo F 47% Attorneys United States Patent 3,271,625 ELECTRONIC PACKAGE ASSEMBLY Edward A. Caracciolo, Santa Clara, Calif., assignor to Signetics Corporation, Sunnyvale, Calif., a corporation of California Filed Dec. 9, 1963, Ser. No. 329,190 1 Claim. (Cl. 317-101) This application is a continuation-in-part of my earlier filed application Serial No. 213,912, filed August 1, 1962, now abandoned.

This invention relates to an electronic package assembly particularly adapted for semiconductor and miniature electronic devices.

At the present time, attempts are being made to provide packages for semiconductor devices and miniature electronic devices which have high mechanical and thermal shock reliability. One approach has been to take glass in a powder or frit form and forming the same into a type of package utilizing a suitable mold. However, this approach suffers from conventional handicaps of molded wares, that is, d-ifficulty or impossibility of obtaining repetitive dimensional resolution. In addition, there are the problems of cyclic deterioration of the mold, mold release, and mold replacement costs. This technique or approach also encounters difiiculties because in this process, a great number of particles are fused or sintered together to form the article with the inherent problems of interstitial gases, voids and impurities which seriously affect the quality of the article. There is, therefore, a need for a new and improved package for semiconductor and electronic devices and a method of manufacture for the same as well as an improved electronic assembly.

In general, it is an object of the present invention to provide an electronic assembly, package and method of manufacture which overcomes the above named disadvantages.

Another object of the invention is to provide an electronic assembly which is hermetically sealed and which has high mechanical and thermal shock reliability.

Another object of the invention is to provide a package of the above character which has great mechanical strength.

Another object of the invention is to provide a package of the above character in which a chemically inert material is utilized as a dielectric.

Another object of the invention is to provide a package which is homogeneous.

Another object of the invention is to provide a method of manufacture which utilizes chemical action rather than mechanical action for making the package.

Another object of the invention is to provide a method of the above character which can be readily and economically performed.

Another object of the invention is to provide a method of the above character in which multiple packages can be formed at the same time.

Additional objects and features of the invention will appear from the following description in which the preferred embodiments are set forth in detail in conjunction with the accompanying drawings.

Referring to the drawings:

FIGURE 1 is a chart showing my method for the manufacture of my package.

FIGURE 2 is an isometric view of the base portion of a package incorporating my invention,

FIGURE 3 is an isometric view showing an electrode structure disposed between two thin sheets of a dielectric material.

FIGURE 4 is an isometric view showing the assembly after the sheets have been bonded together with heat and pressure to provide a sandwich.

FIGURE 5 is an isometric view similar to FIGURE 4 showing recesses etched into the dielectric material to expose the internal electrode structure.

FIGURE 6 is an isometric View of the assembly shown in FIGURE 5 showing certain portions of the exposed electrodes etched away.

FIGURE 7 is an isometric view showing how the electrode structure and the dielectric sheets cut apart in blocks to provide separate packages.

FIGURE 8 is a side elevational view in cross-section of a semiconductor assembly incorporating my invention.

FIGURE 9 is a side elevational view in cross-section of another semiconductor assembly incorporating my invention.

FIGURE 10 is a plan view of another embodiment of my package with a centrally disposed pad.

FIGURE 11 is a plan view showing the electrode structure is masked to provide the pad.

FIGURE 12 is a plan view of the semiconductor assembly shown in FIGURE 8.

FIGURE 13 is a plan view of another embodiment of a semiconductor assembly incorporating my invention.

FIGURE 14 is an isometric view showing a sheet of conducting material ready to be bonded to a sheet of dielectric material.

FIGURE 15 is an exploded isometric view of a plurality of sheets of material ready to be bonded together into a unitary structure.

FIGURE 16A is an isometric view of a portion of the assembly shown in FIGURE 15 bonded together.

FIGURE 16B is an isometric view showing a portion of the dielectric material etched away to expose the leads.

FIGURE is an isometric view showing certain portions of the leads etched away.

The method or process for making the package which is shown in FIGURE 2 is shown in FIGURES 3-7 and is set forth in the chart shown in FIGURE 1. As shown in FIGURE 1, an electrode structure 11 is first formed as indicated by step 12. The electrode structure can be formed in any suitable manner and of any suitable conducting material. However, for reasons hereinafter explained, material having certain thermal expansion characteristics or coefiicient of expansion such as Kovar is utilized. A sheet of Kovar or other suitable metal is punched as shown in FIGURE 3 to provide a plurality of later-ally extending spaced parallel strips 13 which are maintained in a predetermined spaced relationship by a remaining outer portion 14 of the sheet which extends around the entire perimeter of the electrode structure. Since the sheet shown in FIGURE 3 had a rectangular configuration, the outer remaining portion 14 also has a rectangular configuration. The invention may be practiced by forming only one group of strips at a time. However, in order to facilitate production and to make possible the production of a number of packages at the same time, the strips 13 are arranged in groups of six strips each with the spacing between each group being substantially greater than the spacing between the individual strips of the group.

After the electrode structure 11 has been punched, it is thoroughly cleaned in a suitable manner. For example, it can be immersed in a bath of acetic acid, nitric acid and hydrochloric acid with the following proportions:

Milliliters Acetic acid 750 Nitric acid 250 Hydrochloric acid 15 The electrode structure is retained in this bath for a suitable period of time such as 20 seconds with the bath having a room temperature or temperature of approxi- 3 inately 70 F. After the bath, the electrode structure is thoroughly rinsed in a suitable manner such as by use of an ultrasonic bath utilizing first tap water, then deionized Water and then acetonein that order. The electrode structure is then passed through a stream of burning hydrogen gas and heated to a low redness for a period of approximately 5 seconds.

After preparation of the electrode structure 11 has been completed, the electrode structure is embedded in an insulating or dielectric material as shown in step 16 in FIGURE 1. As shown in FIGURES 3 and 4, this can be accomplished by placing the electrode structure 11 between a pair of rectangular sheets 17 of a suitable insulating or dielectric material such as #7052 glass (Corning Code) in such a manner that a sandwich is formed with the electrode structure 11 being disposed between the two sheets 17. The sheets 17 can have any desired thickness such as, for example, .040 inch. The sheets 17 also can be of any desired dimensions. However, =as shown in FIGURES 3 and 4, the sheets should have a width which is substantially less than the length of the strips 13 provided in the electrode structure 11 so that the strips will extend beyond the side edges of the sheets.

The entire sandwich assembly is then fired in a suitable manner to form the same into a unitary assembly such as by placing the sandwich in a furnace and maintaining the furnace at a temperature of approximately 1650 F. for a period of approximately 7 minutes. The assembly 19 is then removed and annealed in a suitable manner such as for a period of 5 minutes at 950 F., after which it is cooled to room temperature. As can be seen from FIGURE 4, the two glass sheets 17 have been bonded together to provide a single glass sheet 20 with the electrode structure 11 embedded within the same.

After this has been completed, recesses 21 of a suitable configuration, such as the rectangular recesses shown in FIGURE 5, are formed in the insulating material as indicated by step 22 in FIGURE 1. These recesses are formed in a suitable manner such as by masking the upper surface of the sheet of insulating or dielectric material 20 with an etch-resistant material. The mask is so formed on the upper surface of the sheet of insulating material so that regions of the upper surface of the sheet 20 are exposed which generally overlie the groups of metal strips 13 embedded in the sheet 20.

A suitable etchant such as full strength hydrofluoric acid is then applied to the upper surface of the sheet 20 which selectively attacks the glass but does not attack the electrodes structure 11. If desired, instead of just masking the upper surface of the sheet of insulating material 20, all the surfaces of the dielectric material 20 can be masked in a suitable manner so that the entire assembly may be placed in an etching bath. When this is done, the etchant can be utilized for peripheral shaping of the sheet 20.

With my invention, it is only desirable to etch the recesses 21 to a depth so that the strips 13 will be exposed within the recess. I have found that this is relatively easy to accomplish by taking advantage of the electro-conductivity of the hydrofluoric acid which is used for the etchant. By connecting an electrical circuit from the etchant to the electrode structure 11, it is possible to ascertain when the etchant has first etched away sufficient glass to come in contact with the strips 13 to establish an electrical contact. As soon as this initial circuit has been established, a time delay device is used in the circuitry so that the etching will continue for a sufficient-period of time to expose all of the strips 13 and to take into account any small variances in depth of the strips 13 within the sheet 20. The electrical apparatus is then utilized to arrest any further etching action. Thus, a suitable buffer such as ammonium bifluoride can be added to the hydrofluoric acid to inhibit any further reaction. Thereafter, the circuitry can actuate a mechanism to transfer the entire assembly 19 into a rinsing bath.

After the assembly or assemblies have been thoroughly washed, a mask is applied over the portions of the strips 13 within the recesses 21 to expose a centrally disposed rectangular area overlying the strips. A suitable etchant such as Kovar etch is then placed within the recesses to selectively attack the Kovar but which does not attack the glass to remove the central portion of each of the strips to form leads 24 as indicated by step 26. After the etching has been completed, the assembly is again rinsed and dried. Thereafter, the portions 14 are cut away as .shown in FIGURE 7 to separate the other ends of the leads 24-. The assembly 1? is then cut apart as also shown in FIGURE 7 to provide rectangular blocks 27 of insulating or dielectric material with centrally disposed recesses 21 with two sets of leads 24. This com pletes the manufacture of the base 31 of the package incorporating my invention.

As can'be seen from FIGURE 2, this base 31 consists of the body 27 of insulating or dielectric material of a suitable configuration such as the rectangular configuration shown in FIGURE 2. This body is formed with a centrally disposed recess 21 which also has a suitable configuration such as the rectangular configuration shown in FIGURE 2. The recess is formed so that there is a relatively large planar bottom Wall 28. The leads 24 are mounted in opposite side walls of the body and are permanently bonded therein. Portions of each of the leads 24 are disposed within the recess and are bonded in the bottom wall but have their upper surfaces exposed within the recess. In the arrangement shown, the leads are rectangular in cross-section and are arranged so that they all lie in the same horizontal plane. The leads on each side are also spaced so that they are parallel to each other. The leads have been formed of Kovar and Corning 7052 glass has been used so that the glass and the leads have substantially the same coeflicient of ex- 7 pansion.

In utilizing the base 31 to form a package, a cover 32 of a suitable insulating or dielectric material and preferably the same insulating material which is utilized for the base is mounted on top of the base 31 as shown in FIGURE 8. The edge areas between the base 31 and the cover 32 are then subjected to heat and pressure to permanently bond the cover 32 to the base 311. If desired, this sealing operation can taken place within a vacuum chamber or within a chamber containing an inert atmosphere. At the same time that the heat and pressure are being applied to the side edges, means may be attached to the leads 24 to drain off any excess heat to thereby prevent damage to the electronic device 36 being encapsulated within the package.

If desired, the bases 31 can be stacked one above the other as also shown in FIGURE 8 and bonded together in a similar manner with the base of the unit above serving as a cover for the base below.

As is readily apparent to those skilled in the art, my package is such that it can be utilized for encapsulating miniature electronic devices and particularly semiconductor devices. Thus, as is preferable in the mounting of semiconductor devices, a metal pad 37 is mounted on the bottom wall 28 and is centrally disposed between the inner ends of the leads 24. This pad 37 may be placed in the base 31 after the leads have been formed in the manner hereinbefore described. However, alternatively, it can be formed with the leads by stamping an electrode structure 38 of the type shown in FIGURE 11 and then utilizing a suit-able mask 39 and etchant to selectively remove the undersired metal from with-in the recess to provide a centrally disposed metal pad 37 which is securely bonded to the bottom wall 28 of the insulating body 27.

The semiconductor device 36 mounted on the base 31 can be of any suitable type, as for example, it can be an integrated circuit such as a NAND gate. Connections between the circuitry of the device 36 and the inner ends of the leads 24 can be accomplished in any suitable manner such as by the use of gold wire which is bonded to the device 36 and to the leads 24 by suitable means such as thermocompresision bonding as described in United States Patent No. 3,006,067 and as shown in FIG- URES 8 and 12.

Alternatively, the pad37 can be omitted and the semiconductor device can be inverted as shown in FIGURE 9. When the semiconductor device is inverted, the leads 24and the portions of the electronic device to which connections are to bemade are arranged so that they will overlie each other. Bonds can be formed between the leads 24 and the desired areas of the semiconductor device 36 by utilization of beads of a suitable material such as gold and then utilizing pressure and temperature to again form the thermocompression bonds between the leads 24 and the gold balls 42 and between the gold balls and the semiconductor device. In order to enhance the formation of good bonds, it may be desirable to first bathe the leads 24 in an electroless gold bath. In FIG- URE 13, I have shown a different arrangement of electrodes or leads 24 in which the semiconductor device is bonded to the leads 24 in much the same way as shown in FIGURE 9.

It is apparent from the foregoing that I have provided a new and improved electronic assembly, package and method of manufacture for the package and the assembly. The leads are sealed in the insulating material which makes the leads easier to handle and also makes the entire package vibration resistant. The package is also constructed in such away that the semiconductor devices or miniature electronic devices can be readily mounted within the same. The packages are also formed so that they can be readily stacked one above the other to thereby obtain a very high packing density.

If desired, the cover 32 can be eliminated and after the electrical connections between the semiconductor device and the leads 24 have been made, the recess 21 can be filled with a potting compound to provide a hermetically sealed device which is also vibration and shock resistant.

In describing the fabrication of the embodiment shown in FIGURES 2-7, I have disclosed that the recesses formed in the dielectric material can be formed in a suitable manner such as by masking the upper surface of the sheet of dielectric material with an etch-resistant material. Such etch-resistan-t material can be in the form of a tape consisting of a strip of Mylar coated on one side with a solvent-resistant adhesive. Such a tape is perforated to provide areas which correspond to the areas which it is desired be recessed. With the use of such tape, it is necessary that graphite or similar high temperature release material be utilized in the furnace during processing of the assembly. Such high temperature release materials are relatively expensive and tend to erode away during the repeated cycling of the furnace.

It is for this reason I have disclosed in FIGURES 14, 15, 16, 16A, 16B and 16C, an electronic assembly, package :and method of manufacture which does not require the use of a mask of this type which must be removed. Thus, as shown in FIGURE 14, in place of a removable mask, I have provided a strip 46 of suitable conducting material such as Kovar which is pro-punched With an array of holes 47 which correspond to the areas which must be etched out to provide access to the leads as hereinafter described. After the strip 46 has been prepared, one side of the strip 46 is then coated with a suitable dielectric material such as No. 7052 glass (Corning Code). This can be accomplished in any number of ways. For example, as shown in FIGURE 14, a sheet 48 of this dielectric material of the same general dimensions as the strip 46 can be provided. This assembly can then be fired in a suitable manner so that the Kovar strip is firmly bonded to the glass sheet 48. This firing can be accomplished in the manner hereinbefore described. Thereafter, the completer assembly 49 can be annealed in a suitable manner as hereinbefore described.

The Kovar strip 46 can also be provided with a covering of dielectric material on one side by covering one side with a suitable masking material and then dipping the strip into a slurry of powdered glass (No. 7052 glass or any other glass having similar physical characteristics in an aqueous suspension). If desired, two strips 46 can be dipped at the same time by utilizing double-faced adhesive tape and bonding two of the strips back to back. After the strips have been dipped in the slurry, they can be separated and fired and annealed in a manner hereinbefore described. Alternatively, both sides can be covered with the slurry and fired, after which the dielectric covering on one side of the sheet 46 can be etched away.

In FIGURE 15, another assembly 50 similar to assembly 49 is provided which consists of a strip 51 of conducting material such as Kovar which is bonded to a plate 52 of dielectric material such as No. 7052 glass (Corning). However, in this case, the conducting material 51 is not provided with apertures such as the strip 46. An electrode structure 53 substantially identical to the electrode structure 11 hereinbefore described is disposed between the assemblies 50 and 49. The assemblies 50 and 49 with the electrode structure 53 are then fired in a suitable manner and annealed as hereinbefore described to provide a unitary assembly.

A portion of the completed assembly 53 is shown in FIGURE 16A. Thereafter, a suitable etchant is applied to the upper surface of the sheet 48 as exposed by the openings 47 in the strip 46. As hereinbefore described, the etching operation is continued until the strips 56 lying in a plane are exposed within the opening 47 as shown in FIGURE 16B.

As hereinbefore described, a mask is then applied over portions of the strips 13 within the recess 57. Thereafter, a suitable etchant such as Kovar etch is placed in the recesses 57 to selectively attack the Kovar to remove the central portion of each of the strips to form separate leads in the manner hereinbefore described. The outer portions of the electrode structure 53 can then be removed as also hereinbefore described to provide base portions for a package which can be utilized as also here inbefore described.

The primary difference between the base formed by the method shown in FIGURES 14-16 and the method shown in FIGURES 2-7 is that the bases formed by the method shown in FIGURES 1416 are provided with a metal top and a metal back which serves as a conducting material. If neither of these is desired, they can be easily stripped away. The use of the metal strips 46 with the perforations is advantageous in performing the etching operation for forming the recesses 57 as hereinbefore described, but in addition they have the further advantage in that these strips of Kovar material serve as a release material built into the package itself. No graphite or similar furnace release material is required to remove it from the molt upon removal from the furnace. There is a further advantage in that the entire assembly can be processed more rapidly because as it comes from the furnace, it can be dropped directly into the etchant which removes the glass exposed by the openings 47.

In many practical applications, the metal conducting tops and backs have advantages. For example, the metal top can be used as a common connector for a number of leads, or it can serve as a ground. Similarly, the metal back can be used as a heat sink for the package. The metal back may also make it easier to affix the package to the assembly of which it is to form a part as, for example, the metal back can be directly soldered to a chassis or framework containing other electronic components. Where photosensitive devices are utilized, the

metal back may also be advantageous because it is opaque.

I claim:

In an electronic package assembly adapted to receive a semiconductor device having contact areas, a body, a plurality of conducting metallic leads having inner and outer end portions, the inner end portions of the leads being embedded in the body and having exposed upper surfaces, the outer end portions of the leads extending outwardly away from the body and being free of the body, portions of the leads intermediate the inner and outer end portions being surrounded on all sides by the body, at least the portion of the body in contact With and surrounding the leads being formed of a material having a coefficient of expansion which is substantially identical to that of the leads and serving to electrically insulate the leads from each other, all portions of said leads in said body being in physical contact with and supported by said body, the exposed upper surfaces of the inner portions of the leads lying in a substantially common plane and being disposed in a predetermined pattern adjacent the perimeter of the body, a substantially planar metal conducting pad mounted on the body in a generally central position and being out of contact with at least certain of the exposed upper surfaces of the inner end portions of the leads, said body being adapted to receive the semiconductor device so that the semiconductor device can be mounted directly upon the pad and so that the contact areas of the semiconductor device can be connected to the upper exposed surfaces of the inner portions of the leads, cover means mounted on said body and means forming a hermetic seal between the cover means and the body so that a semiconductor device mounted in the body is hermetically sealed therein, said body having a substantially planar outer surface and said cover means having a substantially planar outer surface parallel to the outer surface of the body to permit one package to be stacked with another package with surfaces in juxtaposition.

References Cited by the Examiner UNITED STATES PATENTS FOREIGN PATENTS 19,919 11/1893 Great Britain.

References Cited by the Applicant UNITED STATES PATENTS 2,875,387 2/ 1959 Randels. 2,905,744 9/ 1959 Rayburn. 3,072,832 1/1963 Kilby. 3,006,067 10/1961 Anderson et al.

FOREIGN PATENTS 19,919 11/ 1893 Great Britain.

ROBERT K. SCHAEFER, Primary Examiner.



Assistant Examiners.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US2875387 *Apr 8, 1954Feb 24, 1959Corning Glass WorksElectrical condensers
US2905744 *Dec 27, 1956Sep 22, 1959Acf Ind IncModule wafer support for electrical components
US2934814 *Jun 4, 1954May 3, 1960Bert GreeneMethod of making an electronic components package
US2994121 *Nov 21, 1958Aug 1, 1961Shockley WilliamMethod of making a semiconductive switching array
US3006067 *Oct 31, 1956Oct 31, 1961Bell Telephone Labor IncThermo-compression bonding of metal to semiconductors, and the like
US3029368 *Nov 25, 1959Apr 10, 1962Vector Mfg CompanyModular circuit assembly
US3029495 *Apr 6, 1959Apr 17, 1962Doctor Norman JElectrical interconnection of miniaturized modules
US3040213 *Nov 15, 1956Jun 19, 1962Corning Glass WorksComposite glaceramic articles and method of making
US3072832 *May 6, 1959Jan 8, 1963Texas Instruments IncSemiconductor structure fabrication
US3081525 *Sep 3, 1959Mar 19, 1963Gen Am TransportMethods of making printed electric circuits
US3118016 *Aug 14, 1961Jan 14, 1964Texas Instruments IncConductor laminate packaging of solid-state circuits
US3179854 *Apr 24, 1961Apr 20, 1965Rca CorpModular structures and methods of making them
US3184831 *Nov 7, 1961May 25, 1965Siemens AgMethod of producing an electric contact with a semiconductor device
GB189319919A * Title not available
GB189419919A * Title not available
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US3324357 *Dec 28, 1964Jun 6, 1967Int Standard Electric CorpMulti-terminal semiconductor device having active element directly mounted on terminal leads
US3340602 *Feb 1, 1965Sep 12, 1967Philco Ford CorpProcess for sealing
US3341649 *Aug 19, 1966Sep 12, 1967Signetics CorpModular package for semiconductor devices
US3370203 *Jul 19, 1965Feb 20, 1968United Aircraft CorpIntegrated circuit modules
US3373481 *Jun 22, 1965Mar 19, 1968Sperry Rand CorpMethod of electrically interconnecting conductors
US3374537 *Mar 22, 1965Mar 26, 1968Philco Ford CorpMethod of connecting leads to a semiconductive device
US3382342 *Sep 3, 1964May 7, 1968Gti CorpMicromodular package and method of sealing same
US3383454 *Jan 10, 1964May 14, 1968Gti CorpMicromodular package
US3388302 *Dec 30, 1966Jun 11, 1968Coors Porcelain CoCeramic housing for semiconductor components
US3391451 *Mar 22, 1965Jul 9, 1968Sperry Rand CorpMethod for preparing electronic circuit units
US3403438 *Dec 2, 1964Oct 1, 1968Corning Glass WorksProcess for joining transistor chip to printed circuit
US3404319 *Aug 18, 1965Oct 1, 1968Nippon Electric CoSemiconductor device
US3414968 *Feb 23, 1965Dec 10, 1968Solitron DevicesMethod of assembly of power transistors
US3418422 *Feb 28, 1966Dec 24, 1968Texas Instruments IncAttachment of integrated circuit leads to printed circuit boards
US3428866 *Dec 12, 1966Feb 18, 1969IbmSolid state device including electrical packaging arrangement with improved electrical connections
US3436604 *Apr 25, 1966Apr 1, 1969Texas Instruments IncComplex integrated circuit array and method for fabricating same
US3436606 *Apr 3, 1967Apr 1, 1969Texas Instruments IncPackaged multilead semiconductor device with improved jumper connection
US3436810 *Jul 17, 1967Apr 8, 1969Jade CorpMethod of packaging integrated circuits
US3439238 *Dec 16, 1963Apr 15, 1969Texas Instruments IncSemiconductor devices and process for embedding same in plastic
US3444440 *Nov 27, 1964May 13, 1969Motorola IncMultiple lead semiconductor device with plastic encapsulation supporting such leads and associated elements
US3469953 *Dec 7, 1968Sep 30, 1969Advalloy IncLead frame assembly for semiconductor devices
US3483966 *Jun 14, 1967Dec 16, 1969Sprague Electric CoComponent mounting assembly and method
US3491435 *May 25, 1966Jan 27, 1970Int Standard Electric CorpProcess for manufacturing headerless encapsulated semiconductor devices
US3494023 *Apr 21, 1966Feb 10, 1970Siemens AgMethod of producing semiconductor integrated circuits
US3509434 *Apr 27, 1967Apr 28, 1970Nippon Electric CoPackaged semiconductor devices
US3524249 *Oct 5, 1967Aug 18, 1970Nippon Electric CoMethod of manufacturing a semiconductor container
US3538597 *Jul 13, 1967Nov 10, 1970Us NavyFlatpack lid and method
US3569798 *May 13, 1969Mar 9, 1971Rca CorpDouble heat sink semiconductor device
US3597839 *Mar 10, 1969Aug 10, 1971Bell Telephone Labor IncCircuit interconnection method for microelectronic circuitry
US3693239 *Jul 25, 1969Sep 26, 1972Sidney DixA method of making a micromodular package
US3698073 *Oct 13, 1970Oct 17, 1972Motorola IncContact bonding and packaging of integrated circuits
US3745648 *Mar 18, 1970Jul 17, 1973Siemens AgMethod for mounting semiconductor components
US3777365 *Mar 6, 1972Dec 11, 1973Honeywell Inf SystemsCircuit chips having beam leads attached by film strip process
US3791025 *Apr 6, 1972Feb 12, 1974Teledyne IncMethod of manufacturing an electronic assembly
US3795043 *Nov 2, 1971Mar 5, 1974Honeywell Inf Systems ItaliaMethod for obtaining beam lead connections for integrated circuits
US3811187 *Jun 22, 1972May 21, 1974Siemens AgMethod for mass production of housings for semiconductor devices provided with required connecting terminals
US3823467 *Jul 7, 1972Jul 16, 1974Westinghouse Electric CorpSolid-state circuit module
US3864820 *Dec 14, 1972Feb 11, 1975Gte Sylvania IncFabrication Packages Suitable for Integrated Circuits
US3872331 *Jun 4, 1973Mar 18, 1975Zenith Radio CorpPackaged surface wave selective circuit device and method of making the same
US3934073 *Sep 5, 1973Jan 20, 1976F ArdezzoneMiniature circuit connection and packaging techniques
US4204317 *Nov 18, 1977May 27, 1980The Arnold Engineering CompanyMethod of making a lead frame
US4355463 *Mar 24, 1980Oct 26, 1982National Semiconductor CorporationProcess for hermetically encapsulating semiconductor devices
US4375008 *Apr 28, 1980Feb 22, 1983Siemens AktiengesellschaftMethod for encapsulating components with cases and an encapsulation provided by the method
US4639826 *May 24, 1984Jan 27, 1987Compagnie D'informatique Militaire, Spatiale Et AeronautiqueProtection against ionizing radiation
US4801765 *Jan 6, 1986Jan 31, 1989American Telephone And Telegraph Company, At&T Bell LaboratoriesElectronic component package using multi-level lead frames
US4814947 *Feb 17, 1988Mar 21, 1989North American Philips CorporationSurface mounted electronic device with selectively solderable leads
US4936792 *May 1, 1989Jun 26, 1990Amp IncorporatedFlexible printed cable connector
US5501003 *Dec 15, 1993Mar 26, 1996Bel Fuse Inc.Method of assembling electronic packages for surface mount applications
US5633620 *Dec 27, 1995May 27, 1997Microelectronic Modules CorporationArc containment system for lightning surge resistor networks
US7396265 *Sep 30, 2003Jul 8, 2008Cochlear LimitedFeedthrough for electrical connectors
US7950134Dec 8, 2004May 31, 2011Cochlear LimitedImplantable antenna
US7988507 *Feb 4, 2008Aug 2, 2011Cochlear LimitedFeedthrough for electrical connectors
US7996982Feb 4, 2008Aug 16, 2011Cochlear LimitedMethod of making feedthroughs for electrical connectors
US8124173 *Dec 8, 2008Feb 28, 2012Ube Industries, Ltd.Process for packaging electronic devices
US8672667Jul 15, 2008Mar 18, 2014Cochlear LimitedElectrically insulative structure having holes for feedthroughs
US8698006Jun 4, 2010Apr 15, 2014Morgan Advanced Ceramics, Inc.Co-fired metal and ceramic composite feedthrough assemblies for use at least in implantable medical devices and methods for making the same
US8819919May 27, 2011Sep 2, 2014Cochlear LimitedMethod of forming a non-linear path of an electrically conducting wire
DE1909480A1 *Feb 26, 1969Jan 15, 1970Gen ElectricHalbleiterbauelement und Verfahren zu seiner Herstellung
DE2902502A1 *Jan 23, 1979Jul 26, 1979Plessey Handel Investment AgFilteranordnung fuer akustische oberflaechenwellen
WO2011066477A1 *Nov 26, 2010Jun 3, 2011National Ict Australia Limited (Nicta)Methods for forming feedthroughs for hermetically sealed housings using powder injection molding
U.S. Classification361/735, 29/827, 257/E23.189, 257/701, 257/E23.43, 174/50.5, 361/779, 174/551, 257/678, 257/690, 174/548
International ClassificationH01L23/057, H01L23/495
Cooperative ClassificationH01L2924/01019, H01L23/057, H01L24/48, H01L2924/16195, H01L23/49541, H01L2224/48247, H01L2224/48091
European ClassificationH01L23/495G, H01L23/057