US 3300066 A
Description (OCR text may contain errors)
Jan. 24, 1967 s. HENIG ETAL SORTING MACHINE PROVIDING SELF-OPTIMIZING INVENTORY REDUCTION 14 Sheds-Sheet l Filed June 2l, 1963 INVENTORS ATTORNEY Jan. 24, 1967 s. HENIG ETAL SORTNG MACHINE PROVIDING SELF-OPTMIZING INVENTORY REDUCTION 14 Sheets-Sheet Filed June 2l, 1963 .VJ mim n a @la HP WC O mm evdw 5E By QQJQMM ATTORNEY Jan. 24, 1967 s. HENIG ETAL 3,300,066
SORTING MACHINE? PROVIDING SELF-OPTIMIZING INVENTORY REDUCTION Filed June 2l, 1965 14 Sheets-Sheet 15 lOUTPUT 0F LETTEQ- HANDLING MECHAN/SM 25 WQTVM VQQIIIQO mi ATTORNEY Jan. 24, 1967 s. HENIG ETAL SORTING MACHINE PROVIDING SELFQOPTIMIZING INVENTORY REDUCTION 1,4 Sheets-Sheet 4 Filed June 2l, 1965 ATTORNEY Jan. 24, 1967 s. HENIG ETAL SORTING MACHINE PROVIDING SELF-OPTIMIZING INVENTORY REDUCTION 14 Sheets-Sheet 5 Filed June 2l, 1963 TRA CK TRA CK R mwo DHU w, WD O MW Bm BA P MW www5 m m n n m miv 6 6 6 6 M w: L TE LOMB," 70- SU N x D VE .I .2 .5 ESER HAR n CHAR CHAR Dn O rL 4 n.6 2 Jllvl C C C C 4 a. 4 a. 25456l o 6 f v M O C 0 C Mu/co 6 6 6 N XC INVENTORS eymour Herzig ATTORNEY Jan. 24, 1967 s. HENIG ETAI. 3,300,066
SORTING MACHINE PROVIDING SELFTOPTIMIZING INVENTORY REDUCTION Filed June 2l, 1963 14 Sheets-Sheet 6 SLOT NUMBER CATEGORY COUNT BIT AcTII/E UNLOAD TRAC/ 5 STORE TRACKS STORE TRA@ CATEGORIES f STORE TRA@ OTITRACKS IS TRAC/S M LEAD SIT 4r-X m T x 1 E3B/TS CHA/#5 2O ITSW- OBITS CHAR.#2 *cHARf/ CHA/#2 CHAR. "il "MM wwf- ETRAZ TRACKS 6 TRAC/ 5 E BITS CHAR. #I II QI II I Q II III I I LL-XW'L TRAIT- BIT I I I I I I I I I I I I I I 1 X DIRECTION /l OF ROTATION INvI-:NTORS F 45 56ymOuI^-^Henz`g EPI/I? C Palas/91 ATTORNEY Jan. 24, 1967 s. HENIG ETAI. 3,300,066
SORTING MACHINE PROVIDING SELF-OPTIMIZING INVENTORY REDUCTION Filed June 2l, 1965 14 Sheets-Sheet 7 PLACE CLOCK TALLY SCHEME LIST THRESHOLD MARK TRAC/e `STORE CATECoR/Es STORE STORE E00 CECTORJ, TRA CK TRA CKs TRA CK TRAC/4, ,f f w x P l 3 BITS ARE l2 Bl T5 T ONE "200" A SECTOR sans LL \D/RECTT0N of;
RoTAT/o/v LoAD/A/e BUTTER #a LETTER STORE TRACR sLoT cATEGoRy NUMBER STRE WAC/(5 ACT/VE UNLOAD TRAC/ 5 CATEGORIES CLOCK TRACK I, STGR TRACK 40 SECTORS EM m ,ff-f E A T Y /YN A 0 A P \l/|1\|/|||r||xr|\|/|||l|||||l|| 2x\ D/RECT/OA/ 0F RoTAT/o/v INVENTORS Seymour Herzig Ervin C Palas/g mi M;
ATTORNEY Jan.f24, 1967 S. HENIG ETAL Filed June 2l, 1963 CA TEGORY CODE SLOT NUMBER 14 Sheets-Sheet a TRANSFER D12-Uw /4/ CODE SIGNAL 2/ fmg ,-40 w w 2 PA/QALLEL Q Y f 57 n l /292 `SER/A1. KEYBOARD @55g 1 fou/WER J l I V v .l L /54 M l DEL/w :X DEV/CE [Vc I 5c @mame/Q l 2,5 1 if F 505 L62 T0 HTH? l l HANDLING 5' Cown/emma r MecHAN/SM 25 /N F/e. l 50 I l I v TVP/CAL c/Qcums FOR fi EACH STAT/0N l To 2o D -YC "L6 iw-JC "2'5 Eg T t INVENTORS :1R ruw/N6 leN/JL S H Y CN'QA ms /N F/G. 5 yl/powa @mg EPI/m CPa/as/y BY Y ATTORNEY Jan. 24, 1967 s. HENIG ETAL SORTING MACHINE PROVIDING SELFOPTIMIZING INVENTORY REDUCTION 14 Sheets-Sheet 1 O Filed June 2l, 1963 QMJ ATTORNEY QW @Px www.
Jan. 24, 1967 s. HENIG ETAL 3,300,066
SORTING MACHINE PROVIDING SELF-OPTIMIZING INVENTORY REDUCTION 14 Sheets-Sheet 1'1.
Filed June 2l Jan. 24, 1967 A s. HENIG r-:TAL 3,300,066
SORTING MACHINE PROVIDING SELF-OPTIMIZING INVENTORY REDUCTION 14 Sheets-Sheet 12 Filed June 2l, 1963 THRES HOLD PLACE MARK TA L LV STORE RET/MRR STORE RET/MER TRAcR TRACK TRACK TRACK @55 ADT/ANCE /25115 FZ- 365 I 569 9' L READ WRITE J READ N 430 290 AMPL. AMPL. AMRL.
570 READ j wRnT READ WRITE AMPL. AMPL. AMPL. AMPL.
M565 1564 485i F 0 571 M Azzw 425 -I COMPARATOR 574# 63 4// 4Llg] M* ICOMPARATOR FLM 3&38
4 Il ifo-BIT REQ. I l 59T 5456 2To l F F H69 coMPA- f 0 RAToR g 559 92 R 5 OF END oF lA H4 Re J TNVENTORS LSeymour1 -Henz'g ERT/n CPalas/y ATTORNEY Jan. 24, 1967 s. HEN'IG ETAL 3,300,065
SORTING MACHINE PROVIDING SELF'OPTMIZING INVENTORY REDUCTION Filed June 2l, 1965 14 Sheets-Sheet 13 SCHEME LIST CATEGORY TALLY CHAR. #L or CHARS. STORE COMMAND #E A #5 TRA CR if@ TRACK TRACK E WRITE AMPL. N 284 265 l ze: 26a
--DRUM5L w READ @-893 265 READ 2671 READ AMPI-v AMPL. v MPL.
A COMPA RATOR B coMPARAoR COMPARATOR CLEAR fd a C-BLT COMMAND 390 l R REESOURCE \455 200K R-L }L, FROM TIM/NG SIGNAL GNERATORS IN F INVENTORS fymou/n Henzg FCLQI ffl/n C Palas/j Jan. 24, 1967 S. HENIG ETAL.
1,4 Sheets5heet 14 Filed June 2l, 1965 ww www Q Y l i n :SI Il m WWW www .Nw www` ||1 illl www ATTORNEY nited States Patent iitice 3,300,066 SORTING MACHINE PROVIDING SELF-@PTI- MIZING INVENTRY REDUCTIN Seymour Heng, Kensington, and Ervin C. Palaslty, Silver Spring, Md., assignors to the United States of America as represented by the Secretary of Commerce Filed June 21, 1963, Ser. No. 289,761 24 Claims. (Cl. 214-11) This invention relates to a sorting machine in which physically similar Karticles are deposited randomly into individual storage slots emplaced in a r-ack. Each articles category information along with its storage location is tiled in the machines memory. In order to`sort, the memory is searched periodically for articles of like category which are then unloaded to a common conveyor belt. The belt is used for different categories during successive periods and emptied slots are immediately available for reuse by new articles of any category. The invention described herein is further characterized by the provision of self-optimizing inventory Ireduction of articles from the slots.
A machine, constructed in accordance with this invention, is particularly suitable to the sorting of mail, but the principles are applicable in sorting other articles, as will become apparent as the description proceeds.
In the Mail Separator described in U.S. Patent No. 2,863,574, issued to Seymour Henig on December 9, 1958, each compartment `receives an article to be sorted during a cycle of operation, and the identification of each cornpartment, together with the postal destination of a letter deposited therein, are stored in a memory register. The compartments are i'illed randomly with letters which have a variety of postal destinations or categories and the letters are then discharged in accordance with a fixed, category program.
The mail separator, disclosed in the above patent, has the disadvantage that the letters in the compartments are discharged in a fixed sequence that can not provide optimum inventory reduction, except by remote chance. Again, the separator is incapable of making an internal decision on whether a category should be stacked alone, or in company with other categories, to form a bundle that is equal to or exceeds a minimum size requirement.
Accordingly, it is an object of the present invention to provide an article separator that permits optimum category reduction of the articles in a butter storage unit.
Another object is to provide a separator that is capable of making a decision on whether a category should be stacked separately, or in combination with a more inclusive category, to obtain a bundle that exceeds a selected minimum size.
Other objects of the present invention will be readily appreciated as the same becomes lbetter understood with reference to the following detailed description when considered in connection with the accompanying drawings in which like reference numerals designate like parts throughout the gures thereof and wherein:
FIG. 1 is a block diagram of an embodiment of the present invention;
FIG. 2A is a pictorial representation of a typical installation showing a plurality of individual sorting stations arranged to disch-arge sorted letters on a common conveyor belt;
FIG. 2B is a side view of a shuttle, rack of slots and the conveyor belt that are employed at each station;
FIG. 2C discloses the encoding matrices utilized at each station in developing the binary numbers that represent the slots in FIG. 2B;
FIG, 3 discloses in greater detail the timing signal generators shown as a rectangle in FIG. l;
3,366,555 Patented Jan. 24, i967 FIGS. 4A to 4D represent portions of various tracks of the memory drum in FIG. l;
FIG. 5 is a block diagram that illustrates the manner in which FIGS. 5A and 5B are assembled;
FIGS. 5A and 5B constitute la circuit diagram of the loading buffer units in FIG. l;
FIG. 6 is a circuit diagram of the transfer unit shown in FIG. l;
FIG. 7 is a circuit diagram of the tally accounting unit represented as a rectangle in FIG. l;
FIG. 8 is a block diagram illustrating the way in which FIGS. 8A and 8B are assembled;
FIGS. 8A and 8B comprise a circuit diagram of the unload category selector in FIG. 1; and
FIG. 9 is a circuit diagram of an embodiment of the stack-forming synchronizer used in FIG. l.
In accordance with the present invention, a sorting machine is provided that includes several stations, each having a rack containing a plurality of slots, each slot having a gate positioned above a common conveyor belt. An operator, reading the destination of a letter to be sorted, operates a keyboard at a station to record the related letter category code in the memory of a control computer. The letter is then dropped in the rst empty slot an-d the number code of the slot is generated and stored in the memory.
Using the generated number code and an identical number code pre-recorded in the computer, the latter places the category code for each letter in a section of the memory whose arrangement is analogous to the slot number or the letters physical location in the racks. A running inventory with respect to categories is kept for the letters stored in the slots. Periodically, the computer makes a determination, premised on optimum inventory reduction, of the next category to be unloaded from the slots. The code of this category is recorded in a section of the memory, which retains a list of the category codes of the stacks forming on the conveyor belt. The computer continuously makes identity comparisons between the categories of the stacks being formed and the category of the letters stored in the slots. Each identity is converted into a gate-opening signal, the latter controlling the gate of a respective one of said slots, permitting the letter contained therein to fall in the appropriate stack forming on the conveyor belt.
The block diagram (FIG. l)
The number of sorting stations employed in a particular installation is determined by the volume of sorting to be accomplished. In this embodiment twenty stations are used and sorting stations 1 and 20 are shown in FIG. l. Each station includes a keyboard 21 for controlling a signal generating mechanism that is generally used in a teletypewriter to develop signal patterns in binary code. An operator, by striking selected keys on the keyboard, transcribes the ladd-ress of each letter vinto a category code in accordance with an appropriate scheme list of categories.
The scheme list, in one example, may comprise two hundred direct and secondary categories. A direct category is one that requires no further sorting enroute or at the post ofce of origin, while a secondary category requires further sorting. In this example, the list includes twenty secondary categories, sixteen representing states and four representing groups of states, one hundred and seventy-five direct categories, and five spares.
Each secondary category is encoded in binary in a four position code by means of two characters and a command symbol, represented by an asterisk. New York State, for example, is designated by (Note that the second position of the code is blank.) Each direct category is encoded in binary in a four position code by the characanoche@ ters representing a related secondary category and another prefix. Rochester, N.Y., is therefore designated as RNY. (Note that here the tirst position of the code is blank.) The number of direct categories assigned to each secondary is determined by the statistical probability of the former.
After observing the address of a letter, an operator generates the related category code by striking the appropriate keys on keyboard 21 (FIG. 2A). When the address is in a direct category, the operator strikes the three characters of the category code, but when the address is a secondary category, the operator strikes the space bar 23 and the two characters of the Code. The command code :t is prerecorded in the scheme list categories track 261 (FIG. 4C) and is provided in control computer 29, when required, as indicated below.
After the category code is struck, the letter-handling mechanism 25 is activated and the letter is indexed to a central position with respect to the traverse of shuttle 26 and is dropped into either pocket 26a or Zdb. The shuttlel traverses a rack 27 of sorting slots 24a and deposits the letter in the first vacant slot encountered. When the lastmentioned operation is performed, a code representing the number of the slot into which the letter was deposited is generated (FIG. 2C).
Returning to FIG. 1, the letter category code and slot number code are applied to loading buffer units 28 in control computer `29 and are read into the information buffer section 3) of memory drum 31. The codes are then transferred from section 3@ through transfer unit 33 to information analog section 34.
The data stored in section 34 is considered to be information analog, since in this embodiment, the slot number and related letter cate-gory code are positioned, sideby-side, in successive sectors of memory drum 31 in the same sequence as the corresponding letter stored in slots 24a. It is understood, however, that the codes need not be written on the drum side-by-side so long as each letter category code is provided with a iixed displacement relative to its related number code and the number codes are read out of the memory drum, in the manner described below, in the same sequence as the slots 24a are positioned in rack 27.
Each category code in the scheme list is pre-recorded in certain tracks in the tally store section 37. A threshold code, representing the minimum number of lette-rs required for each category before it is selected for unloading, is also recorded in a track in this section. The tally accounting unit 38 keeps a running tally of the number of letters in each category stored in each slot 24a, as indcated by the recordings in analog section 34, and writes this tally in a track in section 37. All the information used to provide self-optimizing inventory reduction is now pre-sent in memory drum 31.
In the operations performed in obtaining optimum inventory reduction, the predominant categories are selected on an alternate basis with a programed category, i.e., the categories in the scheme list are unloaded in turn on an alternate basis with the categories having the greatest number of lette-rs in slots 24a when an active unload category is selected. Accordingly, during certain revolutions of memory drum 31, unload category selector 40 performs one of the following operations:
(a) The predominant category, either direct or secondary, is determined and becomes the next active unload category. (Instead of selecting an active unload category code purely by predominance, the selection may be further constrained by a threshold, so that the category code selected is related to a tally code of desired magnitude.)
(b) vThe magnitude of a tally of a programed, direct category is compared with the magnitude of its recorded threshold. At the same time, the predominant category is determined. If the tally exceeds its threshold, the direct category is selected. If not, the direct category is skipped and the predominant category becomes the next active unload category.
(c) A search is made for the predominant category. Concurrently, a determination is made of the sum of the tallies of a programcd, secondary category and all its associated direct categories, which include those skipped. If the magnitudeof the sum exceeds the magnitude of the threshold recorded for the secondary category, the letters in the secondary and related direct categories are unloaded together. If the tally fails to exceed its threshold, the predominant category is selected.
A sequence of the operations just indicated is presented below and explained in detail in connection with Table I.
After selector 46 has determined the next category of letters to be unloaded from slots 24a, the code representing this category is written on a track in information analog section 34. Each category code written on this track is compared in stack-forming synchronizer 43 with each category code in the analog section positioned adjacent the number code of the slot containing the letter. When an identity is found, the number Code, related to the Category code, is read out and passed in binary form, as one output of the stack-forming synchronizer, to decoding matrix 44. The matrix converts the binary code to a pulse on a line connected to one of the slot-gate actuators d5. The energized actuator opens the gate 24o of the related slot to drop the letter on the stack 46 forming on conveyor belt 41 (FIG. 2A).
Stack-forming synchronizer 43 instructs the tally accounting unit 38 to discount any letter in an active unload category that is located in a slot 24a in advance of the related stack being formed on conveyor belt 41. This is done so that the letters, that are dropped in slots positioned in advanced of the stack, will not alfect the tally and therefore the selection of the next active unload category.
Another output of stack-forming synchronizer d3 com= prises each active unload category code, which is directed to a conventional system, not shown, that is used to bundle, pouch and label the stacks of letters formed on conveyor beit 41.
The driving mechanism 59 comprises a synchronous motor for the memory drum 31 and a separate synchronous motor for conveyor belt 4l. The motors are driven from the same source, and the motor for the belt is provided with a gear reduction arrangement so that the time required for a reference point on the belt to traverse the width of one slot 24a, plus a fixed time interval, is equal to the time required for one revolution of memory drum 31.
The bits engraved in clocks 53 to 55 are used to drive for timing signal generators 52, which provide the timing signals for control computer 29, as will be explained in detail further on.
Letter handling and encoding (FIGS. 2A to 2C) Each sorting station I to 2Q, as shown in FIG. 2A,y includes an alpha-numeric keyboard 21, a letter-handling mechanism 25, a letter tray 57, and a rack 27.
The rack is divided by partitions into one hundred and twenty sorting slots 24a, each provided with a gate 24E-b, as illustrated in FIG. 2B. The tracks 59 are located on the rack (FIG. 2A) and shuttle 26, slidably mounted on the tracks, is adapted to be reciprocated in the directions indicated by the arrows, so as to traverse the sorting slots 24a.
The letter-'handling mechanism 25 provides a means for sequentially feeding letters individually from letter tray 57 for visual inspection by an operator and then t-o shuttle 26. Under selective control of the operator, a letter e3 is fed from tray 57, and is then translated along trackway 64 in the direction of the arrows to an inspection position 65, and from there to one of the pockets 26a or Zeb in the shuttle. For more specific details of the letter-handling mechanism, reference is made to the above-mentioned patent.
As described in the above patent, the letter-handling mechanism is at a medial position with respect to the length of rack 27. The shuttle 26 is preferably made one-half the length of the rack and is translated from one end of the rack to the opposite end. In either position, one of the pockets 26a or 2Gb in the shuttle will be in registry with the output of the letter-handling mechanism, as shown in FIG. 2B. In other words, the shuttle has two initial positions; one in which pocket 26a is at the middle of rack 27 and pocket 26h is at the left side of the rack; the other in which pocket 26b is at the middle of the rack, pocket 26a is at the right end of rack 27. In this manner, after a given traverse in which the letter has been discharged from one pocket to an appropriate slot 24a, the other pocket is automatically positioned for receiving a letter from the letter-handling mechanism. It will be obvious that such construction precludes the need for causing the shuttle to retraverse the full length of the storage bin.
Flag assemblies 75 are serially arranged in a wall of the rack 27, as shown in FIG. 2A. Each assembly is mounted for vertical reciprocation within a chamber positioned at the end of a slot 24a and includes a plunger that controls the position of a gate 24E-b illustrated in FIG. 2B. The construction and operation of a typical ag assembly is described in detail in the above patent and, for the purposes of this disclosure, is briey set forth as follows. As shuttle 25 traverses the length of the rack 27, the ag assembly 75 of the rst vacant slot 24a will be elevated and will be contacted by the pin of a bell crank positioned on the shuttle. The flag, together with its plunger will be displaced downward. Concurrently with such downward displacem-ent of the plunger, the bell crank rotates to pivot a gate 26e that is mounted on either pocket 26a or 26k, permitting the letter 63 carried in the pocket to be discharged into a slot 24a associated with the activated flag assembly. In this manner, a letter is transferred from letter tray 57 to shuttle 26 and from there to the first vacant slot in rack 27.
When the ag assembly 75 and its associated plunger is depressed, a switch is closed, as indicated in the above patent. Each switch 77a. or 7717 is illustrated in FIG. 2C and in this embodiment, is of a type, well known in the art, that will provide a momentary pulse when closed by the plunger and n-o pulse when opened by the plunger.
When the Hag assembly of a slot 24a in rack-half X (FIG. 2B) is depressed, indicating that a letter will be deposited in the slot, a related switch '77a (FIG. 2C) is closed and a pulse is applied from potential source 78 through the switch to encoding matrix 79a. The encoding matrix generates signal X in a six-bit binary code. Likewise, when a ag assembly in a slot 24a in rack-half Y is depressed, an associated switch 77b is closed and a pulse is transmitted to encoding matrix 79b. The latter matrix develops signal Y in a six-bit binary code. Each signal X, Y represents the number of the slot in rack-half X or Y, respectively, into which the letter 63 will be deposited. The outputs of the encoding matrices are directed to the loading buffer units 23 in FIG. l, which are shown in detail in FIGS. 5A and 5B.
Timing signal generators (FIG. 3)
The timing signal generators 52, shown in detail in FIG. 3, provide the timing signals that maintain the various components of control computer 29 in synchronization.
With reference to FIG. 3, there are twenty-four hundred bits engraved in clock track 53. This track is continually sensed by read amplifier 88 whose output is applied to 6-counter 09. The counter has six outputs, a1- ternately activated, to generate bit pulses 6C in a continuous sequence.
Clock track 54 contains forty equally spaced, engraved 6 bits dividing the ieinory drum 31 into forty equal sectors, each sixty bits long. The start of each sector is aligned with one of the bits engraved on track'53. (See FIGS. 4A, 4B.) The read amplier 90 senses track 54 and applies pluses to l0-counter 91, which provides time gates 40C. The latter comprise time gates 40C-1X through 40-20X and 401Y through 40C-20Y. Each time gate appears on a separate line; -and each time gate, ending in a number and X, is generated before the time gate ending in the same number and Y.
Whenever a pulse is applied to an input terminal marked 1 on a ip-tlop, in accordance with the notation used herein, the flip-Hop is turned on, and whenever a pulse is applied to an input terminal marked 0, the flip-dop is turned off.
Read amplifier feeds forty equally spaced pulses to terminal 1 of flip-Hop 94. On coincidence between the output of flip-flop 94 and pulse 6C-1 in and-gate 95, a signal is applied to 4-counter 96 which is then advanced. The output 4C of this counter comprises time gates 4C-0 to 4C-3, each appearing on a separate line.
The two hundred bits engraved on clock track 55 divide memory drum 31 into two hundred sectors, each having space for twelve bits. (See FIG. 4C.) Each bit in these sectors is aligned with a bit in clock track 53. Track 55 is sensed by Iread amplifier 97 to obtain 200K bit pulses. Track 93 forms a tach clock containing one pre-recorded bit or liducial mark which is aligned with a bit in each of clock tracks 53 to 55. The latter track is sensed by read amplifier 99, whose output is output is applied to counter 107 to count the revolutions of the memory drum 31. The read amplifier also provides an R-bit pulse during each revolution of the drum.
Each of the devices shown in a box, containing REV and other notations, is an arrangement, well known in the art, that provides a signal representing a number in binary code. Thus, when a count of four is preset in device 102, there will be an output from comparator 103 each time a count of four appears in counter 107. The output of device 102 determines the pitch between letter stacks, i.e., the distance between stacks 46 in FIG. 1, expressed as a multiple of the width of one slot 24a.
The outputs of counter 107 and device 105 are compared in comparator 110 so that on the occurrence of an identity, time gate R2 is generated. Likewise, on the occurrence of an identity in comparator 111 between the outputs of counter 107 and device 104, time gate R-l is generated. The trailing edge of time gate R-1 resets counter 107 to a count of 2.
The output of comparator 103 advances counter 116 to develop signal xC, representing a multiplier of the number of revolutions of memory drum 31 that is preset in device 102. Signal xC and the output of device 106 are directed to comparator 115, which, on the occurrence of an identity, provides time gate R-xSS. Time gates R-1 and R-xSS are transmitted to and-gate 117 whose output resets counter 116 to 0.
Thus, if is set in device 102, if 101 is set in device 104, and if 2 is set in devices 105 and 106, then each time that 101 is recorded in counter 107, time gate R-1 is developed by comparator 111. Each time that counter 107 is reset to 2, time gate R-2 is generated by comparator 110, and each time that counter 116 records 2, or every 200th revolution of memory drum 31, time gate lR-.rSS is generated by lcomparator 115. (See Table I.)
Devices 102 and 106 are provided with suitable panel adjustments, not shown in the drawings.
The manner in which the various timing signals just described are used to synchronize the units of control computer 29 will ybecome apparent as the description proceeds.
The loading buer units (FIGS. 5A, 5B)
The loading buffer units 28, shown in detail in FIGS. 5A, 5B, accept letter category and slot number codes as they are aperiodially generated at the sorting stations 1 to 20 and effect the recording of these codes in loading buffer tracks 121) and 121. These tracks are located in the information buffer section 30 in FIG. l.
The circuits in dotted box 122 are typical for each sorting station and are explained in detail in conjunction with the operation of station 1.
It will be recalled from FIG. 3 that time gates 40C divide memory drum 31 into forty sectors; two sectors. are assigned to each sorting station 1 to 20. The sectorsv for station 1 are delimited by time gates 40C-1X and 4t!-C1Y, the sectors for station 2 by 40C-2X and LC-ZY, etc. The time gates 40C-1X and 4C-1Y are applied to and-gates 123 and 124, respectively,
When a key is struck on keyboard 21, a binary code, representing a character in the letter category code, is applied in parallel form to 128, which denotes six andgates. Each time a key is struck, 3-counter 129 is advanced. The output of 129 is denoted by 3C, comprises signals 3C-1 to -3 and is fed to comparator 131), On the third count of counter 129, signal 3C-3 is passed through or-gate 131 to the letter-handling mechanism 25, which then moves the letter from inspection position 65 (FIG. 2A) to shuttle 26. The output of or-gate 131 is branched through delay device 134 to reset the counter to 0.
It is apparent that the function of ycounter 129 is to limit a category code to three characters. If another scheme list is used that contains a category code having a blank in the third and/or fourth position, such as the operator strikes the character or characters of the code and then the end of category key 135 (FIG. 2A). A signal is then applied through or-gate 131 to reset counter 129 and to the letter-handling mechanism to move the letter away from the operator inspection position.
Assume that just before the example described below, a letter was deposited in rack-half Y. In encoding the category of this letter, 2-counter 132 was advanced to apply signal X through delay device 150 to terminal 1 of flip-iop 151, so that during the appropriate time interval in the example just below, the flip-flop is turned on and applies a signal to and-gate 149. Signal X is also branched to and-gate 123.
Now assume that a direct letter category code RNY is struck by the operator on keyboard 21. Because shuttle 26 is in the positio-n shown in FIG. 2B, the letter associated with the category code, just struck, will be deposited in the first empty slot 24a in rack-half X.
When the R key is struck, a signal in binary code is applied in parallel form to and-gates 12S. On the occurrence of time gate 40C-1X, which marks the start of the one-fortieth sector of tracks 121i and 121 shown in FIG. 4A, the Ioutput of and-gate 123 is directed through orgate 136 to and-gate 137. On coinciden-ce of time-gate LC-l and signal 3C-1 in comparator 130, the output of the comparator is appli-ed to and-gate 137. The next sequence of time gates 6C-1 to -6 enables and-gates 128 and the category code R passes in serial form through orgate 140, and-gate 137, or-gates 141 and 142 to the iwrite amplifier 143. The six bits of code are then written in the space allocated to character No. 1 in track 120. (See FIG. 4A.) The first section of the one-fortieth sector consisting of six bits in track 121) is reserved to permit a related slot number to be written first when the information recorded in the remaining sections of this sector is transferred t-o track 121.
After the N key is struck, on the occurrence of time gates 40C-1X, `6C-1 to -6, and the coincidence of sign-al 3C-2 and time gate 11C-2 in comparator 130, the six-bit binary code representing N is recorded in the section of store track 12@ marked character No. 2. Likewise, after Y is struck, on the occurrence of the last-mentioned time gates and the coincidence of .3C-3 and 1C-3 in the comparator 130, the code representing Y is written in the section of the track marked character No. 3.
When the operator depresses the Y key, counter 129 generates signal 3C-3, which is transmitted through orgate 131, delay devices 134.1, 147 and time gate 148 to and-gate 14%. Since signal X was sent through delay device 151') to terminal 1 of flip-iop 151, the latter applies a signal to and-gate 149. On the occurrence of time gate 40C-1X, the latter and-gate is enabled and a transfer delay signal is applied through or-gates 154 and 155 to and-gate 156. Read `amplifier 157 then reads track 120 and applies the category code RNY through and-gate 156 and or-gates 160 and 161 to write amplifier 162. The latter records the code bit-by-bit in the sections of track 121 reserved for character Nos. 1 to 3, as represented in F1G. 4A.
The lcategory code is branched from `and-gate 155 to the write amplifier 163 and is thereby recorded on retimer track 164. The code is read by read amplifier 165 from the retimer track, is converted to an erase signal in eraser 166, and is applied through oir-gate 142 to write amplifier 143. Thus, within one revolution of memory drum 31 after the category code is shifted from track 121i to track 121, the code just r-ead from the former track is erased.
The retimer track method, just described, provides an erasing means that is independent of the speed setting of memory drum 31, and this means is used where applicable in other functions of control computer 29. An eraser head that clears the retimer tracks for immediate reuse is positioned, but not shown in the drawings, between the read yand Write amplifiers associated with each retimer track.
The output of gate 148 is branche-d through delay device to terminal 0 of flip-fiop 151, turning the flip-flop ofi.
The value of delay devices 150 and 179 are selected so that one 4of the and-gates 149, 172 may be enabled only after the other has transmitted a transfer sign-al through or-gates 154 and 155 to and-gate 156. Time gate 14? and -delay device 134 have values dependent upon the speed of rotation of memory drum 31.
It will be recalled that the category codes of the letters deposited in rack-half X are recorded in sequence in a single assigned one-fortieth sector of track 121. Likewise, the category codes of letters deposited in rack-half Y are Written in sequence in another single assigned sector of track 121. The codes for each rack-half are recorded on an alternate basis. The value of delay device 147 is selected to insure that the previous category code has been read out `of track 121 before the present code is recorded in the same assigned sector of the track.
When, as set forth above, the operator depresses the Y key, counter 129 is advanced and signal SiC-3 is generated and applied through `or-gate 131 and delay device 134 to reset the co-unter to t?. The signal 3C-3 is branched to the letter-handling mechanism 25, thereby starting the letter moving away from the operators inspection position 65. The letter is deposited in pocket 2Gb `of shuttle 26 and then in the first empty slot of rackhalf X. The shuttle is then moved in FiG. 2B so that pocket 26a is positioned to receive a letter from the letterhandling mechanism. Signal 3C-3 is branched to 2- counter 132 to advance the counter which then develops signal Y, thereby permitting the ycategory code for the next letter to be Written in the one-fortieth sector associated with time gate 4tPC-1Y, as described below.
As the letter is deposited into slot 24a, one of the switches 77a is closed and a pulse is applied to the encoding matrix 79a in FIG. 2C. The signal X' appearing in t-he output of the matrix represents the number of the slot in binary code and is applied in parallel form to 176, which designates six and-gates in FiG. 5B. When time gates `6C-1 through -6 are applied to and-gates 176, the slot number code is passed through `or-gate 177 in serial form to arid-gate 178. Time gates 40C-1X `and AlC-t) are also applied to this and-gate. When there is coincidence among all three signals, the output of aud-gate 178 is asoaoe 9 sent through or-gates 181, 182, 160, and 161 to Iwrite amplifier 1-62. The sl-ot number code is now Written serially in its reserved section in track 121. (See FIG. 4A.) The lcategory code -RNY is recorded, as stated above, in the sections of this track reserved for character Nos. 1 to 3.
As indicated above, upon the completion of the category code for the letter headed for rack-half X, signal Y is applied to rand-gate 124. On the occurrence of timegate 40C-1Y, the output of and-gate 124 is passed through or-gate 136 to and-gate 137 t-o enable the category code for the next letter to be Written in track 120. (This letter will be deposited in rack-half Y.)
Signal Y is also branched through delay device 179 to terminal 1 of dip-flop 171 and the o-utput of the flip-flop is -applied to and-gate 172. At the appropriate time, as described in the example presented above, the output of the latter and-gate, which is the transfer delay signal, will enable and-gate 156 to transfer the letter category code from track 120` to track 121.
Further, signal Y', representing the number of the slot in binary form, is applied in lparallel form to the six and-gates 183. O-n the occurrence of time gates 6C1 to 6, signal Y is passed through or-gate 184 in serial form to and-gate 185. On coincidence of the latter signal and time gates 40C-1Y, 1C-) in and-'gate 185, the slot number code is `passed through or-gates 181, 182, 160, and 161 to write amplifier 162 and is recorded in the section of track 121 reserved for the slot number code.
The above examples were given for sorting station 1. When a station 2 to 2t) is activated, a slot number code, a transfer delay signal and a category code are applied lfrom t'he corresponding control circuits in dotted box 122 in that station to or-gates 182, 155 and 141, respectively.
Transfer unit (FIG. 6)
The circuit in FIG. 6 represents the transfer unit 33 in FIG. 1, whose function is to transfer each category code in information store section 30, nam-ely track 121, to a position adajacent its related slot n-umber in the information analog section 34.
When the sorting machine is turned on, initial set device 186 is adjusted on the panel to generate a signal that passes through or-gate 229 to termi-nal 1 of flip-fiop 187, turning the fiip-flop on. On coincidence of the output of the flip-flop and a 40K pulse in and-gate 18S, the output of this and-gate clears `6-bit register 189 and turns on flipfiop 190. The latter, in turn, applies a signal to and-gate 191. Since the read amplifier 192 reads track 121 continuously, when time gate LlC-i is applied to the latter and-gate, the information relating to a slot nurnber is passed through the and-gate in serial yform to register 189.
Flip-flop 193 is turned on by the 40K pulse, just mentioned, and is turned off by virtue of a 'branch of the output of and-gate 191 that is applied to terminal 0 of the fiip-flop.
The information in the Output f and-'gate 191 is also branched through or-gat-e 194 to write amplifier 195 and is Written on retimer track 196. The latter track is sensed by read amplifier 197, whose output is converted to an erase signal in eraser 198. The erase signal is passed through or-gate 161 to write amplifier 16,2 where it is used to erase from track 121 the slot number code just recorded in register 189.
An output of register 189 is passed through or-gate 199 to and-gate 200. Since time gates 4C-1 to -3 and the output of flip-flop 190 are also ap-plied to this and-gate, after the slot number is recorded in register 189, the related letter category code is read out of track 121 and is passed through and-gate 200 in serial form to 18-bit register 201.
The information in tracks 284 is retarded from the information in track 121 `by one-fortieth revolution of memory drum 31. Thus, during one-fortieth revolution of the drum, a slot number code is read out of track 121 and is stored in register 189, and d-uring the following 1d one-fortieth revolution, the contents of the register is conipared with each slot num'ber code read out of tracks 204.
More specifically, during the one-fortieth revolution of memory drum 31 when a number code is shifted bit- Iby-bit into register 189, the code is ybranched to terminal (i of liip-flop 193. The flip-flop is turned off, blocking the six and-gates 205, so that a comparison can not be made in comparator 206 between the code in register 189 and the slot number codes read from tracks 2114. After the code is stored in register 189, the next 40K pulse, marking the start of the next one-fortieth revolution of the drum, is transmitted to terminal 1 of fiip-fiop 193, turning the fiip-op on to enable and-gates 285. The code in register 189 is then sent through and-gates 20S to comparator 286. During this one-fortieth revolution, each slot number code, pre-written in tracks 284, is sensed Iby read amplifiers 207 and applied to comparator 2116. When an identity is obtained in the comparator, a signal is applied to 2118, which designates eighteen and-gates. This signal enables and-gates 298 to pass the category code stored in register 2111 through eighteen or-gates 221 to write amplifiers 222. The category code is then written in parallel form in eighteen tracks designated by 223, and on line with the relate-d number code in tracks 204. (See FIG. 4B.)
The output of comparator 296 is Ibranched through or-gate 224 to the write amplifier 225 to record a l on count-bit track 226, adjacent to the category code just written into tracks 223. (See FIG. 4B.) This indicates that a category code has been recorded in tracks 223, which as yet has not been tallied.
The output of comparator 266 is also branched through or-gate 22@ to terminal 1 of flip-flop 187 to turn the flip-'flop on and thereby send a signal to and-gate 188. Upon the occurrence of the next 40K pulse, the output of this and-gate clears register 189, turns flip-flop 19t) on and flip-flop 187 off.
At this point, it is convenient to present with the assistance of FIG. 4D, a brief summary of the operation of the transfer 4unit 33 in FG. 6. Sector 1Y of memory drum 31 is assigned to the second rack-half or rack-half Y of station 1, while sector 2X is assigned to the first rack-half or rack-half X of station 2. The -first 40K pulse, referred to above, marks the start of sector IY.`
As the `drum rotates in the direction indicated in the figure, this section ypasses the alignment point P and the slot number and letter category codes designated as A are read out of track 121 and are recorded in registers 189 and 281, respectively. The second 40K pulse, referred to above, marks the end of 1Y and the start of sector 2X. As this sector traverses alignment point P, an identity is found in comparator 206 between the slot number code recorded in register 189 and one of the Asixty number codes pre-recorded in tracks 204. The output of the comparator enables and-gates 2118 to pass the letter category code to write amplifiers 222 which then write the code in store tracks 223.
As sector 2X Ipasses the alignment point P, read amplifier 192 reads the category and num-ber codes designated by B in FIG. 4D. However, since flip-flops 187 and 190 are turned off, these codes are l'blocked by and-gates 191 and 200 and are unable to pass to registers 189 and 201, respectively.
It should 'be noted that the information concerning a letter in a slot 24a of rack-half X or Y, at a particular sorting station 1 to 20, is read out of track 121 during one one-fortieth revolution of the track past the alignment point P. An identity is sought and the letter catelgory code is written into tracks 223 during the succeeding one-fortieth revolution of the tracks. This arrangement is used since the serial read out of track 121 consumes part of the traverse of tracks 223 past the alignment point P. Thus, transfer of information from track 121 to tracks 223 utilizes two adjacent sectors, each of onefortieth revolution of memory drum 31.
It is possible that an operator at one of the sorting stations 1 to 2t) will encode a letter to be deposited into rack-half Y, while simultaneously an operator at the next station will encode a .letter to be deposited into rack-half X. Assume that the information relating to the two letters is designated by A and B in FG. 4D. Then, during one revolution of memory drum 31, the information relating to one letter, or A, will be transferred from track 121 to tracks 223, and during the next revolution, the information relating to the second letter, or B, will `be transferred 121 to 223. Accordingly, with the unlikely occurrence of simultaneous encoding by all twenty operators at stations 1 to 2d, it would take no more than two drum revolutions to transfer all the letters information from track 121 to 223. This speed will be at least ten times the operators combined production rate.
Each output of re-gister 261 is branched to an or-gate 292, so that any information in the register' applies a signal through the ordgate to and-gate 2493. On coincidence of this signal with the end of time gate 4C-3, the output of and-gate 263 is applic-d to terminal (l of flipflop 190, turning the latter 01T. This will prevent the transfer of additional information through and-gate 290 to register 201, or through and-gate 191 to register 189. Thus when information is present in the latter registers, it cannot tbe over-written by the output of read amplier 192, which continually reads track 121.
The output of and-gate 26d is branched through orgate 194 to write amplifier 195 so that the letter category code, -just read out of track 121 and recorded in register 201, is erased from the track in the same fashion as the related slot number code.
The six tracks 234, located in information analog section 34, contain the numbers, pre-written in parallel form, of all the slots in sorting stations 1 to 20. Each station is assigned two 40 sectors of tracks 204 and each sector contains the slot numbers of either rack-half X or Y positioned at that station. In this embodiment, each rack- Ihalf comprises sixty slots `and each 40 sector of tracks 264 contains sixty slot number codes, as illustrated .for one sector in FIG. 4B.
Tally accounting mit (FIG. 7)
The circuit in FIG. 7 is the tally accounting unit 38 in FIG. l, which is assigned the function of keeping a running inventory of the number of letters in each category stored in slots 24a. Because the stack-forming synchronizer 43, described in detail below, searches the information in analog section 34 vby category, an applicable letter will unload to its stack as soon as the latter arrives under the letters slot without regard to the letters accounting. Therefore, to keep the desired accounting, a letter is disregarded When it is in an active unload category and is positioned in a slot in advance of the categorys stack, forming on conveyor belt 41.
With reference to FIG. 7, the combination of andgate 23@ and inverter 231 comprise and-notgate 232. Thus, when a bit is not applied to the input of inverter 231, a l :can appear in the youtput of and-not-gate 232, and when `a bit is applied to the input of inverter 231, a G appears in the output rof 232.
'It will be recalled that when a category code is written into tracks 223, a l bit -is written beside the code in the count-bit track 226. (See FIG. 4B.) The accounting starts When read amplifier 235 reads a bit from this tra-ck. The bit is transmitted through anddgate 230 to the eighteen and-gates 236, while at the same time, read amplifiers 237 sense tracks 223 and transmit the letter category code, related to this bit, in parallel form through and- `gates 23@ to the lS-bit register 238.
When information is present in register 238, its output is passed through yor-gate 239 to inverter 231, thereby blocking and-gates 230, 236, so that further information will not be recorded in the register. Thus, any other bits acter 3,
recorded in track 226 are ignored until register 238 is empty.
The contents of register 235 is immediately compared in comparator 244 with the contents of the succeeding 1Q- fbit register 241. Since an equality yields an output which clears register 233, the same category code can not succeed itself in both registers.
On the occurrence of the next R-bit pulse, the category code in register 23S is transferred in parallel form through the eighteen and-gates 240 to register 241. The R-bit pulse is applied to terminal 1 of flip-dop 250, whose output is sent to and-gate 251, which is enabled in the manner indicated below to advance counter 252.
The information in register 241 is branched to c-o-mparator 249 and the output of read amplifiers 237 is likewise branched to this comparator. Accordingly, the comparator provides an output signal for each category code in tracks 223 that mat-ches the code in register 241. Each output signal is passed through and-gate 251 to advance counter 252. Because flip-flop 259 is set by the R-bit pulse, the counter will .start at the beginning of the revol-ution of track 223 and will tally all the category codes in the tracks that yare identical to the code contained in register 241.
In keepin-g a running inventory of the letters stored in slots 24a, all letters in an active unload category, positioned in advance of the related stack 46, forming on conveyor 'belt 41, are disregarded. This is `accomplished by turning olf flip-flop 25u to inhibit the `co-unt of a category Vfor the remainder of the revolution of memory drum 31 when the code being tallied represents an active unload category. The circuitry used to achieve this result will .be set forth in the last few paragraphs of the description of FIG. 9.
When an identity is found in comparator 249, its output is branched to write amplifier 255 and recorded on retimer track 256. This track is sensed by read amplifier 257 Whose output is `directed to eraser 258, converted to an erase signal, a-nd then passed through or-gate 224 to lwrite amplifier 225. In this way, each `bit that is related t-o the letter category code applied t-o comparator 249, if present, is erased from track 226.
It should be noted that the erasing of Ibits from track 226 for a category code continues for a full revolution of memory drum 31, although the tally may lbe terminated at any point before completion of the revolution.
When the tally is completed, the next R-bit pulse enables the nine and-gates 259 to shift the tally code in -counter 252, in parallel form, to the 9-bit register 260. The .same R-bit pulse enables 245, representing eighteen and-gates, to ltransf-er the letter category code in register 241 to lS-bit register 246.
From the foregoing, it will be seen that Whenever a new letter category code is added to tracks 223, the number of letters in slots 24a designated by this categ-Ory is tallied, a tally code is recorded in register 269, and the category code is recorded in register 246.
The 200K pulses on track 55 -divide this track, as well as tracks 261, 262, 285 and 290 into two hundred sectors, each containing twelve bit-places, as illustrated -by one sector in FIG. 4C. Each bit-place in these tracks is in line with a bit in clock track 53. The tracks are rotated in the direction indicated in the figure.
lEach sector in track 251 and a related sector in track 262 has pre-written therein one of the .category codes of the scheme list. l-f the scheme list is altered to perform a desired sortinfy operation, the codes recorded in these tracks are altered accordingly. For each secondary category code, the command code is pre-written in the 6-bit position `of track 261 marked command Thus, for :t NY, the command code and characters N and Y are pre-written in binary form in the positions of tracks 261, 262 marked comman-d, character 2 and charrespectively. Likewise, characters Nos. 1, 2, and 3, of -a direct category code are pre-written in the