|Publication number||US3321673 A|
|Publication date||May 23, 1967|
|Filing date||Jan 27, 1964|
|Priority date||Jan 27, 1964|
|Publication number||US 3321673 A, US 3321673A, US-A-3321673, US3321673 A, US3321673A|
|Inventors||George Wolfe James|
|Original Assignee||Halliburton Co|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (6), Referenced by (9), Classifications (6), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
May 23, 1967 G.W FE 3,321,673
EIJiKZ'lRONIC COMBINATION LOCK Filed Jan. 27, 1964 Y 2 Sheets-Sheet 1 I25 T I 3/0 Q 7 7 INVENTQRB 'iymfiwm w TTORNEY' I A A May 23, 1967 J. G. WOLFE 3,
I ELECTRONIC COMBINATION LOCK Filed Jan. 27, 1964 2 Sheets-Sheet 2 INVENTOR %'g Jana '6! W061? A ATTORNEYS nited States Pate The present invention relates to an electronic combination lock, and, more particularly, the present invention relates to an electronic combination lock wherein the combination must be set in a preselected sequence and wherein'the combination can be changed quickly at will. This is a continuation-in-part application and improves upon the electronic lock found in my copending application Ser. No. 276,704, dated Apr. 30, 1963, now abandoned.
There are many combination type locks available but most operate upon a mechanical tumbler principle or an electric relay principle to open or unlatch a iock. Very few locking devices are known which employ electronic circuitry and practically all of such devices are one form or another of card or check-controlled locks which operate to unlatch and provide access through .a locked door or gate only responsive to insertion or application of a special card or check.
Locking devices of the combination type as are presently available suffer the drawback of not being quickly changeable at will. Some other disadvantages of present locking devices are high cost, unreliable operation, and the necessity to carry a check or card to operate the lock.
Accordingly, it is the principal object of the present invention to provide a locking device that is electronic in character and which is operable on the basis of a combination or permutation which must be exercised in a preselected sequence. One of the main features of the electronic locking device of the present invention is that the combination can be changed at will very expediently. Persons who are authorized to operate the locking device need to know both the combination and the exact sequence of the combination, but having this information can successfully operate the locking device. A further feature of the present invention is that failure to operate the combination of the locking device in the proper sequence or taking too much time to operate the combination results in the locking device resetting itself automatically.
The foregoing is accomplished by the present invention by providing a series of buttons electronically interconnected with a suitable power supply and an appropriate latch-operating relay. The buttons must be depressed in the exact and proper sequence and they actuate the blocks of the electronic circuitry progressively step by step ultimately to admit power to the unlatching relay. If any button is pressed out of order, if a button is pressed which should not be pressed, or if too much time is consumed, the electronic circuitry resets itself to the initial condition.
Another feature found herein is means to prevent interaction between the electronic stages so that the tripping of one stage will not affect any other stage. Furthermore, entrance can not be effected by positively shorting the circuits at the pushbotton panel, as will be explained below.
' In a more specific from of the present invention, a plurality of step switches are interposed between the set of buttons and the electronic circuitry with appropriate lead connections between the buttons and step switches so that the step switches can be manipulated to change at will the combination of buttons and the sequence in which the buttons must be depressed.
A further feature of the present invention is the provision of extra buttons which are interconnected to reset ICC the apparatus to its initial condition in the event any of them are depressed. These extra buttons, along with the buttons noted in the foregoing, are connected in the preferred specific form of the present invention, with step switches and hence, if it is desired to employ a six number combination, it is conceivable to employ ten buttons, any six of which may comprise the combination, with the remaining four constituting a direct interconnection to reset the locking device to its initial condition. Thus, the number of combinations and permutations that are possible are even greater than if merely six buttons were employed for a six button combination.
It is a still further object of the present invention to provide an electronic combination lock that will provide a convenient and easy method for controlled access to areas desired to be maintained under security.
It is another object of the present invention to provide an electronic sequence combination lock of the type previously described so that unauthorized persons, without the knowledge of the proper combination, will find it virtually impossible to operate.
It is a further object of the present invention to provide a locking device of the type described above which includes facilities for programmed combination changes which can be effected rapidly and expediently.
It is a further object of the present invention to provide a locking device of the character described which will include a control feature that will automatically reset the device to the beginning of the combination either if an improper button is pushed or after a predetermined time interval.
It is another object of the present invention to provide an electronic locking device employing semiconductor components which will operate reliably and be maintenance free.
Other and further objects of the present invention will become readily apparent from the following detailed description of the present invention when taken in conjunction with the appended drawings which portray in schematic form in FIGURES 1A and 1B the preferred embodiment of the present invention. The schematic diagram is too big for a single sheet of drawing and has been divided into a left part (FIG. 1A) and a right part (FIG. 1B) which are jonied together along line AB.
Referring now to the drawings, a preferred embodiment of the present invention will now be described in detail. As shown, a suitable AC. power source is coupled by a transformer 10 to a full wave rectifier comprised of diodes 12 and 14 and the center-tapped secondary of the transformer 10. The output from the rectifier is taken between center-tap terminal 16 and terminal 18. A conventional filter array comprised of capacitors C3, C4 and C5 and resistors R54, and R55 receives the output from the rectifier. Fuses F1 and F2 are incorporated in the power supply for protective measures. The output from the power supply is taken from terminals X and Y and comprises -12 volts at terminal X and a preselected positive reference potential at point Y, such as +12 volts. Resistor R53, comprising a current limiter, is coupled between the center-tap terminal 16 and terminal Z. Coupled between one side of the secondary of transformer 10 and the junction point between resistor 55 and capacitor C4 is an AC. buzzer coil 20 and a button switch 22 in series, the buzzer serving to call someone to the locked door in case the combination is forgotten or unknown.
Terminal Y is connected by line 24 to line 26 at junction 28. Terminal X is connected by line 30 to line 32 at junction 36. Line 32 connects in parallel with a plurality of button switches identified by reference numerals S1, S2, S3 S9 and S10. The other side of each switch is connected in parallel with each of ten step switches identified by the reference numerals SS1 to 10. The arm 40 of the first step switch SS1 is connected by lead 42 to line 44 at junction point 46. Line 44 is connected to resistor R11, resistor R3, capacitor C2, potentiometer R1, and capacitor C1. Resistor R11 is connected to the base of transistor Q1 which has its collector connected via resistor R to line 22. The emitter of transistor Q1 is connected to terminal 48 to which is also connected the collector of transistor Q2. Resistor R8 also connects terminal 48 with the base of transistor Q3. The emitters of transistors Q2 and Q3 are connected to line 26. Capacitor C2 is connected between line 26 and terminal 92 for the purpose which will be explained below. The collector of transistor Q3 is connected via resistor R12 to line 32. A resistor R9 connects the collector of transistor Q3 with the base of transistor Q2. Bias resistors R6 and R7 interconnect the bases of transistors Q2 and Q3 with line 26.
Transistors Q4 and Q5 are interconnected in a flipfiop circuit including bias resistors R and R16, coupling resistors R17 and R18 and load resistors R19 and R20. Load resistor R19 is approximately five or six times greater than load resistor R20 to reduce the voltage drop across transistor Q4. The emitter of transistor Q4 is connected to the collector of transistor Q3 and hence its path to return line 26 is through transistor Q3. Capacitor C6 is connected between the base of transistor Q4 and line 26. The emitter of transistor Q5 is tied to line 26. The flip-flop circuit is arranged such that transistor Q5 is normally on and transistor Q4 oif and the circuit cannot be flipped to turn transistor Q4 on unless transistor Q3 is already conducting. The arm 60 of step switch SS2 is connected via resistor R14 to the base of transistor Q4. The switch arm 60 is also connected through resistor R14a to line 90.
All subsequent step switches SS3 to and including SS6 are connected to flip-flop circuits arranged in the manner of the flip-flop circuit described with reference to step switch SS2 which has been enclosed within a dotted line and to which the reference numeral 70 has been applied. Hereafter in the description, reference numeral 70 will be used to indicate a flip-flop stage. As shown, there are five such stages altogether. The emitter of the first transistor of each stage is coupled back to the collector of the first transistor in the preceding stage. Consequently, the various stages are cascaded such that all of the first transistors in preceding stages must be on before a transistor in a succeeding stage can be turned Starting with the flip-flop stage 70 connected with step switch SS3, the coupling resistors R21, R28, R and R41 between the arms of the step switches and the flipflop stages are bypassed by a series of diodes identified by the referenec numerals CR2-CR5. The arms of the associated step switches have been given the reference numerals 82, 84, 86 and 88. Each of the diodes CR25 is connected with line 90 which interconnects with junction point 92 via diode CR1. Junction point 92 is coupled by resistor R4 with the base of transistor Q2. The last four step switches SS7-10 have their arms 100, 102,
.104 and 106 connected in common to line 110 which is coupled via resistor R13 to junction point 92.
For convenience, the transistors in the flip-flop stages have been given reference numerals as well as all other circuitry shown schematically. Two such flip-flop stages, namely, the third and fourth stages, have been shown in block form only.
The output from the last flip-flop stage is taken from the collector of transistor Q13 and is applied to the base of transistor Q14 via current limiting resistor R49. The 12 volt power supply of line 32 is applied to the collector of transistor Q14 via resistor R50. Transistor Q14 acts as a buffer stage and also provides the high current necessary for the base drive of transistor Q15. This transistor Q15, is normally off and has its collector output connected through a solenoid identified by the reference numeral 120. A. diode CR6 and resistor R52 is shunted across the coil of solenoid between the collector of transistor Q15 and line which line connects to terminal Z. The purpose of resistor R53 is to function as a current limiter to limit the current in line 125 to approximately 350 ma. The purpose of the shunt provided by diode CR6 and resistor R52 is to take care of the side effects which occur during collapsing of the field in the coil of solenoid 120. Energy is leaked to the opposite side of the line and back voltage is prevented from being applied through the collector of transistor Q15. Resistor R51 couples the emitter of transistor Q15 with its base and provides a bias. The emitter of transistor Q15 connects with line 26 which provides the positive or return side of the circuit.
' Although the preferred embodiment has been shown and described in terms of PNP semiconductor devices and for this reason the supply voltage is negative, it will be appreciated that other comparable electronic devices may be used as, for example, NPN devices, in which case the power supply would have to be a positive voltage. But such details are Within the experience and knowledge of those skilled in the art and need not be dwelled upon at length.
The operation of the circuit described above will now be set forth. As already noted, the circuitry enclosed within the blocks designated as 70 are flip-flops with the second transistor of the pair being normally on and the first transistor of the pair being normally off. A description of the operation of the power supply will be omitted altogether since it is routine and conventional in character and known to anyone having even mediocre skill in the art. Transistor Q1 is normally off as are transistors Q2 and Q3.
The locking mechanism (not shown) is unlatched by relay or solenoid 120 by depressing the proper button switches S1 to S10 in the proper sequence. The combination is determined by the setting of the step switches SS1 to S510 and it is only important that the step switches each be on different settings. For convenience, an assumed position setting for the step switches has been shown on the drawing. Thus, it is clear that step switch SS1 has been set to position No. 7 and, as will be recalled from the foregoing, button switch S7 is connected to position 7 on all of the step switches. There-fore, in order to complete the power supply to the electronic circuitry, it is necessary to first depress button switch S7 (not shown) in order to admit the -12 volt power supply on line 32 through position 7 of step switch SS1 to the arm 40 and through line 42 to junction point 46.
The resistor-capacitor combination of R3 and C2 provides a pulse speed-up circuit which applies a negative spike rapidly to the base of transistor Q3 turning same on. Capacitors C6, C7 C8 function to counteract the capacitive reactances taking place in the length of cable between the pushbutton panel and the master control unit. Without the use of said capacitors, it may be possible to inherently trigger a following stage due to said inherent capacity between a triggered stage and its following stage. Therefore, the said capacitors insure a six button operation for a six button code. Since it is known that the cable capacitance increases with the length of the cable, the values of said capacitors must be increased to compensate for said changing length depending upon the design and installation requirements of the network. When Q3 is turned on, the power supply is also placed on the time reset circuit comprised of potentiometer R1, capacitor C1 and resistor R2. The purpose of the time reset circuit is to maintain operation after button 7 is released. Capacitor C1 will immediately charge to the supply value, and when the button 7 is released and the power supply to the junction point 46 has-been cut off, capacitor C1 will discharge over a predetermined and preselected interval of time as determined by the setting of the arm of potentiometer R1. In the preferred embodiment illustrated and being described, the discharge of capacitor C1 takes place over a second interval. This is deemed ample time to depress the six buttons of the combination to cause the actuation of the locking mechanism by means of the relay or solenoid 120, and to provide ample time for ingress.
The resistors R1441, R21a, R28a, R35a, R41a are needed at all stages except the first and function to prevent gaining entrance by shorting the six digit arms together. It can be seen that if such shorting was done then all flip-flops would be simultaneously tripped if the first button (7 in our example) were pushed. Each said resistor is valued such that its individual magnitude is large enough to prevent suflicient current fiow for resetting the circuit. But when two or more arms are shorted together, the parallel resistance decreases to allow the circuit to reset, and said circuit remains in reset until the short is removed. When the short is removed, the circuit returns to normal operations. The pressing of buttons will not affect the circuit as long as it remains in reset due to the short. The resistors R35a and R41a are of slightly lower and slightly higher respective values than the other said resistors to compensate for temperatures changes. Presence of the supply voltage at junction point 46 is also admitted to the base of transistor Q1 via resistor R11. The application of this voltage turns transistor Q1 on to enable transistor Q1 to function as a holding or latching circuit for transistor Q3 after button switch S7 has been released. Consequently, transistor Q1 acts as a switch and enables the base of transistor Q3 to be driven or held in the on condition.
Resistor R3 and capacitor C2 function as a pulse speedup circuit for the first flip-flop stage, and because the value of R3 is very large, C2 and R3 also prevent an undesirable discharge of C1 through the base-emitter junction of Q3.
When transistor Q3 is on, it acts as a short circuit and the voltage drop across transistor Q3 is kept to an absolute minimum. For this purpose, resistor R12 is made five or six times larger than resistor R10, for instance, and the same is true in the next stage and in all succeeding stages.
The step switch SS2 has its arm connected to position No. 3 and consequently power will be admitted through the step switch only when the button switch S3 is depressed. The -12 volts supply will be fed through resistor R14 to the base of transistor Q4 turning same on. This action causes the first flip-flop stage to fiip turning off transistor Q5 when transistor Q4 is turned on. It will be noted that the emitter of transistor Q4 is connected to the return line 26 via the transistor Q3. But since, at that time transistor Q3 is on and appears as a short circuit, no substantial load is placed on the transistor Q4.
In order to actuate the next stage of the circuit, which is the second flip-flop stage 70, the button switch S9 must be depressed since the arm 82 of step switch SS3 is placed on position No. 9. Thus, power is provided via resistor R21 to the base of transistor Q6 and causes the second flipfiop 70 to flip turning oif transistor Q7 and turning transistor Q6 on. Transistor Q6 can only come on or be saturated if transistors Q4 and Q3 are already in saturation. It will be evident that the emitter of transistor Q6 interconnects through transistors Q4 and Q3 to line 26, the return.
In the event that one of the transistors Q3 or Q4 is not conducting or for any reason transistor Q6 cannot be turned on, the diode CR2 provides a return or by-pass for the voltage applied through the resistor R21 to line 90. A signal appearing on line 90 is admitted through the diode CR1 to the base of transistor Q2 which, if turned on, will reset the entire circuit by turning off transistor Q3 and thereby opening the path for all of the first transistors in the succeeding flip-flop stages to the return. Consequently, none of the transistors Q4, Q6 Q12 will be able to see the return side of the line.
The purpose of resistor R4 is to act as a current limiter to raise the threshold of transistor Q2, since some current will always be leaking through the various diodes whenever the power supply is applied across the associated resistors.
The process described is repeated for step switches SS4, 5 and 6. As will be evident, the proper combination and the proper sequence is as follows, the button switches S7, S3, S9, S6, S10 and S1 must be depressed in that exact se quence to obtain an output from transistor Q13. It will be respectfully noted that the output from transistor Q13 is derived by this transistor being turned off when the transistor Q12 is turned on. The turn off of transistor Q13 applies a signal to the base of transistor Q14 to turn same on. This transistor acts as a buffer stage since high current is necessary to operate the coil of relay or solenoid 120. Transistor Q14 provides an output via its emitter of approximately 60 ma. to serve as a base drive for the switching transistor Q15 which is coupled in series with the relay or solenoid 120. Line 125 provides the collector voltage for transistor Q15 which is taken from terminal Z. As noted previously, resistor R53 functions as a current limiter to limit the current in line 125 to approximately 350 ma.
. As will be evident, depressing any of the button switches out of proper sequence, or depressing a wrong button switch as, for example, button switches S4, S2, S8 and S5, will result in transistor Q2 coming on and resetting the cricuitry.
As will be evident, the combination is set by positioning the various step switches SS1 to S810. Although the preferred embodiment of the present invention, as portrayed in the drawings, has been shown and described in terms of a six digit combination, it will be respectively appreciated that the number of digits in the combination can be varied by simply by-passing one or more of the flipfiop stages 70 starting with the last stage and working backward. Thus, for example, a three digit combination can be readily achieved by connecting R49 to the collector of transistor Q7.
The function of the time reset circuit provided by potentiometer R1 and capacitor C1 is to limit the time available to work the combination. In the preferred embodiment illustrated for a six digit combination, approximately 15 seconds or any other interval like 5, 7 or 10 seconds can be provided to energize relay or solenoid and to provide ample time for ingress before the circuitry will automatically reset itself. Resetting occurs whenever capacitor C1 discharges to a predetermined value. Consequently, resetting is generally correlated with the time allotted for working the combination which, for a six digit combination, is presumed, in the preferred embodiment, to be approximately 5 seconds and the time necessary for ingress. For a smaller combination, such as three or four digits, it would probably be desirable to have a reset time of 6 to 10 seconds. This feature of the invention provides additional protection in that an unauthorized person who is attempting to tamper with the combination in an effort to find a way to work same, will find it quite frustrating since the apparatus will reset itself at relatively short intervals.
It is pointed out that this electronic combination device can be used to initiate the operation of any mechanical device, lock, motor or equipment.
Although the present invention has been shown and described in terms of a preferred embodiment, nevertheless, changes and modifications will occur to those skilled in the art from a knowledge of the concepts taught herein. Such changes and modifications as are obvious are deemed to come within the purview of the invention.
1. An electronic combination lock comprising a latch actuator, a power supply, a control circuit for selectively feeding operating power from said supply to the latch actuator, said control circuit comprising a plurality of semiconductor bistable devices each having an output electrode, an input electrode, and a control electrode, said bistable devices being in one conductive state and arranged in cascade such that the output electrode of one bistable device is coupled to the input electrode of the next succeeding bistable device, each said bistable device being operable to the other conduction state only when the next preceding bistable device is in the other conduction state and an operating signal is received by the respective control electrode, each bistable device returning to said one conduction state whenever the next preceding bistable device returns to said one conduction state, a bistable first stage having its output connected to the input electrode of the first bistable device and normally feeding a disabling voltage thereto to maintain said first bistable device in said one conduction state, said first stage having a control electrode and at least one reset electrode, a plurality of operable button switches coupled to said power supply for passing signals whenever the button switches are operated, adjustable coupling means for connecting different ones of a group of said buttons to different ones of said control electrodes and for connecting one of said button switches to the control electrode of said first stage so that whenever the preceding first stage or bistable device changes to the other conduction state and a signal is received by the next control electrode associated with a particular button switch, the associated bistable device changes state, a power switch coupled to the power supply and the last semiconductor bistable device and the latch actuator for operating the latch actuator in response to said last bistable device changing states, first reset means connected from each bistable device to one reset electrode of said first stage to reset the same to its normal output condition whenever a bistable device control electrode receives a signal from its button switch and its next preceding bistable device is in said one conduction state to assure the actuator operation only when said button switches are operated in the sequence determined by the setting of said coupling means.
2. A lock as set forth in claim 1 wherein the number of button switches is greater than the number of bistable devices, second reset means coupled from said coupling means and those button switches not associated with bistable devices to one reset electrode of said first stage to reset the same to its normal output condition whenever one of those button switches is operated to assure the actuator operation only when all buttons not designated for the lock combination are left undepressed.
3. A lock as set forth in claim 1 wherein third reset means is coupled to said first stage which senses when the first stage goes to the other conduction state and controls 8 the first stage so that it returns to the first conduction stateafter a predetermined time period has lapsed thus assuring the actuator operation only in the event the proper sequence of buttons is actuated within said time period.
4. A lock as set forth in claim 1 wherein each said bistable devices include means connected to said first stage for resetting the same whenever a signal is received at the same time by two or more control electrodes associated with the bistable devices.
5. A lock as set forth in claim 1 wherein each semiconductor bistable device comprises a two transistor flipflop circuit with the control electrode coupled to the base of one of the transistors, the input and output electrodes of the semiconductor bistable device comprising the emitter or collector of one of the transistors such that the current path of said one transistor is connected through one of the transistors of the preceding stage.
6. A lock as set forth in claim 1 wherein said power switch comprises a power transistor controlled by the last semiconductor bistable device.
7. A lock as set forth in claim 2 wherein said coupling means comprises a plurality of step switches each having a plurality of contacts and a contact arm, each button switch connected to a different contact of each step switch and each arm of a step switch associated with the first stage or a semiconductor bistable device being coupled to the control electrode thereof, the arms of the remaining step switches coupled to said second means.
8. A lock as set forth in claim 3 wherein said first stage comprises a two transistor flip-flop circuit and said third reset means comprises a storage circuit which is charged when the output transistor assumes the other conduction state and said storage circuit thereafter discharging at a predetermined rate, a bias control device coupled to and controlled by said storage circuit for switching the output transistor to the first conduction state when the remaining charge of said storage device drops below a predetermined level.
References Cited by the Examiner UNITED STATES PATENTS 2,561,076 7/1951 'Tassin 317---l34 2,843,843 7/1958 Davis 340--276 2,855,588 10/1958 Allen 340-276 3,192,448 6/1965 Hevenor 317-134 3,234,516 2/1966 Miller 340-164 3,242,388 3/1966 Tellerman 317134 MILTON O. HIRSHFIELD, Primary Examiner.
I. A. SILVERMAN, Assistant Examiner.
|Cited Patent||Filing date||Publication date||Applicant||Title|
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|US3192448 *||Feb 6, 1961||Jun 29, 1965||Hevenor John C||Keyless electric lock|
|US3234516 *||Sep 28, 1962||Feb 8, 1966||Security Controls Inc||Coded electric load controller|
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|Citing Patent||Filing date||Publication date||Applicant||Title|
|US3407346 *||Oct 14, 1965||Oct 22, 1968||Irvin W. Hunter||Electric sequential combination mechanism|
|US3441808 *||Oct 23, 1965||Apr 29, 1969||Crane Charles V||Electronic door lock and supervisory system|
|US3513357 *||Sep 13, 1967||May 19, 1970||Dittmore Maylin H||Door lock|
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|US3710136 *||Jan 27, 1971||Jan 9, 1973||Smiths Industries Ltd||Electronic combination lock|
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|U.S. Classification||361/172, 70/278.1, 307/40|
|Jan 24, 1985||AS||Assignment|
Owner name: PACIFIC SCIENTIFIC COMPANY
Free format text: MERGER;ASSIGNOR:PACIFIC SCIENTIFIC INSTRUMENTS COMPANY;REEL/FRAME:004376/0149
Effective date: 19850521
|Sep 3, 1981||AS||Assignment|
Owner name: NEOTEC CORPORATION, 2431 LINDEN LANE, SILVER SPRIN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:PACIFIC SCIENTIFIC INSTRUMENT COMPANY;REEL/FRAME:003911/0936
Owner name: NEOTEC CORPORATION, 2431 LINDEN LANE,SILVER SPRING
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:NEOTEC ELECTRONICS,INC.;REEL/FRAME:003903/0505
Effective date: 19810903
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PACIFIC SCIENTIFIC INSTRUMENT COMPANY;REEL/FRAME:003911/0936
Owner name: NEOTEC CORPORATION, A CORP. OF DE., MARYLAND
|Aug 26, 1981||AS||Assignment|
Owner name: NEOTEC ELECTRONICS, INC., 6110 EXECUTIVE BLVD., RO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:HALLIBURTON COMPANY A CORP. OF DE;REEL/FRAME:003902/0929
Effective date: 19810821