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Publication numberUS3378920 A
Publication typeGrant
Publication dateApr 23, 1968
Filing dateJan 26, 1966
Priority dateJan 26, 1966
Publication numberUS 3378920 A, US 3378920A, US-A-3378920, US3378920 A, US3378920A
InventorsPeter F Cone
Original AssigneeAir Force Usa
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method for producing an interconnection matrix
US 3378920 A
Abstract  available in
Previous page
Next page
Claims  available in
Description  (OCR text may contain errors)

April 23, 1968 P. F. CONE 3,373,920

METHOD FOR PRODUCING AN INTERCONNECTION MATRIX Filed Jan. 26. 1966 W INVENTOR. PETE/Y r. Cfd/VE United States Patent 3,378,920 METHOD FOR PRODUCING AN INTERCONNECTIGN MATRIX Peter F. Cone, Bedford, Mass., assignor to the United States of America as represented by the Secretary of the Air Force Filed Jan. 26, 1966, Ser. No. 523,517 2 Claims. (Cl. 29625) ABSTRACT OF THE DISCLOSURE This invention relates generally to electronic circuit interconnection matrixes and more particularly to a layered matrix board wherein all conductors are electrically connected and desired interconnection patterns are made by electrically eliminating undesired connections.

When a series of sets of conductors are orthogonally arranged, there is a mathematical limit to the number of connections for joining various pairs of wires from the sets of wires. Each intersection is a possible connection between the wires running in one direction to the wires in the orthogonally related direction.

Generally, interconnection between orthogonally related conductors has been performed by means of suitable connecting points around the edges of a board with the required interconnection pattern having been previously printed on board, for example, by printed circuit techniques. This method suffers from the disadvantage of not allowing all of the desired connections with one board. For example, the edge connection does not allow for a crossover of wires due to the co-planar relationship of the conductors, and change of the interconnection pattern is both lengthy and expensive.

The preformed interconnection matrix board of this invention has one set of parallel conductors formed on a base board and a second set of conducting lines at right angles to the first set of conductors with insulating material sandwiched therebetween. Suitable contact regions are formed at the ends of the conducting lines during the processing. The key to forming the interconnection be tween particular pairs of orthogonally related conductors is achieved by applying a fusible material between the conductors of each pair and electrically eliminating the fusible material between pairs where a connection is not desired.

Accordingly, it is a primary object of this invention to provide a method for producing a preformed interconnection board which by means of electrical break down of fusible material to eliminate undesired connections allows for any desired interconnection pattern between conduct-ors.

It is another object of this invention to provide a method which enables a predetermined connection arrangement between generally orthogonally related conductors.

It is still another object of this invention to provide a method for producing an interconnection matrix wherein fusible material between layers of conductors is designed to have a break down rating which would allow for elimination of interconnections between superposed conductors which are not desired while not interfering with normal circuitry capacity.

It is a further object of this invention to provide a method for producing an interconnection matrix board which allows ofr easy change of the wiring pattern.

It is a still further object of this invention to provide a method of producing a printed wiring board which is capable of being programmed by a computer.

Another object of this invention involves a process for the production of electrical circuit assemblies which utilizes printed circuit techniques with conventional, currently available materials that lend themselves to stand ard mass production techniques.

These and other advantages, features and objects of the invention will become more apparent from the following description taken in connection with the illustrative embodiments in the accompanying drawings, wherein:

FIGURE 1 is a schematic representation of the prior art type of end connections;

FIGURE 2 is a schematic representation of the interconnection matrix board of this invention; and

FIGURE 3 is an end view, partly in section, of the structure of FIGURE 2.

In the prior art a matrix of wires p and q, which are orthogonally related and which lie in the same plane on the printing wiring boards 10, are interconnected by means of a printed circuit 11. Printed conductors interconnecting the conductors p and q around the edges of the interconnecting matrix board 10 are shown in FIGURE 1. There are p-q ways of joining a set of p wires to a set of q wires with a maximum of (p+q1) valid connections. With the board shown in FIGURE 1, wire p can not be connected with wire r1 This difliculty is overcome by means of the arrangement of this invention illustrated in FIG- URE 2 and also by the structure described in my copending application Serial No. 523,515, filed on even date herewith and titled Interconnection Matrix, however, the instant invention provides for a lower intercapacity with greater reliability.

The matrix in FIGURE 2 comprises a substrate 20 which may be made of almost any conventional material utilized in circuit boards, e.g., Teflon, glass, ceramics, or epoxy board. A first layer of p wires is either deposited chemically or vacuum deposited onto the substrate or bonded thereto, and then etched into lines using standard, printed circuit techniques. The material used for the conductors most commonly would be copper or aluminum.

The second layer, overlying the p wires and the substrate, comprises an insulating layer 22 of glass, alumina or a silicon oxide deposited by bonding, chemically or by vacuum evaporation. This layer, if vacuum deposited, is applied with a mask in order to allow for holes 24 therethrough. When bonding is utilized as the fabrication method, the holes would be preformed in the insulating material 22.

Within the bores 24, which occur at the desired junction between orthogonally related conductors, a fusible material 26, conventionally used in the fure art, which would have a rating or capacity greater than that required for the circuit board, would provide a connection with the conductor p.

The third layer applied to the board 20 com-prises a set of q wires which are orthogonally related to the previously deposited set of p wires. The manner of application and the materials utilized in this last layer would be the same as that described with respect to the p wires. The orthogonal relationship is not a requirement; however, for computer programming of the desired connection, the orthogonal relationship is admirably suited.

At this stage there are four layers forming the matrix board comprising the substrate 20, the set of p wires, the insulation and the q wires. All lines are connected with 3 each other by means of fusible material 26 and suitable contact regions, illustrated generally at 28, are provided for both the p and q conductors.

In order to create the desired interconnection pattern, the undesired connections would have electrical power applied to the wires thereof and a high current passed through the circuit in order to blow the fuse element 26.

Thus, there has been described a preformed interconnection board which allows for any possible connection arrangement between conductors and also which allows for ready change of wiring patterns. The resultant structure is exceptionally reliable and has a very low intercapacity.

Although the invention has been described with reference to a particular embodiment, it will be understood to those skilled in the art that the invention is capable of a variety of alternative embodiments within the spirit and scope of the appended claims.

I claim: 1. A method for producing an interconnection matrix board having any desired interconnection pattern between crossed series of conductors comprising the sequential step of,

applying a series of generally parallel conductors on a matrix board by a printed circuit technique,

applying an insulating layer over a portion of said conductors while leaving holes in said layer exposing portions of said conductors.

applying a conductive fusible material having a breakdown rating which would be greater than the circuit capacity of the matrix board and less than the breakdown rating of any conductors applied to the board on said conductors in the holes and filling the same,

applying a second series of generally parallel conductors on said matrix board, the conductors of said second series of conductors crossing the conductors of said first-mentioned series of conductors at the holes in said insulating layer with said fusible material forming interconnections between conductors of said series of conductors, and

causing said fusible material to break down between conductors of each series which are not to be interconnected.

2. A method as defined in claim 1 wherein said causing of said fusible material to break down is performed by applying a high current through conductors for which no interconnection is desired.

References Cited UNITED STATES PATENTS 2,399,753 5/ 1946 McLarn. 3,028,659 4/1962 Chow et al. 3,226,802 1/ 1966 Goodwin et al.

DARRELL L. CLAY, Primary Examiner.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US2399753 *Mar 13, 1944May 7, 1946Int Standard Electric CorpMultiple connections for electrical apparatus
US3028659 *Dec 27, 1957Apr 10, 1962Bosch Arma CorpStorage matrix
US3226802 *Oct 8, 1959Jan 4, 1966Acf Ind IncMethod of making a matrix board system
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US3491197 *Dec 30, 1966Jan 20, 1970Texas Instruments IncUniversal printed circuit board
US3528048 *Jul 6, 1967Sep 8, 1970IbmMethod of constructing printed circuits for subsequent completion or deletion
US3634600 *Jul 22, 1969Jan 11, 1972Ceramic Metal Systems IncCeramic package
US3699395 *Jan 2, 1970Oct 17, 1972Rca CorpSemiconductor devices including fusible elements
US3747175 *Mar 29, 1971Jul 24, 1973Sony CorpGaseous glow indicator tube formed on a substrate with a plurality of insulating layers
US3816711 *Dec 11, 1972Jun 11, 1974W BlissDecoding apparatus and system for an electrically encoded card
US3818252 *Dec 20, 1972Jun 18, 1974Hitachi LtdUniversal logical integrated circuit
US3876865 *Jun 21, 1974Apr 8, 1975William W BlissElectrical verification and identification system
US4029945 *Aug 27, 1975Jun 14, 1977Stanley Electric Co., Ltd.Card and card reader apparatus therefor
US4376927 *May 28, 1981Mar 15, 1983Mcgalliard James DPrinted circuit fuse assembly
US4652974 *Oct 28, 1985Mar 24, 1987International Business Machines CorporationMethod and structure for effecting engineering changes in a multiple device module package
US4670813 *Nov 29, 1985Jun 2, 1987The Perkin-Elmer CorporationProgrammable lamp plug
US4689023 *Aug 27, 1985Aug 25, 1987The Superior Electric CompanyProgrammable electrical connector
US4831725 *Jun 10, 1988May 23, 1989International Business Machines CorporationGlobal wiring by removal of redundant paths
US4974048 *Mar 10, 1989Nov 27, 1990The Boeing CompanyIntegrated circuit having reroutable conductive paths
US5165166 *Sep 9, 1991Nov 24, 1992Microelectronics And Computer Technology CorporationMethod of making a customizable circuitry
US5247735 *Dec 18, 1991Sep 28, 1993International Business Machines CorporationElectrical wire deletion
US5438166 *Nov 23, 1992Aug 1, 1995Microelectronics And Computer Technology CorporationCustomizable circuitry
US5573409 *Nov 17, 1991Nov 12, 1996Itt CorporationInterconnector
US6059917 *Dec 6, 1996May 9, 2000Texas Instruments IncorporatedControl of parallelism during semiconductor die attach
US7179520 *Dec 23, 2004Feb 20, 2007Seiko Epson CorporationCircuit substrate, electro-optic device and electronic equipment
US8297514Aug 10, 2006Oct 30, 2012Novalia LimitedElectronic tag
US20050161832 *Dec 23, 2004Jul 28, 2005Seiko Epson CorporationCircuit substrate, electro-optic device and electronic equipment
US20090294537 *Aug 10, 2006Dec 3, 2009Kate Jessie StoneElectronic Tag
U.S. Classification29/847, 235/488, 235/492, 337/142, 439/43, 439/516, 235/441, 174/254
International ClassificationH05K3/40, H05K1/00
Cooperative ClassificationH05K2203/175, H05K1/0293, H05K1/0289, H05K3/4038, H05K2203/1115, H05K2201/10181
European ClassificationH05K1/02M8, H05K1/02M2B, H05K3/40D