Publication number | US3453423 A |

Publication type | Grant |

Publication date | Jul 1, 1969 |

Filing date | Mar 16, 1966 |

Priority date | Mar 16, 1966 |

Publication number | US 3453423 A, US 3453423A, US-A-3453423, US3453423 A, US3453423A |

Inventors | Ma Peter Pu-Yuan |

Original Assignee | Atomic Energy Commission |

Export Citation | BiBTeX, EndNote, RefMan |

Patent Citations (3), Referenced by (2), Classifications (6) | |

External Links: USPTO, USPTO Assignment, Espacenet | |

US 3453423 A

Abstract available in

Claims available in

Description (OCR text may contain errors)

Y 1969 PETER PU-YUAN MA 23 FOUR QUADRANT LOGARLTHMIC MULTIPLIER FOR TIME-DEP ENDENT SIGNALS Filed March 16, 1966 F /'g. 5 INVENTOR.

PETER PU-YUAN MA BY United States Patent 01 Efice 3,453,423 Patented July 1, 1969 3,453,423 FOUR QUADRANT LOGARITHMIC MULTIPLIER FOR TIME-DEPENDENT SIGNALS Peter Pu-Yuan Ma, Hsinchu, Taiwan, China, assignor to the United States of America as represented by the United States Atomic Energy Commission Filed Mar. 16, 1966, Ser. No. 536,590

Int. Cl. G06g 7/16 US. Cl. 235-194 3 Claims ABSTRACT OF THE DISCLOSURE variables and feedback to provide a result which is proportional to the product of the variables. A differential amplifier receives the outputs from the logarithmic amplifiersto produce the product.

The present invention relates to a four quadrant logarithmic multiplier and more particularly, to a four quadrant logarithmic multiplier for obtaining the instantaneous product of time-dependent signals.

The invention described herein was made in the course of, or under a contract with the U.S. Atomic Energy Commission.

The use of logarithms to obtain the product and division of parameters is a common approach because it involves merely the addition or subtraction of the logarithms for the input values. There is on problem, however, which arises and is especially difficult to overcome when electronic apparatus is devised to carry out these functions. When it is necessary to process values at or approaching zero or which are negative, ordinary techniques for using logarithmic values are not applicable. Previous efforts to produce apparatus capable of receiving both positive and negative inputs have met with some success; however, when the time-dependent input signals come close to zero, substantial circuit inaccuracies arise. The present invention has to do with improved electronic circuitry for overcoming the difliculty of dealing with negative parameters and thereby enabling true four quadrant multiplication to occur in a logarithmic circuit, and, additionally, maintaining circuit accuracy when input parameters approach zero.

It is thus a first object of this invention to provide a logarithmic multiplier operable in all four quadrants.

A further object of the. invention is 'to provide logarithmic multiplier circuits with improved accuracy.

Still another object is the provision of logarithmic multiplier apparatus capable of receiving input signals close to zero withoutsacrifice in accuracy.

Other objects and advantages of this invention will hereinafter become readily apparent from the following description of preferred embodiments of this invention taken with the accompanying drawing in which:

FIG. 1 illustrates a basic logarithmic multiplier circuit;

FIG. 2 shows a logarithmic multiplier circuit incorporating the principles of this invention;

FIG. 3 shows a logarithmic divider embodying this invention;

FIG. 4 illustrates the'invention utilized for squaring a time function; and

FIG. 5 demonstrates use of the inventive concept to obtain the square root of an input signal.

Referring to FIG. 1, there is shown a logarithmic multiplier circuit of more or less conventional design consisting of logarithmic amplifiers L L and 1. and

a balanced differential amplifier D Amplifier D, adjusts itself to produce an output signal such that the sum of the inputs will be zero at all times. Such a device is 'Well known in the art. Amplifiers L L and L each produce an output which is proportional to the logarithm of its input signal at any given instant, such amplifiers also being well known in the art. Amplifiers L and L are supplied with input signals A and B, respectively, which represent the time-dependent values to be multiplied. The outputs of these amplifiers are passed through a pair of resistors R and R respectively, then are combined or added and supplied as one of the inputs to differetnial amplifier D The output signal C from amplifier D is fed back in a feedback loop as the input to logarithmic amplifier L while the output of the latter is passed by way of resistor R to amplifier D as the second input. Since the sum of the inputs to amplifier D approaches zero, that is, the output of D is adjusted to a value such that the sum of the inputs is zero, it is readily apparent that its two inputs are equal to each other, or, log C is equal to the sum log A+log B, so that C represents or is proportional to the product AB.

In the basic arrangement illustrated in FIG. 1, provision can and has been made to accommodate one or both negative signal inputs, however, substantial inaccuracies arise as the values approach zero. The arrangement M shown in FIG. 2, a preferred form of this invention, embodies featuers which avoid this difficulty. This arrangement consists of a parallel arrangement of logarithmic amplifiers L L L and L and a balanced dilferential amplifier D Amplifiers L annd L receive the input signals A and B to be multiplied. Added to these time-dependent signals at the inputs to amplifiers L and L is a DC bias current source signal S which is a little larger than the largest contemplated peak of signals A or B, so that the inputs to log amplifiers L and L as well as amplifiers L and L will never be caused to go negative or near zero.

The outputs of amplifiers L and L are passed through resistors R and R respectively, and added together prior to being supplied as one input to differential amplifier D Log amplifier L receives as its input the signal S while amplifier L receives as its input the sum total of (A+B+S+M). Signal M is the output of differential amplifier D The log outputs of amplifiers L and L; are passed through resistors R and R combined and thus fed as the second input to differential amplifier D From the discussion below it will be seen that the output of amplifier D will be AB/S, or proportional to the product of the time-dependent variables A and B.

As an explanation for the foregoing, consider the outputs of log amplifiers L L L and L to be E E E and E respectively. Thus, a

( 1= d- 2= g E =log S Because of the negative feed back loop through amplifier L as described earlier, the system will align itself so that the sum of the inputs to balanced amplifier D will be zero:

E |log S log (A +S) +log (B+S) 3 Hence, the input to the log amplifier L is 7 I (AB/S+A+B+S) By furnishing the signals A+B+S separately to the input of amplifier L as just described, it is readily apparent that the output of amplifier would be AB/S. Since S is a constant value signal, and may be considered a scaling factor, the output of the system as represented by the output of amplifier D is proportional to the product of A and B. By the arrangement just described, it is readily apparent that with proper selection of scaling factor S, all problems arising out of negative values of A and B, or values thereof being close to zero, have been eliminated so that there is no decrease in the accuracy of the system when the input time-dependent signals approach zero.

The arrangement described above can be readily adapted to the operation of division. Referring to FIG. 3, there is illustrated a multiplier circuit M shown in block form representing the complete circuit illustrated in FIG. 2. The phantom lines surrounding circuit M designate the extent of the arrangement shown in FIG. 2. In the arrangement of FIG. 3, it is desired to produce a result proportional to H/F where H and F are time-dependent signals. F and G in FIG. 3 are equivalent to A and B, respectively, in FIG. 2. Multiplier circuit M is connected to deliver its output to balanced differential amplifier D while the second input to the latter is signal H. Multiplier M is supplied with signals F and the output of amplifier D designaed as G and the scaling factor S. From the discussion of FIG. 2, it is apparent that the output of multiplier M is FG/S which is equal to H so that by simple manipulation of the equation the output G of the system is SH /F, or a signal proportional to H divided by F.

In a similar fashion, the invention can be adapted to the squaring of a function, as shown in FIG. 4. Multiplier M is shown with signal I supplied as botht inputs with the final result W=] /S.

Obtaining the square root of a time function may be accomplished by the arrangement of FIG. where is shown multiplier M and a balanced differential amplifier D supplied with the inputs L and V where L is the time function to be operated upon and V is the output of multiplier M The output of amplifier D which is the output T of the system, is also supplied as input to multiplier M in the manner of FIG. 4 so that the output V of multiplier M is T /S. Hence,

It is thus seen that there has been provided an improved logarithmic arrangement for the multiplication and division of time-dependent signals capable of functioning in all four quadrants and without sacrificing accuracy when the variable input signals approach zero. In addition, it is seen that the arrangements described are simple in construction and thereby do not require the expensive and highly sophisticated arrangements which heretofore have been or would be required to overcome the previously mentioned difficulties involved in logarithmic apparatus.

While several preferred embodiments of the invention have been described, it is understood that many changes thereof may be made without departing from the principles of this invention.

What is claimed is;

1. A four quadrant logarithmic multiplier of first and second variables comprising:

(a) differential amplifier means with first and second inputs having a feedback loop operating to adjust 5 its output to such a value that the sum of said inputs is equal to zero;

(b) means for producing a first logarithm value for the sum of said first variable and a scaling factor whose value is larger than each of said first and second variables;

(c) means for producing a second logarithmic value for the sum of said second variable and said scaling factor;

((1) means for delivering a signal value proportional to the sum of said first and second logarithmic values as the first input to said amplifier means;

(e) means for producing a third logarithmic value for 1 said scaling factor;

( f) means for producing a fourth logarithmic value for the sum of the first variable, second variable,

I said scaling factor, and the output of said amplifier means; and

(g) means for delivering the sum of said third and fourth logarithmic values as the second input to said amplifier means, the output of the latter being proportional to the product of said first and second variables.

2. Four quadrant logarithmic apparatus for dividing a first variable by a second variable comprising:

(a) differential amplifier means with first and second inputs having a feedback loop operating to adjust its output to such a value that the sum of said inputs equals zero;

(b) means for supplying said first variable as the first input to said amplifier means;

(0) multiplier means for producing the product of said second variable and the output of said amplifier means; and

(d) means for delivering the output of said multiplier means as the second input to said amplifier means, the output of said amplifier means being proportional to the quotient of said first variable divided by said second variable.

3. 'Four quadrant logarithmic apparatus for obtaining the square root of a time function variable comprising:

(a) differential amplifier means with first and second inputs operating to adjust its output to such a value that the sum of said inputs equals zero;

(b) means for supplying said variable as the first input to said amplifier means;

(c) multiplier means for squaring the output of said amplifier means; and ((1) means for delivering the output of said multiplier means as the second input to said amplifier means,

the output of the latter being proportional to the square root of said variable.

References Cited UNITED STATES PATENTS 2,920,828 1/1960 Davis 235-494 3,000,565 9/1961 Wilkinson 235-194 x 3,039,694 6/1962 Hunt 23s 194

Patent Citations

Cited Patent | Filing date | Publication date | Applicant | Title |
---|---|---|---|---|

US2920828 * | Sep 16, 1955 | Jan 12, 1960 | Davis Billy E | Four quadrant computer |

US3000565 * | Apr 10, 1957 | Sep 19, 1961 | Wilkinson Robert H | Circuits for obtaining four quadrant analogue multiplication |

US3039694 * | Nov 19, 1958 | Jun 19, 1962 | Gen Precision Inc | Four quadrant multiplier |

Referenced by

Citing Patent | Filing date | Publication date | Applicant | Title |
---|---|---|---|---|

US3736415 * | Sep 14, 1971 | May 29, 1973 | Ferranti Ltd | Electric analogue calculating circuits |

US3940603 * | Jul 2, 1974 | Feb 24, 1976 | Smith John I | Four quadrant multiplying divider using three log circuits |

Classifications

U.S. Classification | 708/843, 708/807 |

International Classification | G06G7/16, G06G7/00 |

Cooperative Classification | G06G7/16 |

European Classification | G06G7/16 |

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