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Publication numberUS3471848 A
Publication typeGrant
Publication dateOct 7, 1969
Filing dateSep 20, 1968
Priority dateSep 30, 1963
Also published asUS3305841, US3609443
Publication numberUS 3471848 A, US 3471848A, US-A-3471848, US3471848 A, US3471848A
InventorsManber Solomon
Original AssigneeAlphanumeric Inc
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Pattern generator
US 3471848 A
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Description  (OCR text may contain errors)

Oct. 7, 1969 s. MANBER 3,471,848

PATTERN GENERATOR Original Filed Aug. 15, 1966 3 Sheets-Sheet 1 INVENTOR.

Solomon Manber FIG. 1 BY ATTORNEY Oct. 7, 1969 Original Filed Aug. 15, 1966 3 Sheets-Sheet 2 sRR' R2 F|G.2A STEP STEP PULSE GENERAToR --ME GRY KV SPG Twvs )N v MM A 25m 04-COUNTERC A GAGTE couNTER REGISTER S Rcc NcsR A A A A PLS MM E D GATE PULSE D64 GENERATOR FUNCTION DECODER E P65 5;

* I sue 1 1 T MOD SRt, RsR MOD RsR ML CfiEQTER s GATEs SELECTIVE ADDN/ COUNTER REPEA slGN ADDER- DECODER REGISTER REGISTER SUBTRACTOR K ssR s R SIGN A s ucc i (8) -ORES COLUMN SEGMENT sToRAGE SWITCH g;

TAR 3 1 t f TBR y M 0 sue s R ML Evs EVS-n- A-REGIsTER AR B-REGISTER BR R2 L RZ-DF s4 7 e4 FARo--1 FBR FAR FER I I COLUMN sEGMENT ADDER-SUBTRACTOR (5) DATA SWITCH cs0 SWITCH Ass AUG 1 (8) o--4 SD '-OSDD UAB U C Mo vsRR so AB oEcooER couNTER i AB& (3)

SEGMENT 0EQ- DATA GATE -RZ 5 couNTER El soc CL Evs Oct. 7, 1969 s. MANB-ER 3,471,848

PATTERN GENERATOR Original Filed Aug. 15. 1966 3 Sheets-Sheet 5 EVS s s A I so ENT COMPARATOR COUNTER J CVERT s ggm g CEC CEK SCAN RTK CEN FIF. DEQ -1-' %L 1 V S A GATE GATE VIDEO I COUNTER i g lg J A I OSCILLATOR 1 VIDEO VERTICAL DRIVE DEFLECTION CIRCUITS CONTROL voc VDFC HORIZONTAL ACCEL. DEFLECTION VOLTAGE CONTROL SOURCE HDC AVS United States Patent M 3,471,848 PATTERN GENERATOR Solomon Mauber, Sands Point, N.Y., assignor to Alphanumeric, Incorporated, Hicksville, N.Y., a corporation of Delaware Continuation of application Ser. No. 572,609, Aug. 15, 1966. This application Sept. 20, 1968, Ser. No. 784,972 Int. Cl. G08!) 23/00 US. Cl. 340324 17 Claims ABSTRACT OF THE DISCLOSURE A cathode ray tube symbol generation system wherein the beam of the CRT is scanned in a raster over the symbol display area and is selectively blanked and unblanked in response to coded signals defining the beginning and end points of the unblanked segment for each scan of the raster. The addresses of the beginning and end points of the segment of the first scan are defined in absolute terms and the addresses of the segments of the subsequent scans are obtained by incrementing the addresses of the segment of the first scan.

This is a continuation of application No. 572,609, filed Aug. 15, 1966.

This invention is related to pattern generators and more particularly to the generation at a very high speed of high-quality patterns such as characters on an electromagnetic radiation sensitive medium.

Pattern generators have many applications such as display devices, computer output devices, etc. Of these ap plications the ones which produce the greatest amount of end result output are character generators used in the graphic arts and printing fields. Although these fields are very old the best automated line casting machines available today are electromechanical devices which can produce fifteen to twenty characters per second.

In order to increase the rate of generating characters, there have been attempts to utilize light beams and photosensitive films. Some early approaches were to use the controlled trace of a cathode ray tube which was driven by figure eight bar generators which produced intelligible symbols by appropriate combinations of barlike elements. However, such characters in no way approached the quality of the characters produced by conventional metal type slugs. Vector generators were also employed to drive the cathode ray tube beams with a slight improvement in quality.

About fifteen years ago a cathode ray tube was inr troduced which included a stencil of a plurality of characters equivalent to a degenerate type font. The electron beam was first aimed on the region of the stencil having the outline of the character selected for output and further deflection circuits deflected the beam to the desired position on the face of the tube. Although the quality of the output characters greatly improved, only one type font was available per tube. In addition, the circuits and the stencils are relatively expensive.

Other approaches included a multicharacter stencil having controllably ignitible light sources behind each character outline with optical focusing to direct the image to a particular portion of the output media. However, the proposal sulfered from all the defects of the cathode ray tube-stencil systems and was even more expensive.

A further approach included the video scanning of a 3,471,848 Patented Oct. 7, 1969 stencil and using the video signal to intensity modulate the beam of a cathode ray tube. Such a system demanded very precisely engraved stencils which are prohibitively expensive to initially fabricate and to reproduce.

The field has tried dispensing with mechanical stencils and has tried using pre-wired control circuits and magnetic core matrices, one per character, to generate patterns of signals to intensity modulate a cathode ray tube beam. However, the pre-wired control circuits and core matrices are exorbitantly expensive when high-quality characters are required.

An improvement on these systems is disclosed in US. Patent No. 3,165,045, for Data Processing System wherein each character is represented by a plurality two-valued (black or white) elements in a matrix array. A storage means stores the representations of the characters as bits, with one bit per element. The bits are fed serially to a light source which scans a photographic medium. The bits intensity modulate the light source. Since the bits are stored on an addressable magnetic drum, the disadvantages of the pre-wired matrix are not present. However, this system is merely an electromagnet version of a conventional dot printer. Such printers are notorious for their inability to produce graphic arts quality characters. Such quality requires a very finely divided matrix array, for example an array of columns and rows, or 7000 elements per character. Therefore, it is necessary to store 7000 bits per character.

In order to minimize the number of stored bits per character, there has been disclosed in application Ser. No. 312,405, for a Pattern Generator, assigned to the same assignee, and now US. Patent No. 3,305,841, a system utilizing coded combinations of indicia or bits. In particular, it discloses a system wherein each character is divided into linear regions. Within each region is a line segment. The stored indicia (bits) are in groups of coded combinations of indicia which indicate the starting and ending points of the line segments in each linear region. With such a system, in the worst case, the number of bits required to represent a character is compressed, vis-a-vis the system of US. Patent No. 3,165,045, by a factor of three, and in the average case the compression is fivefold. While such compressions are extremely valuable, they have created a demand for even greater compressions.

It is an important object of this invention to provide apparatus for effecting these greater code compressions.

The invention contemplates a system for presenting a pattern to an electromagnetic radiation sensitive medium wherein the pattern includes an area divisible into linear regions. The area has a first visual state (such as white) and an array of linear portions in the area have a second visul state (such as black). The system comprises means for storing a coded representation of the pattern as a plurality of coded combinations of indicia associated with the linear regions of the pattern area. A first of the coded combinations of indicia includes at least a first coded group of indicia for indicating a starting point where, in a first linear region, a line segment having the second visual state begins, and at least a second coded group of indicia for indicating an end point where, in this first linear region, the first line segment terminates. At least a second of the coded combinations of indicia include at least one coded group of indicia representing an increment of a linear distance which, when combined with one of the coded groups of indicia of the first coded combination of indicia indicates a new one of the points of a line segment of a second linear region. The coded combinations of indicia are serially transmitted from the storing means. Electromagnetic radiation source means are included for scanning in a rasterlike manner successive linear regions of the electromagnetic radiation sensitive medium. Two-state means control the energization of the electromagnetic radiation source means. When the twostate means is in a first state it energizes the electromagnetic radiation source means and when in the second state it deenergizes the electromagnetic radiation source means during the scan of each linear region of the electromagnetic radiation sensitive medium. Means which receive the coded combinations of indicia from the storing means include first control means for switching the twostate means to the first state and second control means for switching the two-state means to the second state. The first control means first receives the first coded group of indicia of the first coded combination of indicia for switching the two-state means at a first point represented by the first coded group of indicia in a scan of a first linear region of the electromagnetic radiation sensitive medium. The second control means receives the second coded group of indicia of the first combination of indicia for switching the two-state means at a second point represented by the second coded group of indicia in the scan of the first linear region. Means combine the coded group of indicia of the second coded combination of indicia with one of the coded groups of indicia of the first coded combination of indicia and transmit the combined coded group of indicia to one of the control means for switching the twostate means at the new point in a scan of a second linear region of the electromagnetic radiation sensitive medium.

Thus it is seen that it is only necessary to state in full the starting and ending addresses of the line segment of a first linear region since the starting and ending addresses of the line segments of subsequent linear regions are obtained by incrementing the addresses of the line segment of the first linear region. Since the increments are small numbers they can be represented by smaller coded groups of indicia than those representing the full addresses.

There are also disclosed features of the invention for still further compressing the number of bits required to represent the patterns.

These features and other objects and the advantages of the invention will be apparent for the following detailed description when read with the accompanying drawings which show, by way of example and not limitation, representative apparatus for realizing the concepts of the invention.

In the drawings:

FIGURE 1 shows in detail a character superimposed on a coordinate system for explaining the invention; and

FIGURES 2a and 2b show a block diagram representation of a system for generating patterns or characters on an electromagnetic radiation sensitive medium.

In general, the system can generate a line of characters at a time wherein the characters are serially generated along the line. When one line is completely generated, the system can start generating the next line of characters. The lines of characters will, in being generated, energize a source of electromagnetic radiation such as a light source which creates visual representations of the characters for exposure onto an electromagnetic radiation or light sensitive medium such as a photographic film. The film thereafter can be used as a negative for creating printing plates. Therefore, each character will be recorded on an area of one visual state such as one color (for example, white) and the character itself will comprise line portions in a second visual state such as a contrasting color (for example, black).

Not only can the characters be generated serially along a line, but each of the actual characters is generated by a plurality of serially generated lines, such as columns of elements.

FIGURE 1 shows by way of example a greatly enlarged version of a 12 point upper case G. This character will now be analyzed. It is seen that it occupies the region between columns C8 and C63, and between rows R4 and R75. However, it should be noted that columns C5, C6 and C7 are blank. Similarly, columns C64, C65 and C66 are blank. These columns are space columns to the left and right of the pattern columns C8 to C63 inclusive. A pattern column is a column of the character slug which includes at least one black element. Accordingly, the columns defining the 12 point G include three blank columns followed by 56 pattern columns followed by three blank columns.

Now consider typical pattern columns. Column C8 scanned from top to bottom comprises an area of white extending from row R1 to row R30, an area of black extending from row R31 to row R45, and and area of white from row R46 to row R100. Column C34 comprises a first area of white extending from row R1 to row R3, a first area of black extending from row R4 to row R9, a second area of white extending from row R10 to row R69, a second area of black extending from row R70 to row R75, and a third area of white extending from row R76 to row R100. Column C44 has three areas of black interspersed between four areas of white. If any area of black within a pattern column is defined as a column segment, it is seen that each pattern column includes at least one column segment. In fact, it has been found that the majority of available type font styles have characters which comprise no more than four column segments.

It is also possible to analyze the character by means of rows. In such a case each pattern row will have at least one row segment. The invention contemplates both types of analyses and the claims employ the generic word line to mean either row or column.

From the above analysis of the pattern columns it is possible to establish a method of defining the pattern within the column. In particular, it is only necessary to indicate the starting row of an area of black or column segment and to indicate the ending row of the column segment. Accordingly, the pattern in column C8 can be defined as a column segment starting at row R31 and ending at row R45. The column segment of the next column, column C9, starts at row R28 and ends at row R52. Similarly, the pattern of column C34 canbe defined as: a first column segment starting at row R4 and ending at row R9, and a second column segment starting at row R70 and ending at row R75. The pattern of column C44 would be similarly defined. Therefore, any pattern column can be defined with four groups of two units of information, wherein the first unit indicates a starting element address (the row at which the column segment starts) and an ending element address (the row at which the column segment ends).

It is also possible to define the pattern within a column by a starting element address along with an element area (the length of the column segment). It should be noted that the element area indirectly defines an ending address element. While the invention contemplates either method, the starting and ending address method will be used as an example.

Returning now to the starting and ending address method, it is also possible to define the starting and ending element addresses of the column segment of column C9 by incrementally modifying the starting and ending element addresses of the column segment of column C8. In particular, the starting element address R31 of column C8 can be changed by an incremental value of 3 to obtain R28, the starting element address of column C9. Similarly, the ending element address R46 of column C8 can be changed by the incremental value +6 to obtain the ending element address R52 of column C9. Thus, the incremental values indirectly define the starting and ending element addresses of column C9.

Table I is an analysis of the pattern columns of the character shown in FIGURE 1 with respect to starting and ending element addresses and also with respect to element address increments between adjacent columns.

A study of FIGURE 1 and Table I reveals several interesting phenomena. There is one column segment for columns C8 through C17, two column segments for columns C18 through C41, and three column segments for columns C42 through C48, two column segments for columns C49 through C60 and one column segment for columns C61 through C63. In addition, the columns with the same number of column segments are in adjacent groups of columns. If each column is assumed to have the same number of column segments, the maximum number must be chosen and the columns with fewer column segments must be defined as having the maximum number of segments which are contiguous. Therefore, according to a feature of the invention, the coded combination of indicia associated with a column is preceded with a coded combination of indicia representing the number of column segments in the column.

In Table I it can be seen that there are a large number of incremental changes between adjacent column segments, but there are only about eleven changes in sign or the direction of the incremental change. See, for example, the transitions between columns C40 and C41, between columns C55 and C56, and between columns C60 and C61. Hence, if each coded group of indicia representing an increment has associated with it a sign indication, more information is required to represent the character. However, according to another feature of the invention, each coded group of indicia representing an increment actually represents the magnitude of the increment, and, wherever appropriate, coded indicia is imbedded in the flow of coded combinations of indicia from the storing means to indicate a change in the direction (sign) of the increment.

There are many adjacent columns having column segments with the same starting and ending element addresses, such as columns C33 to C40. In other words, these column segments have no increments. If these zero increments are represented by coded groups of indicia, more information than necessary is required to represent the character. According to another feature of the invention, after the transfer from the storing means of the coded combination of indicia associated with a column which precedes a group of columns having zero increments, there is transferred a coded combination of indicia indicating that the last starting and ending element addresses are to be repeated a given number of columns. A variation of this feature can be seen by studying columns C50 to C60. Here, the starting element address R43 remains constant while the ending element addresses are incremented. Therefore another feature of the invention contemplates keeping one element address constant while incrementing the other element address of a column segment.

Referring to FIGURE 2 there will now be described a system for executing the above described inventive concepts.

The system generates patterns by modulating the intensity of an electron beam as it sweeps across the inside a of the face of a cathode ray tube. The electron beam is driven to scan in a rasterlike manner, i.e., there are sequential vertical (column) scans which are incrementally displaced from each other in a horizontal direction. Of course, the horizontal and vertical directions can be interchanged. However, columnar (vertical) scans are more desirable when the patterns are actually a line of characters.

In particular the electron beam is controllably turned on and off during each column scan.

As has been discussed above, each pattern column has a plurality of elements and has at least one distinct line segment of contiguous elements. The line segments have start and end points or elements. The electron beam, during each scan, is turned on at a time related to the start point and off at the end point of each line segment in each column of the pattern.

In order to determine the electron beam turn-on and turnoff times each column scan is divided into a plurality of equal time increments. Since the column scan is a linear function of time each time increment is equal to an element in the column on the face of the cathode ray tube. Therefore, by equating the elements on the face of the cathode ray tube with the elements in the pattern, the elements of the pattern are mapped onto the face of the cathode ray tube. Now, by storing in registers the addresses of the start and end elements, i.e., the number of elements from a base point, of each line segment of a column of the pattern and by counting the number of time increments (elements) elapsing in a column scan from the start of the column sweep by the cathode ray tube the desired result is obtained. For example, when the number of counted time increments equals the stored address of the start element (start element address) of the first line segment in the column, the electron beam is turned on and when the time increment count equals the address of the end element (end element address) of the first line segment, the electron beam is turned off. If there is a second line segment in the column, the electron beam is turned on and off in a similar manner for the second line segment. After the column has been scanned, the registers are updated for the next column by any combination of the following methods:

(1) The start and end element addresses in the registers can be replaced by new start and end element addresses received from a memory; or

(2) The start and end element addresses in the registers can be modified by combining them algebraically with incremental data obtained from a memory; or

(3) The start and end element addresses in the registers can be explicitly repeated without modification. Either all element addresses can be repeated or only selected addresses repeated while the others are replaced or modified.

Several system parameters are worth noting before describing the system. All words, whether data or code (control), are transferred from the memory as 4-bit bytes in parallel. Every starting and ending element address is an 8-bit byte. Therefore two words are required to transfer an address from the memory. Every increment is a 4-bit byte with the most significant bit always being zero. Therefore, the incrementing can only extend to eight elements. There is also assumed to be a maximum of four line segments per column (or four pairs of start and end element addresses).

The following table indicates the types of words transferred from the memory.

Only memory data words assume values from zero to seven. The operation codes or code words have values between eight and fifteen. The operation codes have the following meanings.

The codes NOP indicate no operation is to be performed. The SUB code indicates that the next two words from memory are data words which are to be combined to form a new start or end element address for a line segment. The NCS code indicates that the next word from memory represents twice the number of line segments in a column. The RC code indicates that the next word from memory represents the number of pattern columns which are to be generated by repeating the last previous values entered prior to this operation. The RS code indicates that the direction of incrementing for one of the start or end element addresses of one of the line segments is to be changed. The RSR code controls the repeating of a selected start or end element address. The EOP code indicates the end of the data for the pattern.

The data has one of the following meanings:

DS:Start address increment DE=End address increment SM=Most significant half of a start address SL=Least significant half of a start address EM=Most significant half of an end address EL=Least significant half of an end address RCV=Repeat value NCSV=Number of column segments value The various units of the system will now be described with reference to FIGURE 2.

It should be noted that signal names and the lines carrying the signal have the same reference designation. For example, the MOD signal is transmitted on the MOD signal line. Generally, the positive or high signals are shown or mentioned. However, most of the signals also have a complementary signal. For example, the AB counter ABC transmits, from its two outputs, two signals, respectively, in parallel, the UAB and UAB signals. When the UAB signal is high the UAB signal is low, and vice versa. When specifically required, both the signal and its complement are shown and mentioned. In addition, many of the lines which carry data are shown as a single line, for example, the TAR signal line. This is actually a cable of sixty-four lines TAR1 to TAR64. For simplicity, only the single line cable is shown. However, when required the cable is fanned out and the specific lines therein are given their appropriate suffix numbers. Numerals shown in parentheses adjacent to lines indicate the actual number of lines in the cable.

The memory M can be a magnetic core memory with suitable address selection and control circuits. The memory delivers 4-bit parallel words to four output lines MM1 to MM4 (shown as line or cable MM) in response to step pulses received from the step pulse generator SPG. Each step pulse causes the memory to output one word.

There is a control unit comprising a decoder FD, pulse generator PGS, and an update control counter K. The decoder FD is used to generate control signals in response to code words received from memory M. The decoder FD can comprise four paraphase amplifiers having inputs connected to the four MM signal lines, respectively. The outputs of the amplifiers are connected to inputs of a binary-to-hexadecimal decoder. The outputs of this decoder are connected via gating logic, to the set inputs of flip-flops which generate the control signals, RC, NCS, RSR, RS, SUB and EOP. The positive output of the paraphase amplifier connected to the most significant bit line MM4 drives a flip-flop for the MOD signal. However, provision is made to insure that the MOD signal does not occur for the data word following the code words RC and NCS and the two data words following the SUB code word. This can be done by feeding the MOD signal to an input of a gate having other inhibiting inputs connected to the RC, NCS and SUB signals.

The flip-flops are cleared by using a circuit employing gating logic, a counter and a delay device which responds to the pulses on line STEP. Each of the flip-flops, except the one generating the SUB signal, is cleared after the next step pulse. That flip-flop is cleared after the second next step pulse.

The pulse generator PGS which is used to step the counter K is basically two channels of one-shot multivibrators. In the first channel, the MOD and RSR signal lines are connected to the input of a first one-shot multivibrator which delivers a pulse from its output a given period of time after it receives a signal at its input. This output PLS is connected to the step input S of counter K. The SUB signal line is connected to the input of a second one-shot multivibrator which delivers a pulse from its output the given period of time after it receives a signal at its input. The output of the second multivibrator is connected to the input of a similar third one-shot multivibrator. The outputs of the second and third one-shot multivibrators are connected via another OR circuit to the input of a most-least counter MLK. This counter is a one-stage binary counter having an initial clear input (not shown) for setting it to a zero state at the start of operation. The counter delivers an output to the ML signal line. The counter is used to keep track of the most and least significant halves of start and end addresses during the SUB operations. The output of the third oneshot multivibrator is also connected to the step input of counter K. Whenever the MOD signal is present the pulse generator PGS delivers a pulse on the PLS signal line after the given period of time from the start of the MOD signal. Whenever the SUB signal is present the pulse generator delivers a first pulse to the counter MLK (which changes state) after the given period of time and a second pulse to that counter MLK. The second pulse is also transmitted via the PLS signal line to step counter K the given period of time after the first pulse. The time delay is required to insure that all required memory transfers are completed before indexing the counter K since this counter is to control the suspension of memory transfers.

The update control counter basically keeps track of the start or end element address being considered at any one time. For example, when the counter has a count of Zero it indicates the start element address of the first line segment in a column, a count of one indicates the end element address of the first line segment, etc. The update control counter comprises the counter K, the gate G and the counter decoder KD. The counter K can be a fourstage binary counter which counts to sixteen. The counter K has a count (or step) input S, connected to the PLS signal line, and also to the D-gate DG4. The count input steps the counter for each pulse received. The counter K has a clear input C, connected to the output of gate G, which clears the counter to Zero in response to a signal received from gate G, and has an initial clear input (not shown) to clear the counter at the start of operation. The gate G can be an AND circuit having two inputs connected to the EVS and R2 signal lines, respectively. The EVS signal line transmits a pulse from the cathode ray tube circuits (FIGURE 2B) at the end of each column scan of the electron beam. The RZ signal line will have an allow signal only at those times when the repeat col umn counter RCC contains zero indicating no column repeat. When columns are to be repeated it is necessary to interrupt the flow of information from the memory. This is accomplished by preventing the clearing of counter K as will become apparent during the description of the step pulse generator SPG.

The counter decoder KD is a standard binary-to-octal decoder which receives the outputs of the three-least significant binary counter stages of counter K via paraphase amplifiers and transmits a signal on one of eight output signal lines UCC (UCCl to UCCS) in accordance with the count accumulated by counter K. Hence each line is associated with one of the start or end addresses of one of the four possible line segments.

The step pulse generator SPG generates the step pulses which are transmitted via the STEP signal line to direct the memory M to transfer the next word. The step pulse generator SPG can include a free running pulse generator having an output connection to one input of an AND gate. The output of the AND gate is connected to the STEP signal. One control input of the AND gate is connected to the output of an equality comparator. The comparator compares the contents of the counter K with the signals on NCSV lines from number of columns segments register NSR. This register stores an indication of the number of line segments in the column being updated. When the comparator senses equality it transmits a signal which blocks the AND gate. Then pulses will not pass through the gate until the counter K is cleared. Another control input receives the RZ signal.

The adder-subtractor AS which is used to modify by incrementing start and end element addresses, can be an eight binary position parallel adder-subtractor. The adder-subtractor has eight augend inputs connected to the eight lines AUG]. to AUG8, respectively, and has eight addend inputs. The four least significant addend inputs are connected via the four ADDNI to ADDN4- and gates GS to the four lines MMl to MM4, respectively. The four most significant addend inputs are wired to permanently represent zeros. (The gates GS can be four AND circuits having control inputs connected to the MOD signal line.) An adder-subtractor control is connected via the SIGN signal line to the sign register SR. When the signal on the SIGN signal line represents zero the adder-subtractor AS operates as an adder and when the signal represents one it operates as a subtractor. The eight result terminals of the adder-subtractor are connected via the eight RES signal lines to the column segment storage switch CSS.

The sign register SR stores sign indications for incre menting. Since there can be up to four line segments per column and each line segment has a start and an end element address, there are eight possible addends per column scan. Accordingly, the sign register SR includes eight one-stage binary counters, each associated with one of the possible addresses. The input of each one-stage binary counter is connected to the output of an input AND circuit. One input of the input AND circuit is connected to the RS signal line. The other input of the AND circuit is connected to one of the UCC signal lines. The output of each one-stage binary counter is connected to one input of an output AND circuit. The other input is connected to the same one of the UCC signal lines. The outputs of all of the output AND circuits are connected via an OR circuit to the SIGN signal line.

The selective repeat register SRR is identical to the sign register SR except that the one input of the input AND circuit is connected to the RSR signal line, and the associated OR circuit is connected to the SRR signal line. The register SRR controls selective repeating of starting and ending addresses of selected line segments in the column.

The register NCSR which stores a representation of the number of required line segments in a column can be a four-stage flip-flop register. The set input to each flip-flop is connected to the output of an AND circuit. One input to each of the AND circuits is connected to the NCS signal line. The other input of each of the AND circuits is connected to one of four MM signal lines. The clear inputs of the flip-flops is difierentiator coupled to the NCS signal line to clear the flip-flops before they receive a new number. The output terminals of fiip-fiops are connected via the eight NCSV signal lines, respectively, to the step pulse generator SPG. The register has means (not shown, responding to an initial clear signal) for initially clearing it to the representation of the number two at the start of operation.

The repeat column counter RCC stores a number indicating the number of column scans which use the same start and end addresses unmodified. The number is decremented by one for each succeeding column scan. The counter can be a four-stage binary counter of the count down type. The step input is connected via an AND circuit to the EVS signal line. Upon reaching zero the counter emits a signal on the R2 signal line to the gate G. The control input of the AND circuit receives the RZ' signal. Each of the stages has a presetting input connected to the output of an AND circuit. One input of each AND circuit is connected to the RC signal line. The other input of the AND circuits is connected to one of the MM signal lines to allow loading of the counter.

The column segment storage switch CSS is basically a logic network that switches information from either the memory M, via the four MM signal lines, or the result from the adder-subtractor AS, via the eight RES signal lines, to either the A-register AR, via the 64 TAR signal lines, or to the B-register BR, via the 64 TBR signal lines. Typical Boolean equations for the logic network are as follows.

[ (SUB ML) +MOD+SRR1 TAR5=UAB'UCC1- (MM l-+RES5) The integer following a letter combination indicates the specific signal line. The indicates an OR operation, the an AND operation, and a the complement of a signal.

The A-register AR is a sixty-four stage flip-flop register arrayed into eight groups of eight flip-flops. Each group is associated with a start or end element address of one of the four possible column segments. The set input of each flip-flop is connected to one of the TAR signal lines from the switch CS8. The clear input of each of the flip-flops is connected to the output of one and the same AND circuit. A first input of the AND circuit is connected to the UAB signal line. A second input is connected to the EVS signal line and a third input is connected to the RZ signal line. Thus the A-register is cleared just prior to its updating provided a repeat scan is not called for. The output of each of the flip-flops is connected to one of the sixty-four FAR signal lines.

The B-register BR is a sixty-four stage flip-flop register similar to the A-register AR. The set input of each of the flip-flops is connected to one of the TBR signal lines. The clear input of each of the flip-flops is connected to the output of one and the same AND circuit. A first input of the AND circuit is connected to the UAB signal line. A second input is connected to the EVS signal line and a third input is connected to the RZ signal line. The output of each of the flip-flops is connected to one of the sixtyfour FBR signal lines.

The column segment data switch CSD is basically a logic network which switches selected outputs of either the A-register AR, via the PAR signal lines, or the B- register BR, via the FBR signal lines, to the column element comparator CEC, via the eight SD signal lines.

A typical Boolean equation of the logic network for the least-significant bit is:

where (1+N8) and (1+N) are suflix numbers for the FAR, FBR and SDD signal lines.

The adder-substractor switch ASS is also a logic network which switches selected outputs of the A-register AR, via the FAR signal lines, or the B-register BR, via the FBR signal lines, to the augend inputs of the addersubtractor AS, via the eight AUG signal lines.

A typical Boolean equation for the least significant bit AUGl (SRR-l- MOD) -UAB- where (1+N8) and (1|N) are sutfix numbers for the PAR, FBR and UCC signal lines.

The segment data counter SDK which selects the start and end element addresses for transfer to the column element comparator CEC can be a three-stage binary counter. The step or count input S of counter is connected to the DEQ signal line which is pulsed each time the electron beam is switched between on and off indicating a new address is required. The clear input C of the counter is connected to the EVS signal line which emits a pulse at the end of each column scan of the electron beam. At that time, the counter is cleared to zero. The counter has an initial input (not shown). The outputs of the counter are connected to inputs of the SD decoder SDD. The decoder can be a binary-to-octal decoder whose inputs are the outputs of the binary counters of the counter SDK and whose outputs are connected via the SDD via signal lines to the column segment data switch CSD.

The A-B counter ABC is a one-stage binary counter having its step input connected via the gate G1 to the EVS signal line, and an initial clear input (not shown). Signal RZ controls operation of gate G1. The counter ABC has a 1 and a 0 output connected to the UAB and UAB signal lines (shown only as one line UAB). After the initial clear, counter ABC transmits a positive or high signal on line UAB and a negative or low signal on line UAB. As the counter is stepped the states of the signals alternate.

In FIGURE 2B there is shown the cathode ray tube control circuits. The column element counter CEK counts the time increments and therefore the elements in a column during a column scan by the electron beam. The column element counter CEK can be an eight-stage binary counter. The outputs of the stages are connected via the CEN signal lines to column element comparator CEC. When the counter is indexed beyond its capacity it clears to zero and emits an overflow signal on the EVS signal line. The counter CEK has an initial clear input (not shown) which clears it to zero. The step or count input is connected to the output of gate G2. The retrace counter RTK establishes the retrace time period for the electron beam by counting time increments. The counter RTK is a five-stage binary counter. When it reaches its capacity it resets to zero and emits an overflow pulse on the SVS signal line. The step or count input is connected to the output of gate G3. The counter RTK has an initial clear input (not shown) which sets the counter to a count of zero.

The EVS signal line is connected to the clear input of vertical scan flip-flop VS while the SVS signal line is connected to the clear input of flip-flop VS. The outputs of the flip-flop are connected to the gating inputs of AND gates G2 and G3. The other inputs of each of the gates is connected to the output of a free-running oscillator OSC.

The EVS and SVS signal lines are connected to the vertical deflection control VDFC which drives the vertical deflection of the cathode ray tube CRT. Control VDFC can be a gated sawtooth generator that is gated on by an SVS signal and gated off by an EVS signal.

When counter CEK is cleared to zero the EVS signal turns off the sawtooth generator and sets the flip-flop VS to the clear state opening gate G3 and closing gate G2. Pulses from the oscillator OSC start stepping the counter RTK. When the counter RTK exceeds its capacity (overflows) the SVS pulse is emitted turning on the sawtooth generator and setting the flip-flop VS. Gate 2 opens and gate 3 closes. Pulses from oscillator OSC are now fed to the count input of counter CEK. When the counter CEK overflows it emits an EVS pulse, and the cycle repeats. While counter CEK is counting it transfers signals (representing the instantaneous element count), via the CEN lines, to the column element comparator CEC. The other side of the comparator, which is a conventional equality comparator, is receiving a start or end address 13 for a line segment via the lines SD. When equality is reached the comparator CEC emits a pulse on the DEQ signal line. The comparator has paraphase amplifiers at its inputs.

The DEQ signal line is connected to the step input of the video counter VC (a one-stage binary counter). The counter has an initial clear input (not shown) to set it to a state that turns off the electron beam. Video counter VC drives the video drive circuits VDC (the usual Z-axis circuits) of the cathode ray tube CRT. The cathode ray tube CRT has horizontal deflection control HDC which drives the horizontal deflection system. The horizontal deflection is incremented whenever an end of vertical scan EVS occurs. The cathode ray tube also receives electron beam accelerating voltages from source AVS.

The face of the cathode ray tube is focused by the lens LENS onto a moving film FLM. The film is driven by scroll drive SDX past lens LENS. Thus images generated on the face of the cathode ray tube are recorded on film FLM.

The system will now be cycled through the writing of several typical columns of the pattern of FIGURE 1. It is assumed that all registers, flip-flops and binary counters have been cleared to their initial states.

Columns C8, C9 and C will first be written. Since the number of column segments register NCSR is initially cleared to two and the counter K is cleared to zero, the comparator in the step pulse generator detects an inequality. Generally, as long as the inequality exists, step pulse generator SPG transmits pulses via the line STEP to the memory M. The first such pulse causes memory M to transmit the first memory word (1011) to the lines MM. The word is the NCS code word implying that the next word from the memory M will indicate twice the number of column segments in the column C8 and all succeeding columns until it is changed by a new NCS code word. The decoder FD transmits a signal on the NCS signal line to open the input gates of the register NCSR. The step pulse generator SPG emits the next pulse and the memory M emits the data word (0010), indicating one line segment per column, to the MM signal lines. The word enters the NCSR register. The next step pulse from step pulse generator SPG causes the memory to emit the next word, a code word (1010). Decoder FD decodes this as the SUB code word meaning that the next two words are the least and most significant halves of a start element address, and transmits a signal on the SUB signal line. The next word (1111) emitted by memory M is a data word. This word is an SL data word, the least significant half of a start address. At this time, counter K holds a count of zero causing decoder KD to emit a sginal on the UCC1 signal line, the ML counter MLK is cleared and emitting the ML signal, the AB counter ABC is cleared and emitting the UAB signal. These signals cooperate in the column segment storage switch CSS to cause the data word (1111) to pass from the signal lines MM via the switch CSS and the TAR1 to TAR4 signal lines to the four least significant bit flip-flops of the first group of eight flip-flops in the A-register AR. The first group stores the start address of the first line segment of a column. The SUB signal causes the pulse generator PGS to emit a first pulse. The pulse switches the ML counter MLK which thereafter emits a signal on the ML signal line. The next word from the memory M is a word (0001); an SM (most significant half of a start address) data word. Because the ML signal instead of the ML signal is now present, and since the remaining control signals to the column segment storage switch CSS have not changed the data word (0001) is fed via the MM signal lines, the switch CSS and the TARS to TARS signal lines to the four most significant bit flip-flops of the first group of eight flip-flops in the A-register AR. This group of eight flip-flops now contains the binary number 00011111 (decimal 31), the start element address of the line segment of column C8.

The pulse generator PGS emits the second pulse in respouse to the SUB signal. This second pulse clears the ML counter MLK which now generates the ML signal, and also steps via the PLS line the counter K causing counter decoder KD to emit the UCC2 signal. Step pulse generator SPG still detects an inequality between the contents of the register NCSR represented by the signals on the NCSV signal lines, and the count in the counter K, represented by the signals on the KV signal lines. The pulse generator SPG continues emitting step pulses.

The next word from the memory M is a code word (1010) representing a SUB operation code indicating the next two words are data words which, in fact, represents the least and most significant halves of the end element address of the first line segment. These next two words have the binary values (1110) and (0010). The operation on these two words is the same as that following the first SUB code word except that the UCC2 signal instead of the UCC1 signal is now present. The words pass sequentially through column segment storage switch CSS and the TAR9 to TAR12, and TAR13 to TAR16 signal lines to the second group of eight flip-flops (the storage register for the end element address of the first line segment) in the A-register AR. This group now stores the binary number 00101110 (decimal 46).

The ML counter MLK is restored by the second pulse resulting from this SUB signal. This second pulse is also fed to the step input of counter K and decoder KD emits a signal on the UCC3 signal line. Now the step pulse gen erator SPG detects equality between the count of counter K and the contents of the register NCSR, and suspends emitting step pulses to memory M.

The A-register AR now contains all of the information for the writing of column C8, i.e., the start element address (00011111, decimal 31) and the end element address (00101110, decimal 46) of a single column segment. The remainder of the A-register AR is zero. See the entry for column number 8 of Table I.

All of this loading occurs before the first column scan by the electron beam has occurred. When the column element counter CEK next overflows, it emits an EVS pulse signal. The EVS signal switches the A-B counter ABC which then generates the UAB signal, it clears the segment data counter SDK (redundant at this time), it clears the B-register BR (redundant at this time) and more particularly it clears the counter K. Counter decoder KD emits a signal on the UCC1 signal line. Step pulse generator SPG again detects an inequality between the count in counter K and the number stored in the number of column segment register NCSR so it again emits step pulses to the memory M.

The memory M emits the word (1101) a reverse sign code word. Decoder FD decodes the word to the RS signal which is transmitted to the sign register SR where it cooperates with the UCC1 signal to reverse the state of the one-stage binary counter associated with the start address of the first line segment (indicated by the UCC1 signal). Since all of the counters in the sign register SR were initially cleared to the zero state indicating the reversal of this counter, switching it to the one state indicating changes the sign associated with any incrementing of the start address of the first line segment to a decrement.

The next memory word (0011) is a data word (decimal 3) indicating an incremental change. Since the most significant bit is a 0, the decoder FD senses it and generates the MOD signal. Recalling that UCC1 signal is present, the MOD signal cooperates with the UCC1 signal in the sign register SR to gate out the contents of the first counter (just set to one). Since this counter is set to one a signal is fed to the adder-subtractor AS switching it to a subtractor. The MOD signal opens gates GS connecting the MM signal lines to the ADDN signal lines so that this data word (decimal 3) provides a subtrahend for the adder-subtractor AS. The MOD signal cooperates with the UAB signal and the UCC1 signal in adder-subtractor switch ASS to non-destructively read out the contents (decimal 31) of the first group of eight flip-flops of the A-register AR, via the FAR1 to PARS signal lines, the switch ASS, the AUGl to AUGS signal lines, to the addersubtractor AS to provide a minuend. The MOD signal cooperates with the UCC1 signal and the UAB signal in switch CSS to transfer the difference (decimal 28) to the first group of eight flip-flops (storage register of the start address of the first line segment) in the B-register BR. This is done by connecting the RESl to RESS signal lines to the TBRl to TBR8 signal lines.

The pulse generated by the pulse generator PGS in response to the MOD signal is transmitted via the PLS signal line to the Step input of counter K which steps. Decoder KD starts transmitting a signal on line UCC2.

The next memory word (0110) is a data word (decimal 6). Decoder FD senses the zero in the most significant bit position and generates another MOD signal. This MOD signal cooperates with the UCC2 signal in the sign register SR to gate out the contents of the second counter. Since this counter is still cleared the signal on the SIGN line makes the adder-subtractor AS an adder. The MOD signal at gates GS connect the MM signal lines to the ADDN signals to provide the data word (decimal 6) as an addend. The MOD signal cooperates with the UCC2 signal and the UAB signal in switch ASS to connect the FAR9 to FAR16 lines to the AUGI to AUG8 lines. The contents of the second group of eight flip-flops (storing the end address of the first line segment) of the A-register AR are fed to the augend inputs of the adder-subtractor AS to provide an augend (decimal 46). The MOD signal cooperates with the UCC2 signal and the UAB signal in switch CSS to connect the RES]. to RES9 signal lines to the TBR9 to TBR16 signal lines. The sum (decimal 52) is loaded into the second group of eight flip-flops (those storing the end address of the first line segment) of the B-r-egister BR.

The pulse generator PGS in response to the MOD signal then transmits a pulse via the PLS signal line to the step input of counter K. Decoder KD then transmits a UCC3 signal (extraneous at this time). Step pulse generator SPG detects equality between the count of counter K and the contents of number of column segment register NCSR and stops emitting stepping pulses. Transfers from memory M are suspended. The B-register BR new stores all the information required to write column C9 (S -=28; E=52). See the entry for column 9 of Table I.

Just after the start of the updating of the B-register BR (following the EVS pulse), the contents of the A-register AR start being transferred to cathode ray tube circuits. In particular, the EVS signal that initiated the updating of the B-register BR cleared the segment data counter SDK causing the generation of the SDD1 signal by decoder SDD.

The SDD1 signal cooperating with the UAB signal in the column data switch CSD connects the FARl to FAR8 signal lines to the SD1 to SD8 signal lines. The contents (00011111, representing decimal 31) of the first group of eight flip-flops of the A-register AR are transferred to one set of inputs of the column element comparator CEC. The outputs of the column element counter CEK (the instantaneous addresses during the column scan) are fed to the other set of inputs of the comparator CEC. When an equality is sensed the comparator CEC emits a DEQ pulse signal which triggers counter VC to the on state. Counter VC energizes the video drive circuits VDC which turn on the electron beam.

The DEQ signal also steps the counter SDK which is decoded to generate the SDD2 signal. The SDD2 signal cooperates with the UAB signal in switch CSD to connect the FAR9 to FAR16 signal lines to the SDI to SD8 signal lines. The contents (00101110, representing decimal 46) of the second group of eight flip-flops are transferred to the first set of inputs of the column element comparator CEC. Another comparison operation is performed with the element count of counter CEK. Upon equality another DEQ pulse signal is generated. This second DEQ pulse signal restores the counter VC which deenergizes the video drive circuits VDC turning 01f the the electron beam. This second DEQ pulse signal steps the counter SDK which causes the generation of the SDD3 signal. The contents of the third group of eight flip-flops are fed to comparator CEC. However, since the contents is 00000000 no equality can be detected before the end of the column scan. At the end of the scan column C8 has been written and the EVS signal is generated. The EVS signal cooperates with the UAB signal in the A-register AR to clear all the flip-flops therein so it can receive the information for column C10. The EVS signal clears the counter SDK which starts generating the SDD1 signal. The EVS signal switches the counter ABC which starts generating the UAB signal. And the EVS signal passes through gate G (the RZ signal is present all this time) to clear the counter K causing the decoder KD to generate the UCC1 signal. When the counter K is cleared, step pulse generator SPG notes the inequality between the count in counter K and the number stored in the register NCSR, and starts emitting stepping to direct the memory to resume transmitting information. This information will be used to update the A-register AR for the writing of column C10. Shortly thereafter, the contents of the B-register BR are transferred to the video circuits of the cathode ray tube system for the writing of column C9.

In particular, the UAB signal cooperates with the SDD1 signal in switch CSD to connect the FBRl to FBR8 signal lines to the SDl to SD8 signal lines. The contents (00011100, decimal 28) of the first group of eight flipfiops (the storage register of the start address of the first line segment) of the B-register BR are fed to one set of inputs of the column element comparator CEC. The outputs of the column element counter CEK are fed to the other set of inputs of the comparator CEC. When equality is detected the DEQ pulse signal is generated. The DEQ signal switches the video counter VC to one which turns on the electron beam through the agency of the video drive circuits VDC.

The DEQ signal also steps the counter SDK which causes the decoder SDD to generate the SDD2 signal. The SDD2 signal cooperates with the UAB signal in the switch CSD to connect the FBR9 to FBR6 signal lines to the SDI to SD8 signal lines. The contents (00110100, decimal 52) of the second group of eight flip-flops (the storage register for the end address of the first line segment) of the B-register BR are fed to one set of inputs of the comparator CEC. When the count of the counter CEK (represented by signals on the CEN signal lines) equals the address represented by the signals on the SD signal lines, comparator CEC emits another DEQ pulse signal. This second DEQ pulse signal switches the counter VC to zero turning off the electron beam through the agency of the video drive circuits VDC.

This second DEQ pulse signal also steps counter SDK resulting in the generation of the SDD3 signal. However, since the third group of eight flip-flops in the B-register store zero no further equalities are detected by comparator CEC before the end of the column scan and the electron beam remains off. Thus column C9 has been written. At the end of the scan another EVS signal is generated. The B-register BR is again updated to provide the writing information for column-C11 and the contents of the A-register AR are read out to perform the Writing of column C10.

The above sequence shows the updating of writing information for columns with a single line segment by substituting a new address (column C8) and by incrementing old addresses (column C9). Furthermore, the incrementing was either positive for the end address or negative (decrementing) for the start address of the line segment of column C9.

The next example will be the writing of columns having more than one line segment per column. See, for example, columns C18 and C19 of FIGURE 1. Since the signal flow through the system is similar to the signal flow described for columns C8 to C10, the discussion will not be as detailed and only the prominent aspects will be specifically pointed out. In order to simplify the description, Table III shows the flow of words from memory M.

TABLE III Column Comments Number NCS code word 18 Indicates two line segments 18 DS= 1 18 SUB code wordl 18 EL= 18 18 18 (S 45) 18 N=2 18 SUB code word (new address) 18 EL=4 18 18 19 RS ode word 19 DE 19 SUB code word (new address) 19 SL=5 19 At this time the A-B counter ABC is cleared (the UAB signal is present), counter K is cleared and the UCCI signal is present. The word (1011) is read from memory M. It is a code word causing the decoder FD to generate the NCS signal which clears the number of column segment register NCSR and opens its input gates. The next word from memory M (0100, decimal 4) enters the register NCSR. The word indicates that there are two start-end element address pairs (two line segments) in the current column being entered into the A-register AR. The memory word m+2 is the data word (0001) indicating that the start address of the first line segment is to be changed by one. The counter, in the sign register SR, associated with this start address has been set to one ever since the scan of column C9, therefore the MOD operation performs a subtraction on the contents (decimal 14) of the first group of eight flip-flops in the B-register BR and transfers the undated start address (decimal 13) to the first group of eight flip-flops in the A-register AR. Counter K is stepped by one and the UCC2 signal is generated. The memory word m+3 (1010) is a SUB code word followed by memory word m+4 (1111), a data word, and memory word m+5 (0001), a data word, and the second group of eight flip-flops of the A-register AR are loaded to contain decimal 31. Counter K is stepped by one generating the UCC3 signal.

The memory word m-+6 (1010) is a SUB code Word, followed by memory word m+7 (1101), a data word, and memory word m+8 (0010), a data word, and the third group of eight flip-flops of the A-register AR is loaded to contain decimal 45. Counter K is stepped by one and the UCC4 signal is generated.

The memory word m+9 (1010) is a SUB code word. The next two memory words m-l-IO (0100) and m'+11 (0100) are loaded into the fourth group of flip-flops of the A-register AR. The counter K is stepped by one. Now the comparator in the step pulse generator SPG detects an equality between the count in counter K and the contents of the number stored in the column segments register NCSR and suspends generating the step pulses to the memory M. The writing information for column C18 is now in A-register AR. The EVS pulse signal, at the end of the scan out of the contents of B-register BR to the video control circuits, for writing column C17, clears counter K causing the generation of the UCCl signal by decoder KD, and steps the A-B counter ABC causing the generation of the UAB' signal. The B-register BR will now be updated with information for writing column C19 and the contents of the A-register AR will be scanned out to write column C18.

The next memory word mi+12 (0001), a data word, causes the subtraction by one of the contents (decimal 13) of the first group of eight flip-flops of the A-register AR by the adder-subtractor AS and the difference (decimal 12) is stored in the first group of eight flip-flops in the B-register BR as the start element address of the first line segment of column C19. Counter K is stepped by one and the UCCZ signal is generated.

Memory word m=+13 (1101) is a RS code word which sets the second one-stage binary counter (the one associated with the end address of the first segment) of the sign register SR to indicate subtractions.

Memory word m+ 14 (0101, decimal 5), a data word, which generates the MOD signal, subtracts five from the contents (decimal 31) of the second group of eight flipflops in the A-register AR. The difference is stored in the second group of eight flip-flops in the B-register BR as the end element address of the first line segment. The counter K is stepped by one and the UCC3 signal is generated.

The memory word m +15 is a SUB code word. The memory words m+16 (0101) and m+17 (0011) are loaded into the third group of flip-flops of the B-register BR representing the start element address (decimal 53) of the second line segment. The counter K is stepped by one and the UCC4 signal is generated.

The memory word m+18 (0001, decimal 1) generates a MOD signal which causes the incrementing of the contents (decimal 63) of fourth group of eight flip-flops of the A-register AR via the adder-subtractor AS to the fourth group of eight flip-flops of the B-register BR to store the end element address (decimal 69) of the second line segment. Counter K is stepped by one. The contents of the counter K now equal the number stored in number of column segments register NCSR and memory transfers are suspended. The writing information for column C19 is now stored in the B-register BR which will be scanned out at the appropriate time in the usual manner.

The next example will be the use of a special code word imbedded in the flow of words from the memory to repeat in its entirety the writing information for a plurality of identical columns. This occurs for columns C33 to C40 inclusive of FIGURE 1.

The writing information for column C32 is stored in the A-register AR as a start element address (decimal 4) and an end element address (decimal 10) for the first line segment, and a start element address (decimal 70) and end element address (decimal 76) for the second line segment.

The memory word following the updating of the information for column C32 is the RC code word which is decoded by decoder FD to an RC signal fed to the input gates of repeat column counter RCC. The next memory word (1000, decimal 8) is a data word, which is loaded into counter RCC. Since the counter now stores a count other than zero it stops generating the R2 signal.

The disappearance of the R2 signal at the control input of gate G prevents EVS pulse signals from stepping counter K. The disappearance of the RZ signal at the clear gates of the A-register AR and the B-register BR prevents EVS pulse signals from clearing these registers after scan outs. The disappearance of the RZ signal at the control input of gate G1 prevents the EVS pulse signal from stepping A-B counter ABC. And the absence of the RZ signal to a control input of the gate in step pulse generator SPG suspends further memory transfers. The appearance of the RZ' signal at the input gate of the counter RCC will allow subsequent EVS pulse signals to step the counter. The result is that further memory transfers are suspended, the contents of the A-register AR and the B-register BR are frozen and successive scan outs of one of the registers (in this case the A-register AR) occur until the counter RCC is stepped down from eight to zero. Each EVS pulse signal following the scan out of the A-register AR steps counter RCC down by one. After eight such EVS pulse signals resulting in the writing of columns C33 to C40 counter RCC again contains zero. Then the RZ signal reappears, memory transfers resume, the A-register AR and the B-register BR are clearable, the counter K and the A-B counter ABC are steppable. The disappearance of the RZ' signal at the input gate of the counter RCC prevents further EVS pulse signals from stepping this counter.

Following the completion of column C40 (FIGURE 1) processing is routine until column C50. Column C50 contains two line segments. The start element address of the second line segment (set to decimal 43 during the updating of column C49) requires no modification for the next eleven columns (from column C50 through column C60). The other start and end element addresses require occasional modification during this section of the pattern. Table IV shows the memory words associated with column segments C50 and C51 which are typical for this section.

At this time the A-B counter ABC is cleared (the UAB signal is present), counter K is cleared and the UCCl signal is present. B-register BR contains the start element address (decimal 8) and the end element address (decimal 15) of the first line segment and the start element address (decimal 43) and the end element address (decimal 73) of the second line segment of column C49.

The memory word p+ (0001) is a data word which also generates the MOD signal for incrementing by one the contents (decimal 8) of the first group of eight flipfiops of the B-register BR while it passes via the addersubtractor AS to the first group of eight flip-flops of the A-register AR to become the start element address (decimal 9) of the first line segment of column C50. Counter K is stepped by one and the UCC2 Signal is generated.

The memory word p+l (0001) is a data word which also generates the MOD signal for incrementing by one the contents of the second group of eight flip-flops of the B-register BR while it passes via the adder-subtractor AS to the second group of eight flip-flops of the A-register AR to become the end element address (decimal 16) of the first line segment of column C50. Counter K is stepped by one and the UCC3 signal is generated.

The next memory word p+2 (1110) is a reverse selective repeat code word which generates the RSR signal. The RSR signal cooperates with the UCC3 signal in selective repeat register SRR to set to one the counter associated with the start address element of the second line segment. The output of this counter cooperating with the UCC3 signal generates the SRR signal. The SRR signal cooperates with the UCC3 signal in adder-subtractor switch ASS to connect the FBR17 to FBR24 signal lines to the AUGl to AUG8 signal lines. Thus the contents of the third group of eight flip-flops in the B-register BR pass through the adder-subtractor AS to the RESl to RES8 signal lines. Note the addend is zero at this time since gates GS are blocked (no MOD signal present). The SSR signal cooperates with the UCC3 signal in column segment storage switch CBS to connect the RESl to RES8 signal lines to the inputs of the third group of eight flip-flops of the A-register AR. The start element address of the second line segment of column C50 is thus stored. The RSR signal causes the pulse generator 20 to step the counter K by one and the UCC4 signal is generated.

Memory word p+3 (0001) is a data word which also generates the MOD signal for decrementing by one the contents of the fourth group of eight flip-flops of the B register BR while it passes via the adder-subtractor AS to the fourth group of eight flip-flops of the A-register AR to become the end element address (decimal 72) of the second line segment of column C50. The counter K is stepped by one. Now the comparator in the step pulse generator SPG detects an equality between the count in counter K and the number stored in the register NCSR and suspends memory transfer. The writing information for column C50 is now in A-register AR. The EVS pulse signal, at the end of the scan out of the contents of the B-register BR, clears counter K causing the generation of the UCCl signal and steps the A-B counter ABC causing the generation of the UAB signal. The B- register BR will now be updated with information for the writing of column C51 and the contents of the A- register AR will be scanned out to write the column C50.

The next memory word p+4 (0000) is a data word which also generates the MOD signal for incrementing by zero the contents of the first group of eight flip-flops in the A-register AR in its transfer via the adder-subtractor AS to the first group of eight flip-flops in the B-register BR to give the start element address (decimal 9) for column C51. Counter K is stepped by one and the UCC2 signal is generated.

The next memory word 2+5 (0001) is a data word which also generates the MOD signal for incrementing by one the contents of the second group of eight flip-flops of the A-register AR while it passes via the adder-subtractor AS to the second group of flip-flops of the B- register BR to become the end element address (decimal 17) of the first line segment of column C51. Counter K is stepped and the UCC3 signal is generated. The UCC3 signals gates out the one now stored in the one-stage binary counter associated with the start element address of the second line segment as the SRR signal. The SRR signal cooperates with the UCC3 signal in the addersubtractor switch ASS to connect the FAR17 to FAR24 signal lines to the AUGl to AUG8 signal lines. Thus, the contents of the third group of eight flip-flops of the A- register AR pass through the adder-subtractor AS unmodified (gates GS are blocked). The UCC3 signal cooperates with the SSR signal in switch CSS to connect the RESI to RES8 signal lines to the TBR7 to TBR24 signal lines and the start element address of the second line segment of column C50 is repeated and becomes the start element address of the second line segment of column C51. The SRR signal cooperates with the RSR signal at D-gate DG4 to emit a pulse to the step input of counter K. (D-gate DG4 can be an AND circuit which drives a delay multivibrator.) Counter K is stepped by one and the UCC4 signal is generated. The SRR signal disappears from the gate within the step pulse generator SPG permitting the memory M to transfer the next memory word p+6 (0000).

Memory word p+6 is a data word which also generates the MOD signal for incrementing by zero the contents of the fourth group of eight flip-flops in A-register AR in its transfer via the adder-subtractor AS to the fourth group of eight flip-flops in the B-register BR to give the end element address (decimal 72) of the second line segment for column C51. The counter K is stepped by one. Now the comparator in the step pulse generator SPG detects an equality between the count in counter K and the number stored in the register NCSR and suspends memory transfers. The writing information for column C51 is now in B-register BR ready for scanning out.

The remainder of the pattern is generated by combinations of the cited examples.

Finally the memory transfers the word (1111), an EOP code word, indicating an end of pattern which can be used to stop the processing by suitable means (not shown) or to prime the system by suitable means (not shown) for generating further patterns. It should be noted that an initial clear signal is required to initialize all counters and registers. The source of this signal and its feeding network to the appropriate devices was not shown merely for the sake of simplicity, it being realized that good engineering practice requires such initializing.

Since the various elements shown in the system are made up of standard components, and standard assemblies, reference may be had to High-Speed Computing Devices, by the staff of Engineering Research Associates, Inc. (McGraw-Hill Book Company, Inc., 1950); and appropriate chapters in Computer Handbook (McGraw- Hill, 1962) edited by Harvey D. Huskey and Granino A. Korn, and for detailed circuitry, to the example Principles of Transistor Circuits, edited by Richard F. Shea, published by John Wiley and Sons, Inc., New York and Chapman and Hall, Ltd., London, 1953 and 1957. In addition, other references are: For system organization and components: Logic Design of Digital Computers, by M. Phister, Jr., (John Wiley and Sons, New York); Arithmetic Operations in Digital Computers, by R. K. Richards (D. Van Nostrand Company, Inc., New York). For circuits and details: Digital Computer Components and Circuits, by R. K. Richards (D. Van Nostrand Company, Inc., New York).

An especially worthwhile book for finding the components mentioned in the specification, and the hardware for realizing the components as well as the techniques for mechanizing Boolean equations to actual logic networks is The Digital Logic Handbook, 1966-67 edition, copyrighted in 1966 by the Digital Equipment Cor poration of Maynard, Mass.

I claim:

1. In a system for presenting a pattern to an electromagnetic radiation sensitive medium wherein said pattern includes an area divisible into linear regions, said area having a first visual state and an array of linear portions in said area having a second visual state, means for storing a coded representation of said pattern as a plurality of coded combinations of indicia associated with the linear regions of the pattern area, a first of the coded combinations of indicia including at least a first coded group of indicia for indicating a starting point where, in a first linear region, a line segment having said second visual state begins and at least a second coded group of indicia for indicating an end point where, in said first linear region, said first line segment terminates, and at least a second of the coded combinations of indicia including at least one coded group of indicia representing an increment of a linear distance which when combined with at least one of the coded groups of indicia of said first coded combination of indicia indicates a new one of said points of a line segment of a second linear region, means for sequentially transmitting said coded combinations of indicia from said storing means, electromagnetic radiation source means for scanning in a rasterlike manner successive linear regions of said electromagnetic radiation sensitive medium, two-state means for controlling the energization of said electromagnetic radiation source means, said two-state means when in a first state energizes said electromagnetic radiation source means and when in the second state deenergizes said electromagnetic source means during the scan of the linear regions of said electromagnetic radiation sensitive medium, means for receiving said coded combinations of indicia from said storing means, said receiving means including first control means for switching said two-state means to the first state and second control means for switching said two-state means to the second state, said first control means first receiving said first coded group of indicia of said first coded combination of indicia for switching said two-state means at a first point represented by said first coded group of indicia in a scan of a first linear region of said electromagnetic radiation sensitive medium, said second control means receiving said second coded group of indicia of said first combination of indicia for switching said twostate means at a second point represented by said second coded group of indicia in said scan of said first linear region, means utilizing said one coded group of indicia of said second coded combination of indicia for modifying at least one of the coded groups of indicia of said first coded combination of indicia and transmitting the modified coded group of indicia to at least one of said control means for switching said two-state means at said new point in a scan of a second linear region of said electromagnetic radiation sensitive medium.

2. The system of claim 1 wherein the starting and ending points of the line segments are referenced with respect to given base point, wherein said new one of the points can be closer to or more remote from said given base point, and wherein said storing means stores further coded combinations of indicia similar to said second coded combinations of indicia and stores at least one coded datum representing a direction of incremental change, and said system further comprising means for receiving said stored coded datum for controlling said modifying means to establish said new point closer to or more remote from said base points by a distance equal to said increment of a linear distance.

3. The system of claim 2 wherein said modifying means maintains the same direction of change for subsequent of said further coded combinations of indicia until receipt of another coded datum.

4. In a system for presenting a pattern to an electromagnetic radiation sensitive medium wherein said pattern includes an area divisible into linear regions, said linear regions having a first visual state and an array of linear portions having a second visual state, means for storing a coded representation of said pattern as a plurality of coded combinations of indicia associated with the linear regions of the pattern area, a first of the coded combinations of indicia including at least a first coded group of indicia indicating a starting point where, in a first linear region, a line segment having said second visual state begins and at least a second coded group of indicia indicating an end point where, in said first linear region, said line segment terminates, a first coded datum, at least a second coded combination of indicia including at least one coded group of indicia representing updating information, means for transmitting said coded combinations of indicia from said storing means, electromagnetic radiation source means for scanning successive linear regions of said electromagnetic radiation sensitive medium, two-state means for controlling the energization of said electromagnetic radiation source means, said two-state means when in a first state energizing said electromagnetic radiation source means and when in a second state deenergizing said electromagnetic radiation source means during the scan of the linear regions of said electromagnetic radiation sensitive medium, means for receiving said coded combinations of indicia from said storing means, said means including first control means for switching said two-state means to the first state and second control means for switching said two-state means to said second state, said first control means first receiving said first coded group of indicia of said first coded combination of indicia for switching said two-state means at a first point represented by said first coded group of indicia in a scan of a first linear region of said electromagnetic radiation sensitive medium, said second control means receiving said second coded group of indicia of said first combination of indicia for switching said twostate means at a second point represented by said second coded group of indicia in said scan of said first linear region, means receiving said first coded datum for selectively controlling at least one of said first and sec ond control means to utilize the previously received 23 coded group of indicia or to receive and utilize the'coded group of indicia of said second coded combination of indicia during the scan of at least the next linear region of said electromagnetic radiation sensitive medium.

5. The system of claim 4 wherein said first coded datum represents a repeat number and said selective control means includes means for controlling at least one of said first and second control means to utilize the previously received coded group of indicia for thescans of a number of subsequent linear regions related to said repeat number.

6. The system of claim 4 wherein said first coded datum represents a control indicium for causing said selective control means to control at least one of said first and second control means to receive and utilize a coded group of indicia of said second coded combination of indicia, during the scan of the next linear region of said electromagnet radiation source means and wherein said coded group of indicia of said second coded combination of indicia represents one of the points of a line segment.

7. The system of claim 4 wherein said first coded datum represents a control indicium for causing said selective control means to control at least one of said first and second control means to receive and utilize a coded group of indicia of said second coded combination of indicia, during the scan of the next linear region of said electromagnetic radiation source means and wherein said coded group of indicia of said second coded combination of indicia represents an increment of a linear distance which when combined with one of the coded groups of indicia of said first coded combination of indicia indicates a new one of the points of a linear 7 segment during said scan of the next linear region.

8. The system of claim 7 further comprising a second coded data representing a repeat number and said selective control means includes means for controlling said first and second control means to utilize previously received coded groups of indicia during scans of a subsequent number of linear regions related to said repeat number.

9. In a system for presenting a pattern to an electromagnetic radiation sensitive medium wherein said pattern includes an area divisible into linear regions, each of said linear regions being divisible into a plurality of elements, said area having a first visual state and an array of linear portions in said area having a second visual state, means for storing a coded representation of said pattern as a plurality of coded combinations of indicia associated with the linear regions of the pat-tern area, at least a first of said coded combinations of indicia including at least a first coded group of indicia representing a first number of elements from a base to where, in the associated linear region, a linear segment having said second visual state begins and at least a second coded group of indicia representing a second number of elements from said base to where in said associated linear region said linear segment ends, and at least a second of said coded combinations of indicia including at least one coded group of indicia which represents an incremental number of elements, electromagnetic radiation source means for scanning linear regions of said electromagnetic radiation sensitive medium wherein the linear regions of said medium correspond to linear regions of said pattern and each of the linear regions of said medium is divisible into a corresponding plurality of elements, means for counting the number of elements said electromagnetic radiation source means scans from a base in each linear region and generating coded combinations of indicia for representing the count'of the scanned elements, first and second register means for receiving the first and second coded groups of indicia, respectively, of said first coded combination of indicia from said storing means, means for comparing the coded combination of indicia generated by said counting means and the coded group of indicia stored in said first register means during each scan of a linear region of said medium for energizing said electromagnetic radiation source means when said indicia have a given relationship and for comparing the coded combinations of indicia generated by said counting means and the coded group of indicia stored by said second register means during each scan of a linear region of said medium for deenergizing said electromagnetic radiation source means, and means for updating the coded group of indicia stored in at least one of said storage register means by algebraically changing the number of elements represented by said stored coded group of indicia by the incremental number of elements represented by said one coded group of indicia of said second coded combination of indicia after the scan of the linear region of said medium associated with said first coded combination of indicia and before the scan of the linear region of said medium associated with said second coded combination of indicia.

10. The system of claim 9 wherein said storing means stores further coded combinations of indicia similar to said second coded combinations of indicia and stores at least one coded datum representing an algebraicoperation-change signal, and wherein said updating means is a switchable adder-subtractor means which switches between adding and subtracting in response to a change signal, said system further comprising means receiving said one coded datum for transmitting said change signal to said switchable adder-subtractor means.

11. In a system for presenting a pattern to an electromagnetic radiation sensitive medium wherein said pattern includes an area divisible into linear regions, said linear regions having a first visual state and a variable number of line segments having a second visual state, means for storing a coded representation of said pattern as a plurality of coded combinations of indicia associated with the linear regions of the pattern area, a first of the coded combinations of indicia including a variable number of pairs of groups of coded combinations of indicia, each of said pairs being associated with a line segment in a linear region, a first coded group of indicia of each pair indicating a starting point where, in said linear region, the associated line segment having said second visual state begins and a second coded group of indicia of each pair indicating an end point where, in said first linear region, said associated line segment terminates, at least a second of the coded combinations of indicia indicating the number of pairs of groups associated with said linear region, means for transmitting said coded combinations of indicia from said storing means, electromagnetic radiation source means for scanning successive linear regions of said electromagnetic radiation sensitive medium, two-state means for controlling the energization of said electromagnetic radiation source means, two-state means when in a first state energizing said electromagnetic radiation source means and when in a second state deenergizing said electromagnetic source means during the scan of the linear regions of said electromagnetic radiation sensitive medium, means for receiving said coded combinations of indicia from said storing means, said means including first control means for switching said two-state means to the first state and second control means for switching said two-state means to said second state, said first control means receiving sequentially said first coded groups of indicia of said first coded combination of indicia for switching said two-state means at first points represented by said first coded groups of indicia, respectively, in a scan of a first linear region of said electromagnetic radiation sensitive medium, said second control means receiving sequentially said second coded groups of indicia of said first combination of indicia for switching said two-state means at second points represented by said second coded group of indicia, respectively, in said scan of said first linear region, and means responsive to said second coded combination of indicia for permitting each of said control means to receive the number of coded groups of indicia indicated by said second coded combination.

12. In a system for recording a pattern on a record medium wherein said pattern includes an area divisible into linear regions, said area having a first visual state and an array of linear portions in said area having a second visual state, means for storing a coded representation of said pattern as a plurality of coded combinations of indicia associated with the linear regions of the pattern area, a first of the coded combinations of indicia including at least one coded group of indicia for indicating at least one of the terminal points of a line segment having said second visual state in a first of said linear regions, and at least a second of the coded combinations of indicia including at least one coded group of indicia representing an increment of a linear distance which when combined with said coded group of indicia of said first coded combination of indicia indicates a new one of said terminal points of a line segment of a second linear region, means for at least transmitting said first coded combination of indicia and thereafter said second coded combination of indicia from said storing means, recording means for changing the visual state of said record medium when energized, said recording means successively scanning linear regions of said record medium, control means having first and second states for controlling the energization of said recording means, said control means when in the first state energizing said recording means and when in the second state deenergizing said recording means during the scan of the linear regions of said record medium, means for receiving said coded combinations of indicia transmitted from said storing means, said receiving means including means for switching said control means to one of said states, said switching means first receiving said one coded group of indicia of said first coded combination of indicia for switching said control means to a particular one of said states at a terminal point repre sented by said coded group of indicia in a scan of a first linear region of said record medium, means utilizing said one coded group of indicia of said second coded combination of indicia, for modifying said one coded group of indicia of said first coded combination of indicia and transmitting the modified coded group of indicia to said switch-means for switching said .control means to said particular one of said states at said new terminal point in a scan of a second linear region of said record medium.

13. The system of claim 1.2 wherein said recording means scans the record medium in a rasterlike manner.

14. The system of claim 12 wherein said recording means includes a source of electromagnetic radiation and said record medium changes its visual state when subjected to electromagnetic radiation.

15. In a system for presenting a pattern to a record medium wherein said pattern includes an area divisible into linear regions, said area having a first visual state and an array of linear portions in said area having a second visual state, means for storing a coded representation of said pattern as a plurality of coded combinations of indicia associated with the linear regions of the pattern area, a first of the coded combinations of indicia including at least a first coded group of indicia for indicating a starting point where, in a first linear region, a line segment having said second visual state begins and at least a second coded group of indicia for indicating an end point where, in said first linear region, said first line segment terminates, and at least a second of the coded combinations of indicia including at least one coded group of indicia representing an increment of a linear distance which when combined with one of the coded groups of indicia of said first coded combination ofvindicia indicates a new one of said points of a line segment of a second linear region, means for sequentially transmitting said coded combinations of indicia from said storing means, recording means for changing the state of said record medium, said recording means scanning ditferent linear regions of said record medium, twostate means for controlling the energization of said recording means, said two-state means when in a first state energizes said recording means and when in the second state deencrgizes said recording means during the scan of the linear regions of said record medium, means for receiving said coded combinations of indicia from said storing means, said receiving means including first control means for switching said two-state means to the first state and second control means for switching said two-state means to the second state, said first control means first receiving said first coded group of indicia of said first coded combination of indicia for switching said two-state means at a first point represented by said first coded group of indicia in a scan of a first linear region of said record medium, said second control means receiving said second coded group of indicia of said first combination of indicia for switching said two-state means at a second point represented by said second coded group of indicia in said scan of said first linear region, means utilizing said one coded group of indicia of said second coded combination of indicia for modifying one of the coded groups of indicia of said first coded combination of indicia and transmitting the modified coded group of indicia to one of said control means for switching said two-state means at said new point in a scan of a second linear region of said record medium.

16'. The system of claim 15 wherein said recording means scans the record medium in a rasterlike manner.

17. The system of claim 15 wherein said recording means includes a source of electromagnetic radiation and said record medium changes its visual state when subjected to electromagnetic radiation.

References Cited UNITED STATES PATENTS 3,058,659 10/1962 Demmer et al. 340-1725 3,237,168 2/1966 Hertz 340-l72.5

JOHN W. CALDWELL, Primary Examiner M. M. CURTIS, Assistant Examiner US. Cl. X.R. 178-68; 3l518, 22; 340-1725

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Classifications
U.S. Classification345/10, 358/1.9, 345/25, 347/225
International ClassificationG06F3/153, H03M7/30, G09G1/14
Cooperative ClassificationH03M7/30, G09G1/14, G06F3/153
European ClassificationH03M7/30, G09G1/14, G06F3/153