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Publication numberUS3492659 A
Publication typeGrant
Publication dateJan 27, 1970
Filing dateOct 5, 1966
Priority dateOct 5, 1966
Publication numberUS 3492659 A, US 3492659A, US-A-3492659, US3492659 A, US3492659A
InventorsLee Fred
Original AssigneeLee Fred
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Electrical resistance memory
US 3492659 A
Abstract  available in
Images(1)
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Claims  available in
Description  (OCR text may contain errors)

Jan. 27, 1970 F. LEE 3,492,659

ELECTRICAL RESISTANCE MEMORY Filed Oct. 5, 1966 I0 F|G-| 20 I6 |2 I2 l2 MZI I8 -18 l8 T M 2 I;

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- REFERENCE 40 LEVEL 38 32 l0 SELECTION VOL cmcun SE United States Patent 3,492,659 ELECTRICAL RESISTANCE MEMORY Fred Lee, 888 Mary Ave., Sunnyvale, Calif. 94087 Filed Oct. 5, 1966, Ser. No. 584,533 Int. Cl. Gllb 9/00 U.S. Cl. 340-173 7 Claims ABSTRACT OF THE DISCLOSURE An electronic memory formed from a plurality of electrical resistance elements connected in an array to permit successive elements to be individually pulsed with a relatively small electrical current, following which a predetermined operative characteristic of each element is sensed to determine whether or not the element is to be pulsed with a relatively large electrical current. The elements forming the array can be incandescent lamps whose heat radiation, light or resistance can be sensed to provide an indication of the status of the operating characteristic of the lamp.

This invention relates to an electronic memory and, more particularly, to a memory having a number of electrical resistance elements providing memory cells.

The present invention resides in a memory comprised basically of a matrix or an array of electrical resistance elements and a method of maintaining the memory in an operating condition. Each element has an operative characteristic or condition which changes when electrical current flows therethrough and whose operative condition persists for a finite time after the current has ceased. The array comprises a series of rows and a number of columns of these elements so that electrical switches can be placed in series with respective rows and columns. With this construction, the elements can be successively and individually actuated and only a single element at any one time can be connected to an external circuit. In this way, each element can be connected to means for sensing its operative condition and thereafter connected to a power source if the condition is found to exist. The entire array can therefore be periodically scanned and current pulses can be sent to those elements whose operative conditions exist. Thus, the operative condition of each element provides its memory.

Any operative condition of the elements can be used as a memory so long as it is affected by current flow through the element. Electrical resistance, heat and light are characteristics that can be sensed and can persist for a relatively long time after current flow through a circuit element has ceased. The persistence times of these characteristics can be considered long if the rate at which the array is scanned is high. A high scanning rate can be assured by the use of a high frequency scanning signal.

To illustrate the concepts of this invention, the particular circuit elements will be disclosed as incandescent lamps whose electrical resistance values increase with an increase in temperature. Thus, the particular operative condition to be sensed will be the increased resistance of the lamp and this can be determined by measuring the voltage drop across the same. The temperature increase in the lamp is brought about by the heat generated due to current flow and, since the heat dissipation from the lamp is relatively slow, the heat retained by the lamp will provide the actual memory therefor.

The purpose of scanning the array is twofold. Firstly, the voltage drop across the lamp is sensed to determine if its resistance value is high, i.e., if the lamp is on, and secondly to direct a current pulse through the lamp if the same is found to be on. In this way, the lamps can be maintained in an ON condition and this characteristic will establish the memory of the lamp. The scanning rate can be high enough to prevent the cooling of the lamps so that the ON lamps will remain on and the OFF lamps will remain off notwithstanding the periodic nature of the scanning signal.

When used in the foregoing manner, the lamp array requires no other memory. It is possible to use each lamp as a temporary memory cell because it remains hot for a finite time after its exciting current is interrupted and because the resistance of the lamp is much greater than when it is cold.

The method of maintaining the memory comprises the testing of a number of lamps in a recurring sequence by measuring their resistance to determine which are hot and then pulsing these lamps with an electrical current to keep them hot. When a hot lamp is found, a suflicient amount of current is allowed to pass through it to keep it hot before the succeeding lamp is tested. Thus, once a lamp is hot, it remains hot even though the current is maintained at a minimum level so that cold lamps are not heated by it.

Rather than sensing the resistance level of the lamps, the heat or light radiated from each lamp can be sensed to give a measure of the ON or OFF condition of the lamp. Specific sensors adjacent to the lamp are required to accomplish these ends.

The resent invention is constructed to allow a lamp, once it is turned on, to remain On with no storage or other memory system required. The lamp itself is its own memory, i.e., it remembers the fact that it has previously been turned on.

For the array of lamps each lamp does not require its own driver. The number of lamp drivers is limited to the number of rows and columns of the lamp array.

By sequentially testing the lamps in order, it is possible to provide a continuously recurring readout of the ON- OFF states of all of the lamps. In this way, a relatively large number of lamps can be used to form the array so that the resulting memory has a broad range of applications.

The memory of the present invention is simple in construction and can be combined with simple logic circuitry so that the lamp on either side of an ON lamp can be turned on and the last mentioned lamp then be extinguished. Thus, the display can be utilized as a forward or reverse counter. Carries or borrows can be caused to move from one row of the array to another row, thus allowing the various rows to represent digits of a decimal counter.

The primary object is thus to provide an electronic memory comprised of an array of electrical resistance elements connected in a manner to permit successive elements to be individually sensed for a particular operative condition and thereafter pulsed if the condition is found to exist so that the elements themselves can provide their own memory to avoid the necessity of a memory independent of the array.

Another object of this invention is to provide an electronic memory having an array of incandescent lamps whose heat radiation, light or resistance can be tested to provide an indication of its ON-OFF status so that the array can define a memory adapted for use in a variety of applications that require no other memory.

Still another object of the invention is to provide an electronic memory of the type described which can be combined with simple logic circuitry to form a counter for use in counting the relatively high figures.

A further object of this invention is to provide a method of maintaining the array of the type described in an operating condition by periodically testing each element for a particular operating condition and then by directing 3 an electrical current through the element immediately to keep the element operating in the particular condition notwithstanding the periodic nature of the scanning and pulsing steps of the method.

Other objects of this invention will become apparent as the specification progresses, reference being had to the accompanying drawing wherein:

FIG. 1 is a schematic view of the invention showing the array of resistive elements coupled to actuatable switches;

FIG. 2 is a schematic view of the invention with the matrix coupled to the sensor; and

BIG. 3 is a view similar to FIG. 2 but illustrating the use of the apparatus as a counter.

The electronic memory of the present invention includes a matrix or array of electrical resistance elements 12 arranged in rows and columns in the manner shown in FIG. 1. For purposes of illustration, each element 12 will comprise an incandescent lamp whose resistance increases with temperature and a respective semiconductive device 14 in series with the lamp to prevent current fiow in one direction.

Each lamp 12 is connected at one of its ends to a lead 16 and each device 14 is connected at one of its ends to a lead 18. Leads 16 and 18 therefore represent the rows and columns of the array.

Matrix 10 is therefore a memory system which can be used in a number of different ways with various types of external circuits. To be used as a memory, the method of the invention is carried out wherein each lamp is first tested to determine if it is on, i.e., if its electrical resistance is high, and then subjected to a current pulse if it is found to be on. Lamps 12 are successively tested by a scanning signal and, each time an ON lamp is found, it will be pulsed before the next lamp is tested. The scanning of array 10 is periodic so that ON lamps will remain on and OFF lamps will remain off so long as the memory system is operating.

Each lead has a switch 20 in series therewith, common terminals of switches 20 being connected by a lead 21 to a parallel network 22 including a resistor 24 and an ON-OFF power switch 26. Each lead 18 has a switch 28 in series therewith and switches 28 are shown as being connected to ground potential to indicate their relationship to terminal adjacent to network 22 when the latter is coupled to a voltage source.

The basic operation of assembly of FIG. 1 includes coupling terminal 30 to a voltage source while switches 20, 26 and 28 are open. Hereafter, switches 20 and 28 are sequenced, i.e., switches 20 are successively actuated when one of switches 28 is closed, switches 20 are succesively actuated when a second switch 28 is closed and so on. The resistance value of resistor 24 is maintained high enough to prevent substantial current flow through lamps 12. Thus, the small current flow through resistor 24 will not energize any of the lamps as switches 20 and 28 are sequenced.

As switches 20 and 28 are sequenced, lamps 12 are successively and individually placed in series with network 22. Thus, at any one time only a single lamp is in the circuit since only one switch 20 and one switch 28 will be closed for each operating time interval.

Switch 26 is to be closed when a lamp 12 is found to have been on and before the succeeding lamp is placed in the circuit. The ON lamp thus will receive a current pulse which will keep it in the ON state. The voltage drop across the lamp-device unit will be determined to give a measure of the resistance of the lamp and if this drop is relatively high which it will be if the lamp has been on switch 26 will be closed to pulse the lamp. In this way, an ON lamp will be remain on and an OFF lamp will remain off. The lamp itself will be its own memory cell because the heat generated by current flow through the lamp will persist for a finite time and the scanning rate can be made much smaller than the time required to allow the lamp to cool.

The apparatus for carrying out the aforesaid steps is shown in FIG. 2 wherein matrix 10 is shown in combination with a switch selection circuit 32 and a voltage sensing circuit 34. Terminal 30 and matrix 10 are connected to a voltage source. Resistor 24 and switch 26, in the form of a transistor, are shown coupled between one side of the voltage source and matrix 10. The input of voltage sensor 34 is coupled by leads 36 and 37 across matrix 10 and the output of sensor 34 is connected by lead 38 to switch 26. Selection circuit 32 provides that only a single lamp 12 is in the circuit at any one time. To this end, it includes switches 20 and 28 of FIG. 1.

If the voltage across matrix 10 is above a predetermined minimum, the output of sensor 34 actuates switch 26 and causes a current flow in bypassing relationship to bypass resistor 24. The current will flow through the lamp in the circuit only for a relatively short time since selection circuit 32 will interrupt the flow and connect the next lamp into the circuit.

If a lamp is hot, the voltage drop is higher than if the lamp is cold. The voltage sensing action is accomplished for each lamp until all lamps of matrix 10 have been tested. Then the entire operation is repeated so long as the system is in operation. Thus, only ON lamps are pulled pulsed and these remain on while OFF lamps remain off.

The lamps can be turned on in any one of a number of ways. For instance, they can be turned on manually by placing a potential across each of them. The lamps also can be turned on from a serial input using other memory by switching to a mode of operation where power switch 26 is controlled by a serial input rather than by sensor 34.

A single circuit such as shown in FIGS. 1 and 2 can accommodate up to lamps if any combination of lamps can be on. Also, more than one of these 100 lamp systems could share one set of lamp drivers, i.e., a single selection circuit 32.

The testing and pulsing of the lamps can be done at an accelerated pace and the pace can be slowed down only when a hot lamp is found. For instance, if groups of 10 lamps represent the various numbers of a decimal digit, only one of which is on at any time, only 10% of all the lamps are on at once. A scanning rate of one microsecond for each lamp can be used and this time interval is sufficient to test each lamp to determine if it is hot or cold. When a hot lamp is found, switch 26 is actuated and the scanning can be inhibited for one millisecond. Using this sequencing action array 10 could handle 1000 lamps (100 decimal digits). To scan the entire matrix would take .1 second and this is clearly insufficient time for a hot lamp to cool between pulses. In this way, each hot lamp would be pulsed at the rate of about one microsecond every .1 second which is the required 1% of the time. If the scanning rate of cold lamps is increased with respect to the duration of the current pulse applied to a hot lamp without increasing the number of lamps in the array greater lamp brightness can be had with smaller current pulse.

With logic circuitry coupled to an assembly of FIG. 2, the circuit can be made to turn on a lamp adjacent to one that has previously been on. Thus, the array can be pulsed and the light moved from one lamp to another in either direction. The assembly of FIG. 3 illustrates this concept wherein logic circuitry 42 is coupled in lead 38 to control the actuation of switch 26 in response to the output of sensor 34. It can also be arranged that after the tenth lamp in each group of 10, the first lamp is turned on again and a carry is propagated to the next group of 10 lamps. The circuit can thus be made to define a decimal counter capable of counting in either direction.

One of two things can be done to the method of scanning array 10 to simplify the logic required if the assembly is used as a bi-directional counter. The direction of counting can be reversed by reversing the direction of a part of the scan mechanism so that lamps of each digit are selected in reverse order.

Alternatively, a method of scanning can be used which selects each lamp twice. The selection for such a system, with respect to the lamp positions in a group of ten lamps, might be as follows: 2, 1, 3, 2, 4, 3, 5, 4, 6, 5, 7, 6, 8, 7, 9, 8, 0, 9, 0. Such a scheme allows the logic to base its decision as to which lamp to pulse on the observation of two adjacent lamps and allows the pulsing of either lamp since the first lamp of any pair to be selected is again selected two time intervals later. With such a scheme, the logic could add or subtract without changing the scanning.

Array can be considered a complete memory with a visual and/ or electrical output or as a display unit with an inherent memory. With associated logic, its uses can include simple displays of all types, totalizing numerical displays, and bi-directional totalizing displays. One application which takes advantage of both its memory and display functions is as a register in a calculating machine.

While one embodiment of this invention has been shown and described, it will be apparent that other adaptations and modifications can be made without departing from the true spirit and scope of the invention.

What is claimed is:

1. An electronic memory assembly comprising: a plurality of electrical resistance elements disposed in a predetermined matrix to form a series of rows and a number of columns, each element having a pair of opposed ends with one of its ends being coupled to the corresponding ends of the elements in a respective row and its opposite end being coupled to the correspondingly opposite ends of the elements in a respective column, each element having an operative characteristic capable of being changed in response to current flow therethrough; a voltage sensing unit for sensing the voltage drop across an element; a power switch coupled to and actuated by said sensing unit when said voltage drop is at least a predetermined value, said power switch adapted to be connected to a voltage source; and sequentially actuated switching structure for successively connecting said elements individually to said sensing unit and said power switch, whereby an electrical current will be caused to flow through the elements whose voltage drop is equal to at least said predetermined value and when said power switch is connected to said voltage source.

2. An electronic memory assembly comprising: a plurality of electrical resistance elements disposed in a predetermined matrix to form a series of rows and a number of columns, each element having a pair of opposed ends with one of its ends being coupled to the corresponding ends of the elements in a respective row and its opposite end being coupled to the correspondingly opposite ends of the elements in a respective column, each element having an operative characteristic capable of being changed in response to current flow therethrough; a voltage sensing unit for sensing the voltage drop across an element; a power switch adapted to be coupled to a voltage source; means coupled to said power switch for controlling the actuation of the same in response to the output of said sensing unit and in accordance with a predetermined sequence; and sequentially actuated switching structure for connecting said elements individually to said sensing unit, whereby the operative characteristics of said elements can be sensed and the power switch actuated according to said sequence.

3. An electronic memory as set forth in claim 2, where in said control means includes a counter unit.

4. An electronic memory assembly comprising: a plurality of electrical resistance elements disposed in a predetermined matrix to form a series of rows and a number of columns, each element having a pair of opposed ends with one of its ends being coupled to the corresponding ends of the elements in a respective row and its opposite end being coupled to the correspondingly opposite ends of the elements in a respective column, each element having an operative characteristic capable of being changed in response to current fiow therethrough; means coupled with each element for sensing the changed operative characteristics thereof; a power switch coupled to and actuated by said sensing means when said changed characteristic is sensed, said power switch adapted to be connected to a voltage source; and sequentially actuated switching structure for successively connecting said elements individually to said sensing means and said power switch, whereby an electrical current will be caused to flow through the elements having said changed characteristic and when said power switch is connected to said voltage source.

5. A method of operating an array of incandescent lamps, each having an operative characteristic capable of being changed in response to the flow of electrical current therethrough comprising the steps of: causing a relatively small current to flow successively through said elements and measuring the voltage drop across each element, whereby to sense the operative characteristics of successive elements to determine if the characteristic of each element has changed; and directing an electrical current through each element having a changed characteristic before the characteristic of the succeeding element is sensed.

6. A method as set forth in claim 5, wherein is included the step of controlling the flow of electrical current through each lamp having a changed characteristic in accordance with a predetermined sequence.

7. A method as set forth in claim 6, wherein said controlling step includes causing said electrical current to flow through the lamps in accordance with a counting operation.

References Cited UNITED STATES PATENTS 2,958,848 11/1960 Garwin 340-1731 3,042,823 7/1962 Willard 340l73 X 3,089,126 5/1963 Miller 340-173 3,146,426 8/1964 Agon et al 340-474 3,199,087 8/1965 Foglia 340--173.1 X 3,357,010 12/1967 Sweeney 340 -324 3,379,831 4/1968 Hashirnoto 340166- X OTHER REFERENCES I. A. Lake, Jr. Array Charging Techniques, IBM TDB, v. 8, No. 4, September 1965.

BERNARD KONICK, Primary Examiner JOSEPH F. BREIMAYER, Assistant Examiner US. Cl. X.R.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US2958848 *Feb 27, 1958Nov 1, 1960IbmSwitching circuit
US3042823 *Nov 28, 1958Jul 3, 1962IbmHigh speed electronic memory
US3089126 *Sep 8, 1959May 7, 1963Rca CorpNegative resistance diode memory
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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US3735367 *Apr 29, 1970May 22, 1973Currier Smith CorpElectronic resistance memory
US3818724 *Jun 26, 1972Jun 25, 1974Bonneterie Sa EtData programming device, particularly for control of knitting machines
US4163409 *Dec 9, 1977Aug 7, 1979Juan M. del CastilloOptical metronomes
US5629635 *Sep 26, 1995May 13, 1997Ics Technologies, Inc.Integrated circuit
Classifications
U.S. Classification365/106, 365/116, 365/100, 365/115, 365/64, 365/175
International ClassificationH03K23/00
Cooperative ClassificationH03K23/001
European ClassificationH03K23/00B