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Publication numberUS3510349 A
Publication typeGrant
Publication dateMay 5, 1970
Filing dateNov 15, 1966
Priority dateNov 15, 1966
Publication numberUS 3510349 A, US 3510349A, US-A-3510349, US3510349 A, US3510349A
InventorsJones Richard T
Original AssigneeUs Air Force
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Vacuum deposited interconnection matrix
US 3510349 A
Abstract  available in
Previous page
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Claims  available in
Description  (OCR text may contain errors)

May 5, 1970 R. T. JONES 3,510,349 I v VACUUM DEPOSiTED INTERCONNECTION MATRIX Filed Nov. 15, 1966 s sheets-sheet 1 United States Patent f 3,510,349 VACUUM DEPOSITED INTERCONNECTION MATRIX Richard T. Jones, Bedford, Mass., assignor to the United States of America as represented by the Secretary of the Air Force Filed Nov. 15, 1966, Ser. No. 594,589 Int. Cl. C23c 13/02 US. Cl. 117-212 1 Claim ABSTRACT OF THE DISCLOSURE A single apertured mask containing interconnection information is utilized with multiple vacuum depositions to provide a desired interconnection matrix.

This invention relates generally to interconnection matrices and, more particularly, to a technique or method and apparatus for forming an interconnection matrix by multiple vacuum depositions while utilizing a single, apertured mask which contains the interconnection information. One of the features which renders the technique practical is the mask method of programming, Wl'IlCh lltiliZCS separate connection and insulating units, to provide the desired information.

The problem of connecting a large number of wires to a second large group of wires, especially in digital computer applications, at first was-performed by manually wiring boards; however, this proved very cumbersome and disorderly.

Since digital computer applications do not require large currents, vacuum deposition of conductors has been found to be both practical and feasible. Previously, however, series of conductors were laid down in an orthogonal relationship with insulating material therebetween, and hole drilling together with separate connecting means between predetermined conductors was the method of manufacture utilized. Subsequently, dependent upon the circuit design, a series of special masks were utilized for depositing the conductors and insulating members. The present invention avoids the utilization of separate connectors or separate steps for making a connection between unconnected conductors, and also avoids the utilization of separate masks.

Accordingly, it is the primary object of this invention to provide a vacuum deposited interconnection matrix which is formed with a single mask.

It is another object of this invention to provide a method of vacuum deposition of an interconnection matrix which utilizes a single mask and, therefore, avoids problems of registration of multiple mask units.

It is still another object of this invention to provide a vacuum deposited interconnection matrix which is formed with a single mask whereby the mask is required to be moved in translation in a single plane.

It is a further object of this invention to provide a multiple. deposition process for producing an interconnection matrix.

It is a still further object of this invention to produce a multiple evaporation process for manufacturing interconnection matrices whereby a single, apertured mask is utilized, and material which passes through the aperture in the mask is deposited on a substrate in a pattern corresponding to the aperture pattern matrix.

Another object of this invention involves the production of insulating units and connecting units which may be combined to form a pattern of interconnection between wires of an interconnection matrix.

Still another object of this invention involves a technique for making interconnection matrices which utilizes 3,510,349 Patented May 5, 1970 conventional, currently available materials which lend themselves to standard mass production manufacturing techniques.

These and other advantages, features and objects of the invention will become more apparent from the following description taken in connection with the illustrative embodiments in the accompanying drawings, wherein:

FIG. 1 is a representation of the aperture arrangement of an insulating unit;

FIG. 2 is a representation of the aperture arrangement of a connecting unit;

FIG. 3 is a 2 x 2 mask pattern aperture arrangement; and

FIGS. 4 through 7 are schematic representations of the successive deposition sequences utilizing the mask of FIG. 3.

When a large number of wires which are spaced and orthogonally related are required to have connections at various points, these points may be designated as connection intersections. At each connection intersection of a two dimensional gridwork of conductors the crossed wires may be either connected or insulated one from the other. It is contemplated that the production of an interconnection matrix could be formed by depositing conducting material and insulation through a single mask with provision being made for translation thereof.

Referring to FIG. 1, there is shown an aperture pattern for an insulating unit. As can be seen from the figure, the horizontal and vertical apertures, represented by the cross hatched areas, are not connected to each other. In FIG. 2, however, the horizontal aperture is not segmented and forms a single aperture across the entire unit. The vertical aperture, however, is broken or segmented.

When a gridwork of orthogonally related conductors for a computer matrix has been decided upon, at each intersection of the conductors, either an insulating unit of FIG. 1 or a connecting unit of FIG. 2 Would be placed, thereby forming the mask to be utilized in applicants process.

The length S and the width W of each aperture are fixed and the proportions are approximately S=.30D and W=.10D, where D is the edge dimension of the unit. FIG. 3 illustrates an example of a mask pattern produced by combining four units such that the upper left and lower right intersections of the resulting matrix would be connected. The upper left and lower right areas are represented by the connecting units of FIG. 2 while the remaining areas for unconnected conductors are represented by the insulating units of FIG. 1.

The first step, therefore, in making the aperture mask, is to produce a master copy of the aperture pattern in which the apertures are represented by opaque tape on a translucent background. The master is then photographed using black lighting and a film positive of the desired magnification is made from the negative. The positive is placed in contact with a photo-resist coated piece of 0.001 inch thick brass and ultra-violet light is used to expose the photo-resist. Development removes the photoresist from the unexposed areas where the apertures are to be. The mask is then etched until the apertures appear. The residual photo-resist coating is dissolved leaving only the brass mask which contains the completed aperture pattern.

The method for producing an interconnection matrix using only a single mask involves three conductor evaporations and one insulation evaporation. This scheme is the heart of this technique. The number of evaporations will be the same regardless of the number of unit cells in the pattern since the number of conductors and the connection pattern are functions only of the mask design.

Specifying the mask location with respect to the substrate, the operational sequence is as follows:

- 3 Step 1.-With the mask of FIG. 3 at location x, y, in Cartesian coordinate system deposit conductor.

Step 2.--Translate mask to location x, yd/ 2, deposit conductor.

Step 3.-Without changing the y-location of the mask (yd/2), deposit insulation while changing the x-location from approximately x-.Od to x+.05d.

Step 4.--Translate the mask to x+d/ 2, y, deposit conductor.

FIGS. 4-7 represent the successive depositions upon a substrate which would result from the use of the mask of FIG. 3. FIG. 4 represents the step 1 conductor deposition, while FIG. 5 is the resultant of the addition of step 2 which forms the continuous vertical conductors and all connected intersections. FIG. 6 illustrates the deposition of insulation 12 to FIG. 5, and FIG. 7 completes the horizontal conductors 10 across the insulated intersections. In the resultant pattern, use is made of the two continuous vertical conductors and the two continuous horizontal conductors only. The other deposits, which are superfluous, are introduced by the use of a single mask with this operational sequence. I

In the production of the matrix, the mask and substrate were mounted about 12 inches above the evaporation sources, and a moving table with conventional micrometer drive in two dimensions was used to introduce the necessary translating between the mask and substrate. Operation of the translations preferably are performed without a break in the vacuum for the successive depositions. Examples of materials capable of being used in the manufacture of the matrices include glass substrates, silicon monoxide evaporated insulation, and aluminum or chrome-gold evaporated conductors. A substrate heater should also be provided so that insulation may be deposited at elevated temperatures. The aluminum is evaporated from tungsten filaments while chromium and gold are evaporated from resistance heated crucibles.

The size of the mask in the drawings is merely illustrative in that the invention is capable of miniaturization with a large number of horizontal and vertical conductors. The limit of conductors per matrix is dependent only upon the photo-etch techniques for making the apertures. Provision also be can be made for connection tabs to the conductors. Additionally, various materials, other than those specified, are capable of utilization for the conductors and insulators.

. 4 I claim: 1. A process for forming an interconnection matrix from a single, apertured mask wherein the mask is provided with insulating aperture patterns and connecting aperture patterns located in accordance with a grid of pairs of parallel, orthogonally oriented, elongated conductors oriented parallel With a Cartesian coordinate system axes,'the aperture forming the insulating patents being provided for each intersection of conductors where there is to be no connection and the connecting aperture patterns for the intersections where connection is desired comprising the steps of vacuum depositing a conductive material through the apertures of said mask with said mask in a first position to provide segmented orthogonally related conductors,

translating said mask in one direction parallel with one axis of the Cartesian coordinate system and depositing conductive material through the apertures of said mask to provide continuous, elongated conductors parallel with the said one axis, by bridging the previously deposited segmented conductive material which is oriented along said one axis,

translating said mask orthogonally to said one directio and simultaneously depositing insulative material through the apertures of said mask, and

translating said mask to a position displaced from said first position along the other axis of said Cartesian coordinate system whereby said segmented conductive material parallel with said other axis which was deposited when said mask was in its first position are bridged by like oriented apertures in said mask, and depositing conductive material through said apertures of said mask for completing the first deposited conductors parallel to the other axis of the Cartesian coordinate system.

References Cited UNITED STATES PATENTS ANDREW G. GOLIAN, Primary Examiner US. Cl. X.R.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US3023727 *Sep 10, 1959Mar 6, 1962IbmSubstrate processing apparatus
US3205855 *Aug 28, 1961Sep 14, 1965Clifford M AultCoating apparatus for producing electrical components
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US4100313 *Oct 28, 1975Jul 11, 1978Rca CorporationProcess for forming an optical waveguide
US4273812 *Feb 1, 1979Jun 16, 1981Hitachi, Ltd.Method of producing material patterns by evaporating material through a perforated mask having a reinforcing bridge
US4335161 *Nov 3, 1980Jun 15, 1982Xerox CorporationThin film transistors, thin film transistor arrays, and a process for preparing the same
US4408875 *Dec 31, 1981Oct 11, 1983Fujitsu LimitedMethod of projecting circuit patterns
US4511599 *Mar 1, 1983Apr 16, 1985Sigmatron AssociatesMask for vacuum depositing back metal electrodes on EL panel
US4615781 *Oct 23, 1985Oct 7, 1986Gte Products CorporationMask assembly having mask stress relieving feature
US4715940 *Oct 23, 1985Dec 29, 1987Gte Products CorporationMask for patterning electrode structures in thin film EL devices
US4746548 *Oct 23, 1985May 24, 1988Gte Products CorporationMethod for registration of shadow masked thin-film patterns
US4915057 *Nov 14, 1986Apr 10, 1990Gte Products CorporationApparatus and method for registration of shadow masked thin-film patterns
EP0051396A2 *Oct 21, 1981May 12, 1982Xerox CorporationProcess for preparing thin film transistor arrays
EP0051396A3 *Oct 21, 1981Jun 22, 1983Xerox CorporationThin film transistors, thin film transistor arrays, and a process for preparing the same
EP0118576A1 *Mar 11, 1983Sep 19, 1984Hitachi, Ltd.Method for forming thin films
U.S. Classification427/96.8, 427/282, 427/97.3, 118/504
International ClassificationH05K3/14, C23C14/04
Cooperative ClassificationC23C14/042, H05K3/14, H05K3/143
European ClassificationC23C14/04B, H05K3/14B, H05K3/14