|Publication number||US3510865 A|
|Publication date||May 5, 1970|
|Filing date||Jan 21, 1969|
|Priority date||Jan 21, 1969|
|Publication number||US 3510865 A, US 3510865A, US-A-3510865, US3510865 A, US3510865A|
|Inventors||Callahan Thomas T, Worters Allen J, Zambuto Domenic A|
|Original Assignee||Sylvania Electric Prod|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Referenced by (26), Classifications (9)|
|External Links: USPTO, USPTO Assignment, Espacenet|
May 5, 1970 1-. T. CALLAHAN ETAL v3,510,365
- A 1 DIGITAL VECTOR GENERATOR I Filed Jan. 21. 1969 I 3 sheetssheet 2 COMPOSITE PULSE TRAIN GATE 2 I GATE 2' GATING GATE 2 LEVELS GATE 2 FROM GATE 2 AXGIAY n REGIsTERs GATE 2 O l 2 3 4 2 PULSES 2 PULSES ZPULSES ZPULSES 2 PULSES Z PULSES PULSE GROUPS FROM CLOCK PULSE GENERATOR 4 FIG.3A IIIIIII|II'IIIIII 3 I PULSE 2 I l I I I I l GROUP SPACING 22 I I I I T IME FOR ONE CYCLE OF CLOCK PULSES 38 REGISTER ALL PULSE GROUPS GATEDTHR'U IIIIIlIIIIIIIIIIIIIIIIIIIIIIIIII RATE MULTIPLIER FIG.3C
ZAZZMIPULSE I II III III III III III III I GROUPS GATEG THRU RATE MULTIPLIER INVENTOR. ALLEN J. woRTERs BY DOMENIC A.ZAMBUTO THOMAS T. CALLAHAN 8W4 yAGENT May 5,1?10 'r.'r. GALLAHAN ERTAL I "3,510,865
DIGITAL VECTOR GENERATOR Filed Jan; 21, 1969 s Sheds-Sheet 3 TO RATE MULTIPLIERS FROM 1 AX ANDAY REGISTERS Fl. IF-FLOP F .lP-FLOP FLIP-FLOP FLIP-FLOP a o o o Q R iao la! 52 163 I v c 6 0' 6 FROM R R R R OSCILLATOR RFSET 42 FROM TIME REGISTER 4! FIG. 4
PULSE GROUP 2, FL I 1 F1 FL F1 PULSE GROUP 2 1 TI PULSE GROUP 2 Fl PULSE GROUP 2' v L INVENTORS ALLEN J. WORTERS BY DOMENLC 'A.ZAMBUTO THOMAS TICALLAHAN al- J 1 4 fl y AGENT United States Patent US. Cl. 340-324 9 Claims ABSTRACT on THE DISCLOSURE A digital vector generator employing a source of digital signals representing the starting point, direction and length of the vector to be displayed on a cathode ray tube (CRT). Digital logic converts the direction and length signals into pulse trains having varying time scales and varying numbers of pulses, both of which are. substantially proportional to the vector length. The pulse train is combined with the starting point signals and converted to an analog signal for display on the CRT.
CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation-in-part of copending application Ser. No. 593,193, filed Nov. 9, 1966, now abandoned.
BACKGROUND OF THE INVENTION This invention is concemed with display systems and, in particular, with a system for digitally generating vectors for display on such devices as cathode ray tubes (CRT).
Many dynamic display systems presently available for presentation of graphical, tactical or other data employ analog techniques, andif the display system is to be linked to a digital computer or other processor, specific interface circuitry must be designed to suit the particular installation. These analog circuits, in addition to being rigid in design, must be tailored to the speed, resolution or linearity required in particular instance. It wou d be advantageous to have, and it is an object of this invention to provide, a simple and versatile display system for operation with high speed digital processing equipment and which is easily adaptable to varying system parameters.
BRIEF DESCRIPTION OF THE INVENTION Briefly, a digital vector generator according to the present invention comprises a digitally controlled display system operative to generate and display vectors on a display device such as a CRT. Digital information representing the starting point, magnitude and direction of a vector is provided by a suitablesource such as a digital computer. Connected to the computer is a pulse train generator which converts the digital information representing the vector magnitude from the computer into pulse trains in which the numbers of pulses and the time bases are both substantially proportional to the vector magnitude thus insuring that the writing speed and intensity of the CRT will be constant for long and short vectors. A summing means, for example, UP/ DOWN counters, adds the vector direction and magnitude information from the pulse train generator to the starting point information already stored in the summing means. The digital output signal from the summing means is converted to the necessary signal format for display.
BRIEF DESCRIPTION OF THE DRAWINGS This invention will be more fully described in the following detailed description read in conjunction with the accompanying drawings, wherein:
3,510,865 Patented May 5, 1970 FIG. 1 is a block diagram of the digital vector generator system;
FIG. 2 is a block diagram of a digital rate multiplier useful in the system of FIG. 1;
FIGS. 3A, 3B and 3C are timing diagrams useful in explaining the operation of the rate multiplier of FIG. 2;
FIG. 4 is a block diagram of a clock pulse register employed in the vector generator of FIG. 1; and
FIG. 5 is a time diagram useful in explaining the operation of the clock pulse register of FIG. 4.
DETAILED DESCRIPTION OF THE INVENTION The requirement of a vector generator is to move a CRT beam from a vector starting point (X, Y) to its end point (X +AX, Y+AY). This requirement may be broken down into three separate requirements:
(1) during the writing time of the vector, the X and Y components must be counted up (or down) by pulses equal in number to the binary value of the respective components;
(2) the pulses used to increment the X and Y components must be spread evenly within the writing time of the CRT so that the vector will be smooth and so that the end point of the components will be reached together; and
(3) the writing time of the vector should be substantially proportional to the magnitude of the vector so that the writing speed will be constant and the intensity equal for long and short vectors.
Referring to FIG. 1, a preferred embodiment of the present invention which realizes these requirements comprises a display unit 10 including a CRT 12, horizontal and vertical deflection amplifiers 14 and 16 and digital to analog converters 18 and 20. To provide the vector starting point, direction and length, a source of digital signals, such as a computer 22, is connected to X and Y summing means such as UP/DOWN counters 24 and 26, respectively. A pulse train generator 11, to be explained in detail hereinafter, has AX and AY inputs from the computer 22 and AX and AY output connections to the respective UP/DOWN counters 24 and 26.
In operation, digital information representing the starting point of a vector to be displayed is supplied from the computer 22 as a reference to the UP/DOWN counters 24 and 26, and information, AX and AY, indicative of direction and length of the vectors, is directed to the pulse train generator 11. For each component of the vector, the pulse train generator 11 converts the length information into a pulse train wherein the number of pulses and time base of the pulse train are proportional to the length. Each pulse train is then directed to the appropriate UP/DOWN counter where it is combined with the starting point information. The UP/ DOWN counters 24 and 26 accept the pulse trains and either count up or down according to the sign in the AX and AY registers 28 and 30. A digital output signal from each UP/ DOWN counter is directed to the appropriate deflection plate of the CRT 12 via its respective D/A converter and deflection amplifier.
The pulse train generator 11 includes a pair of storage devices, for example, AX and AY registers 28 and 30, having input connections from the computer 22. Gating means such as rate multipliers 34 and 36 have first input connections from the respective AX and AY registers 28 and 30 and second input connections from a clock pulse generator 31, to be discussed in detail hereinafter. The output connections from the rate multipliers 34 and 36 are connected to the respective X and Y UP/ DOWN counters 24 and 26. Also connected to the AX and AY registers 28 and 30 and to the clock pulse generator 31 is an output connection from control logic 32, also to be discussed in detail hereinafter.
As stated hereinabove, the information representing the starting point of the vector is supplied from the computer 22 to the X and Y UP/DOWN counters 24 and 26, and the information indicative of direction and length, AX and AY, of the vectors are applied to the AX and AY registers 28 and 30. Control logic 32 strobes the data from the computer into registers 28 and 30 where it becomes available to respective rate multipliers 34 and 36 which are operative to generate pulse trains representing the binary numbr in the registers 28 and 30. These pulse trains are transferred to respective UP/DOWN counters 24 and 26 where the starting point information is stored.
The rate multiplier is shown in greater detail in FIG. 2 and includes a plurality of AND gates 40 whose outputs are connected to corresponding inputs of an OR gate 142. The input from the clock pulse generator 31 provides pulse groups where the number of pulses on each line are of increasing binary significance, i.e., 1, 2, 4, 8 Each pulse group is applied to a corresponding input line of the several gates 40 and in the time sequence shown in FIG. 3A. The second set of input lines to gates 40 provide gating levels from respective AX and AY registers to control which of the pulse groups are allowed to pass through their respective AND gates 40 to the OR gate 142. The output of the OR gate is then a composite pulse train representing the magnitude of the stored component.
FIG. 3B shows a composite train that would appear at the output of OR gate 142 if the vector in the AX register 28 were of the maximum magnitude; that is, all the pulse groups were gated through the AND gates 40. FIG. 3C shows a composite pulse train that results if pulse groups 2 2 and 2 are passed through their respective AND gates 40 by gate pulses occurring at the corresponding gating inputs. The pulse groups which are passed are then combined in OR gate 142 to form the composite pulse train representing the magnitude of the component.
To provide a smooth vector display on the CRT, the pulse group representing each component must be evenly spread throughout the writing period or illustrated, for example, in FIGS. 3B and 3C. This even pulse spread is accomplished by means of the clock pulse generator 31 which is operative to gate the pulse groups out in the time sequence shown in FIG. 3A. It can be seen that no two pulses occur at the same time and that the number of pulses comprising each binary level 2 2 etc., are spread evenly over one clock period. By arranging the pulses such that no pulses in one pulse group occur at the same time as a pulse in another pulse group, the pulse groups may be added to form a pulse train without an overlap of any pulses. By spreading the number of pulses in each pulse group evenly over the time'for one cycle, any combination of pulse groups will produce a vector display spread evenly in time.
The clock pulse generator 31 includes an oscillator 42- connected to a clock pulse register 38. Also connected to the clock pulse register 38 are input connections from the respective AX and AY registers 28 and 30 and a time register 41 such as a well-known ripple counter which, in turn, has an input connection from the control logic 32. One embodiment of the clock pulse register 38, shown in FIG. 4, is a binary counter including a plurality of fiipflops, four of which are shown for illustration purposes, 160-163, each having first and second output connections and an input connection. Associated with each flop-flop 160-163 is a respective AND gate 200-203. Each AND gate 200-203 has input connections from a gate 150, the first output connection of its associated flip-flop and the second output connections of all the preceding flip-flops in the chain. The trigger input connection, C for each of the flip-flops 161-163, is connected to the first output connection of the preceding flip-flop in the chain. The gate 150 has input connections from the oscillator 42, the AX and AY registers and the time register 41, and output connections to each AND gate 200-203 and the trigger input terminal C of flip-flop 160.
The timing diagram of FIG. 5 may be employed in conjunction with FIG. 4 to understand the operation of the clock pulse register 38. As indicated in the timing diagram, with every input pulse from the oscillator 42 passed through gate 150, the binary counter including the flip-flops 160-163 is incremented to the next binary state. For example, the AND gate 200, associated with the lowest ordered flip-fiop 160, passes the input count pulse from the oscillator 42 whenever its associated flip-flop 160 is reset thus producing the pulse group 2 The next AND gate 201, associated with the next higher flip-flop 160, passes the input count from the oscillator 42 when the flip-flop 161 is reset and the lower order flipflop 160 is set. The result is a second pulse group 2 appearing at the output terminal of gate 201 and having a frequency of half the previous one, 2 offset by one oscillator pulse. As shown in FIG. 5, the same pattern continues for each flip-flop and gate in the clock pulse register 38. The input pulses from the oscillator 42 are passed when the flip-flop associated with an AND gate is reset and all previous lower order flip-flops are set. This results in each successive pulse group being half the frequency of the previous one and offset by one count from the previous group thus yielding the desired input signal to the rate multipliers 34 and 36, as shown in FIG. 3A.
The gate has two enabling signals, both of which are necessary to pass the oscillator signal and thereby activate the clock pulse register 38. One enabling signal indicates the end of the normalizing operation, to be explained in detail hereinafter, and may originate from the most significant bit positions of the AX and AY registers 28 and 30. A binary ONE shifted into the most significant bit position of either of the AX and AY registers 28 or 30 will produce the enabling signal. The second signal originates in the time register 41 and is removed when the time register count reaches zero. The time register 41 is a simple counter having a preset stored number from which it counts down to zero. The number stored in the time register 41 is related to the maximum number of pulses required from the clock register 38. Thus, the clock pulse register 38 is enabled from the end of the normalizing cycle to the instant the time register 41 is counted down to zero.
The system described thus far would succeed in drawing vectors or lines on the CRT 12 by loading the starting point information in the UP/ DOWN counters 24 and 26, loading the magnitude and direction data into the AX and AY registers 28 and 30, and the enabling the clock pulse register 38 to produce the requisite pulse groups. The appropriate pulse groups are directed to X and Y UP/ DOWN counters 24 and 26 by the respective rate multipliers 34 and 36. The operation described thus far would result in all vectors being written on the CRT 12 in the same length of time resulting in the writing rate on the CRT to vary over a range that may be larger than 1000: 1.
To write all vectors in a time which is substantially proportional to the length of the vector, normalization is introduced before the clock pulse register 38 is enabled. Normalization is accomplished by shifting the data in the AX and AY registers 34 and 36 one bit at a time towards the most significant bit position in each register. If no other action were taken, with each shift of the AX and AY registers 28 and 30 twice as many pulses would appear in the composite pulse trains appearing at the output of the rate multipliers 34 and 36 as would normally occur for a vector of a given magnitude. However, part of the normalization is to shift the value in the time register 41 one bit towards the least significant binary position which results in the clock register 38 being enabled for one half the time. Given a fixed frequency of operation as set by oscillator 42, the time to count a number, n/Z, down to zero is half the time required to count a number, n, down to zero. Since the clock pulse register 38 is only activated during the period of time that the time register 4 is counting down to zero, with each shift pulse during normalization the time that the clock pulse register 38 is activated will be cut in half. By shifting the time register 41 concurrent with shifting the AX and AY registers, the same number of pulses appear in the composite pulse trains, but the period of time is halved with each shift. This normalization is repeated until a ONE is detected in the highest order bit position of either the AX register 28 or the AY register 30.
Normalization does not change the number of pulses in the composite pulse trains. It does change the length of time in which these pulses occur. If T is the maximum length of time required to draw the longest line, then the time utilized to draw any line is T/m' where m is the number of shift pulses during normalization. If the longest line is kT where k is a simple proportionality constant,
then it would be desirable for the length of the line drawn in time T/ml to be kT/m Normalization does not produce this result exactly but instead draws lines in time T/m which vary from .SkT/m to /2IcT/m. The variation, 2.8: l, is a significant improvement over the 1000z1 range present before normalization and may be said to represent a substantial proportionality between line length and the line writing time.
One embodiment of the control logic 32 which may be employed to accomplish the required shifting for normalization is shown in FIG. 1 and includes a strobe 50 having a first output connection to the computer 22 and a second output connection to a first flip-flop 52. A first gate 56 has an input connection from the first flip-flop 52 and input connections from the AX and AY registers 28 and 30. A second flip-flop 58 has an input connection from the first gate 56 and an output connection to a second gate 60. A second input connection to the second gate 60 comes from a clock.
In operation, the signal from the strobe 50 is sent to the computer 22 to load the UP/DOWN counters 24 and 26 and the AX and AY registers 28 and 30. After the data is received, the strobe sends a signal to the first flip-flop 52 which, in turn, supplies an input signal to the first gate 56. The other two inputs to the first gate 56 originate at the ONE output of the most significant bit position in the AX and AY registers 28 and 30. If neither the AX register 28 or the AY register 30 have a ONE in the most significant bit position, the clock pulses are passed through the second gate 60 to the AX and AY registers 28 and 30 and the time register 41 as a series of shift pulses to normalize the data as explained hereinabove. When a ONE appears in the most significant bit position of either the AX orAY registers 28 or 30, it passes through the first gate 56 and resets flip-flop 58 which, in turn, inhibits the second gate 60 blocking the clock signal and thus stopping the shift pulses to the time register 41 and the AX and AY registers 28 and 30. When normalization is thus ended, the pulses from oscillator 42 are passed to the clock pulse register 38 to produce the pulse groups and to the time register 41 counting it down towards zero. For as long as the time register is still nonzero, the pulse groups are produced, combined into composite trains, and used to count up or down the starting poistion values in the AX and AY registers 28 and 30, thus describing the line as it moves from its original position (X, Y) to its final position (X+AX, Y+AY).
From the foregoing, it is evident that a digital vector display system has been provided which is simple in construction and extremely flexible. The system is adaptable to larger or smaller displays by merely adding to or subtracting from the length of the various registers, and it may be made faster or slower merely by changing the frequency of the clock.
What is claimed is:
1. A digital vector generator comprising:
a source of digital signals representing the starting point, direction and length of a vector to be displayed;
means for generating pulse trains in response to the digital signals representing the length of the components of the vector from said source of digital signals, each of said pulse trains having a number of pulses proportional to the length of the component and having a time base, said number of pulses being substantially evenly distributed within said time base;
summing means having input connections from said source of digital signals and from said means for generating pulse trains and being operative in response to the digital signal representing the starting point from said source of digital signals and to the pulse trains from said means for generating pulse trains to generate a composite digital signal, representing the vector; and
display means connected to said summing means and being operative in response to the composite digital signal from said summing means to display said vector.
2. A digital vector generator according to claim 1 wherein said means for generating pulse trains includes: first storage means having a most significant bit position and being operative to store the digital signals representing the direction and length of a first of the vector components from said source of digital signals;
a clock pulse generator having a plurality of output terminals and being operable to generate pulse groups, each pulse group being of increasing binary significance and each group being uniformly spaced in time; and
first gating means having input connections from said first storage means and said clock pulse generator and being operative in response to the signals from said first storage means and said clock pulse generator to generate a pulse train in which the number of pulses is proportional to the length of said first vector component.
3. A digital vector generator according to claim 2 wherein said clock pulse generator includes:
an oscillator operative to generate a series of pulses at a fixed rate;
counting means operative to count down to zero from a predetermined reference number stored in said counting means and to generate a control signal when the count reaches zero; and
clock pulse register means having input connections from said oscillator, said counting means and said first storage means, and a plurality of output connections to said first gating means, said clock pulse register means being operative in response to the pulses from said oscillator to generate a plurality of pulse groups, each pulse group occurring on one of the plurality of output connections and being of increasing binary significance and uniformly distributed over a predetermined time interval such that no two pulses of said plurality of pulses occur simultaneously, said clock pulse register means being operative to generate said pulse groups when a predetermined signal is received from said first storage means and in the absence of the control signal from said counting means.
4. A digital vector generator according to claim 3 wherein said clock register means includes:
second gating means having input connections from said first storage means, said oscillator and said counting means, said second gating means being operative to pass the output signal from said oscillator when a signal is received from said first storage means and to inhibit the oscillator signal when a control signal is received from said counting means;
a plurality of serially connected flip-flops, each having an input connection and first and second output connections, said first output connection being connected to the input connection of the preceding flip-flop, the first of said plurality of flip-flops having its input connection connected to the second gating means; and
a first plurality of AND gates, each of which is associated with one of said plurality of serially connected flip-flops and each of which has input connections from the second gating means, the second output connection of its associated flip-flop and the first output connection of each preceding flip-flop, each of said AND gates being operative to pass the output signal from said second gating means upon coincidence of signals at its input connections.
5. A digital vector generator according to claim 2 wherein said first storage means is a shift register having a plurality of stages and wherein said first gating means includes:
a second plurality of AND gates, each having a first input connection from one of the stages of said first storage means and a second input connection from one of the plurality of output terminals of said clock pulse generator, each of said AND gates being operable to pass its Iespective pulse group from said clock pulse generator when a ONE is stored in its respective stage of said shift register; and
an OR gate having input connections from each of said second plurality of AND gates and being operative to pass all pulse groups appearing at its input connection whereby a composite digital pulse train representing the length of the first component of the vector is generated.
6. A digital vector generator according to claim 2 wherein said means for generating pulse trains further includes normalizing means connected to said first storage means and to said clock pulse generator for adjusting the time base of said pulse trains to be substantially proportional to the length of the vector component.
7. A digital vector generator according to claim 6 wherein said normalizing means includes:
logic means having an input connection from said first storage means, a first output connection to said first storage means and a second output connection to said clock pulse generator, said logic means being operable to supply a series of shift pulses to said first storage means and to said clock pulse generator, said first storage means being operative in response to the shift pulses from said logic means to shift the digital information towards the most significant bit position and said clock pulse generator being operative in response to each shift pulse from said logic means to half the time of each output pulse group whereby the number of pulses in each of said pulse groups is constant for a given vector component length.
8. A digital vector generator according to claim 7 wherein said logic means includes:
a clock operative to generate a series of shift pulses;
third gating means having an input connection to said clock and an output connection to said first storage means and to said clock pulse generator, said third gating means being operative to pass the shift pulses from said clock to said clock pulse generator and to said first storage means; and
inhibiting means having an input connection from said first storage means and being operative in response to digital information in the most significant bit position of said first storage means to inhibit the third gating means.
9. A digital vector generator according to claim 1 wherein said summing means includes UP/ DOWN countters operative to store the starting point information of the vector to be displayed, said UP/ DOWN counters being operative to add the pulse trains from said means for generating pulse trains to the starting point information to form a composite digital signal representing the vector to be displayed.
References Cited UNITED STATES PATENTS 3,018,045 1/1962 Poland 235150.53 3,205,344 9/1965 Taylor et al. 340324.1 3,238,462 3/1966 Ballard et al. 32872 3,404,394 10/1968 Bassett 340324.1 3,422,304 1/1969 Thorpe 31518 JOHN W. CALDWELL, Primary Examiner M. M. CURTIS, Assistant Examiner US. Cl. X.R. 3l5-18
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|International Classification||G09G1/06, G06F7/68, G06F7/60, G09G1/10|
|Cooperative Classification||G06F7/68, G09G1/10|
|European Classification||G09G1/10, G06F7/68|