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Publication numberUS3515906 A
Publication typeGrant
Publication dateJun 2, 1970
Filing dateJul 1, 1966
Priority dateJul 1, 1966
Publication numberUS 3515906 A, US 3515906A, US-A-3515906, US3515906 A, US3515906A
InventorsGeller William
Original AssigneeGen Telephone & Elect
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Bilateral analog switch
US 3515906 A
Abstract  available in
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Claims  available in
Description  (OCR text may contain errors)

June 2,1970 w. GELLER 3,515,906

BILATERAL ANALOG SWITCH Filed July 1, 1966 IO 2 Sheets-Sheet 1 VOLTAGE I/VVENTOR WILLIAM GELLER *K. .fF

ATT

RNE Y June 2, 1970 V w. GELLER 3,515,906

BILATERAL ANALOG SWITCH Filed July 1, 1966 2 Sheets-Sheet 2 Fig. 3.

OFF LEAKAGE CURRENT AT 20V (microomperes) TEMPERATU RE ("C) INVENTOR WILLIAM GELLER f lm 4770 IVEX United States Patent 01 3,515,906 BILATERAL ANALOG SWITCH William Geller, Plainview, N .Y., assignor to General Telephone & Electronics Laboratories Incorporated, a corporation of Delaware Filed July 1, 1966, Ser. No. 562,280 Int. Cl. H03k 17/00 US. Cl. 307-255 3 Claims ABSTRACT OF THE DISCLOSURE A bilateral switch which provides sustained operation in both open and closed states. Elimination of offset voltages is accomplished by providing a voltage divider in conjunction with a pair of voltage sources which establish a voltage gradient across the voltage divider.

This invention relates to a bilateral analog switch which provides sustained operation in both the open and closed states.

A bilateral analog switch is a device which, under a first set of conditions, provides a relatively low impedance path between two terminals for analog signals of either polarity, and, under a second set of conditions, provides a relatively high impedance path therebetween. When the switch provides a low impedance path, it is in the closed or ON state. Conversely, when the switch provides a high impedance path, it is in the open or OFF state.

Analog switches are presently being employed in pulse code modulation (PCM) encoders and decoders wherein pulse amplitude modulated (PAM) signals are converted into and transmitted as a series of pulses characterizing the polarity and magnitude of the PAM signal. One type of encoding and decoding apparatus is described in my copending application Ser. No. 382,090 filed July 13, 1964. The apparatus described therein utilizes a network of attenuators connected in tandem between a reference voltage and an output terminal. The PCM signal is provided by removing and inserting selected attenuators in the network until, upon comparison, the voltage appearing at the output closely approximates the PAM signal. The removal and insertion of the attenuators is accomplished by the use of analog switches having the capability of sustained operation in both the ON and OFF states.

The switches so employed are required, due to the bilateral nature of the PAM signals, to provide ON and OFF state impedances which are independent of the direction of current flow. Also, the switches are required to make rapid transitions between the ON and OFF states with minimized transient eifect. These performance needs are due to the fact that the PAM signal approximation generated for comparison by the coding apparatus necessitates a large number of switching operations ina relatively short interval of the order of a few microseconds. Further, PCM systems are provided with nonlinear coding characteristics wherein the approximations for low amplitude PAM signals are more heavily weighted so that any error introduced by transients may significantly alter the PCM signals so generated.

The reliance of PCM coding apparatus upon a comparison of the original PAM signal and a PAM signal approximation in order to generate a PCM signal requires that the switches employed therein be adjustable to initially obtain an essentially zero oif-set voltage. This minimized off-set voltage should be independent of the direction of 3,515,906 Patented June 2, 1970 current flow and remain essentially constant with variations in temperature.

In practice, analog switches normally comprise a pair of transistors connected in a back-to-back configuration. The back-to-back configuration refers to a switch wherein Y the transistors are connected in series by the direct connection of the emitters or collectors of the individual transistors. For low voltage applications wherein the signal voltages do not exceed 5 volts, the collectors of the transistors are connected with the switching signal being applied across a transformer having its secondary winding coupled between the collectors and bases of the transistors. This type of switching is known as inverted mode operation.

The inverted mode operation, wherein the switching signal is applied between the collector and base, is characterized by the interchanging of the normal short-circuit current gain [3 and the inverse ,8. As a result, the individual oif-set voltages in this mode are inverse functions of the transistor fls, rather than the inverse fis. Since the inverse [3 of a transistor is typically about one-tenth of the normal ,6, the net off-set voltage of this switch is the difference between two relatively small voltages and is usually less than 1 millivolt. However, accompanying the low off-set voltage is the limitation imposed on the hold-off voltage of the switch by the reverse base-emitter rating of the transistor. Since the signal to be switched appears across this junction when the switch is in the OFF or open state, the use of this switch is limited to low-voltage applications, for example, less than 5 volts.

The back-to-back configuration in which the emitters of the two transistors are connected to each other enables the switch to withstand relatively high voltages when in the OFF or open state. This is due to the fact that the signal to be switched appears across the collector-base junction of the transistor. The ability of this type of switch to operate at higher voltages is gained at the expense of the net off-set voltage, which now is determined by the inverse fls of the transistors and is in the range of several millivolts.

As discussed above, the back-to-back switches suffer from either a low voltage rating or a relatively high net ofi-set voltage. In addition, both types of switch have at least one transistor which experiences the flow of current in the inverse direction between the emitter and collector. Thus, the current gain obtainable is determined by the inverse ,8 of the transistors and therefore limited. More significantly, the use of a transformer in the base circuit of these switches renders them incapable of sustained operation in the ON or closed state, since the switching signal applied across the transformer subsequently decays toward zero.

Another type of analog switch which is capable of bilateral operation employs four diodes. The diodes are connected in a bridge-type configuration to form a fourterminal network in which one diode is connected between adjacent terminals. While the polarities of the diodes are such as to provide sustained bilateral operation, none of the elements incorporated in the switch can provide gain so that the gain of the switch is always less than one. The nature of the bridge circuit requires that a circulating current greater than the magnitude of the current from the signal to be switched be provided.

In addition, isolation impedances are coupled between the switch and the switching signal source in order to inhibit the flow of parasitic components of the signal to be switched. These impedances result in a further reduction of the gain of the switch. Also, the off-set voltage of the switch is determined by how closely the characteristics can be matched over a wide temperature range.

Accordingly, an object of the present invention is the provision of a bilateral analog switch capable of providing gain and sustained operation in both the ON and OFF states.

Another object is to provide a bilateral analog switch having improved gain.

Still another object is to provide a bilateral analog switch having a substantially zero off-set voltage over a wide range of operating conditions.

Yet another object is to provide a bilateral analog switch which is capable of adjustment to provide a substantially zero oif-set voltage without requiring the use of matched components.

A further object is to provide a bilateral analog switch having an improved transient response.

In accordance with the present invention, a bilateral analog switch is provided which comprises a first asymmetrically conductive means having third, fourth and fifth terminals and a second asymmetrically conductive means having sixth, seventh and eighth terminals. The :first means is poled to pass current flowing from the third to fifth terminals, while the second means is poled to pass current flowing from the eighth to sixth terminals.

The first and second mean are coupled between first and second terminals in the following manner; the third and sixth terminals are coupled to the first terminal and the fifth and eighth terminals are coupled to the second terminal. The first and second means are rendered conductive by the application of switching signals to the fourth and seventh terminals respectively. When so rendered, the first means provides a low impedance path between the first and second terminals for current flowing from the first to second terminals. Also, the second means provides a low impedance path between the first and second terminals for current flowing from the second to first terminals. Thus, the concurrent application of switching signals to the fourth and seventh terminals provides bilateral switching.

In the absence of the switching signals, the first and second mean are nonconductive, i.e. in their high impedance state, so that the switch is in its open or OFF state. When the individual means are rendered conductive, the voltage across the first means when conducting may not be equal to the voltage across the second means for an applied signal of opposite polarity. To this end, balancing means such as a voltage divider, may be coupled between the fifth and eighth electrodes. The voltage divider is provided in conventional manner with an adjustable tap which is coupled to the second terminal. By varying the position of the tap and thereby adding voltage in series with the first and second means, the static composite characteristic, i.e. the bilateral curve of current versus voltage, of the switch can be adjusted so that it passes through the origin. Thus, the voltage off-set of the switch is essentially eliminated.

Each asymmetrically conductive means contains a unidirectional conducting element, such as a diode, and a three electrode semiconductor element, such as a transistor. By selecting the corresponding elements of each means to possess complementary static characteristics, the temperature variation of the individual element characteristics do not significantly alter the low off-set voltage of the switch. However, the balancing divider enables the switch to be adjusted for essentially zero off-set at different temperatures without requiring the use of matched elements.

The first means contains a first diode, having first and second electrodes, poled to pass current flowing from the first to second electrode and a first transistor having third, fourth and fifth electrodes. The third electrode is coupled to the second electrode. The first electrode is coupled to the first terminal and the fifth electrode is coupled to the second terminal. The absence of a switching signal at the fourth electrode results in the transistor being cutoif so that the first means is nonconductive for signals of either polarity appearing at the first terminal. It will be noted that for negative polarity signals at the first terminal, the first means is rendered nonconductive by the first diode, While for positive signals, the first means is rendered nonconductive by the first transistor. The transistor is preferably connected so that the collector corresponds to the third electrode and the hold-off capability is determined by the high voltage junction. Also, the conductivity type is selected so that the transistor is not operated in inverse manner and the normal ,8 or shortcircuit current gain determines the gain of the switch.

The second means is constructed in a similar manner with the diode therein being reversed with respect to the first diode and the transistor therein being of opposite conductivity type for the above reasons. It shall be noted that the first and second means of this switch are asymmetrically conductive and provide a switching gain.

Further, the switching signals applied to the transistors need not be applied through a transformer but can be referenced to ground so that the switch is capable of sustained operation in both the ON and OFF states. Also, during the transient periods at turn-on and turn-off, a cancellation of the transient spiking is obtained due to the balanced nature of the circuit. This transient suppression is due to the concurrent application of the switching signals to the first and second means.

Further features and advantages of the invention will become more readily apparent from the following detailed description of a specific embodiment of the invention taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic diagram of one embodiment of the invention;

FIG. 2 is a curve showing representative static characteristics of the embodiment of FIG. 1;

FIG. 3 is a schematic diagram of the equivalent circuit of the embodiment of FIG. 1 during the transient period; and

FIG. 4 is a graph showing the variation in leakage current with temperature for the embodiment of FIG. 1.

Referring now to FIG. 1, a bilateral analog switch is shown coupled between first and second terminals 10 and 11. The switch comprises first and second asymmetrically conductive means 14 and 15 respectively each of which are poled to permit the flow of current in a single direction.

First means 14 having third, fourth and fifth terminals 16, 17 and 18, respectively, is poled to pass current flow ing from terminal 16 to terminal 18. As shown, terminal 16 is coupled to first terminal 10 while terminal 18 is coupled to second terminal 11. Second means 15 having sixth, seventh and eight terminals 20, 21 and 22 respectively, is poled to pass current flowing from terminal 22 to terminal 20. It shall be noted that terminal 20 is coupled to first terminal 10 while terminal 22 is coupled to second terminal 11.

First asymmetrically conductive means 14 contains diode D having its anode electrode coupled to terminal 16 and its cathode electrode coupled to the collector of transistor Q The emitter of transistor Q is coupled to terminal 18 and the base thereof is coupled to switching signal terminal 17. As shown, transistor O is an NPN transistor so that it may be rendered conductive by the application of a positive signal to terminal 17. The diode D prevents first means 14 from conducting current from terminal 18 to terminal 16. However conduction from terminal 16 to terminal 18 can only occur when a positive voltage is applied to terminal 17.

Similarly, second conductive means 15 contains diode D having its cathode electrode coupled to terminal 20 and its anode electrode coupled to the collector of PNP transistor Q The emitter of transistor Q is coupled to terminal 22 and the base thereof is coupled to switching signal terminal 21. The diode D prevents the conduction of current from terminal 20 to terminal 22 while conduction in the opposite direction can occur onlywhen transistor Q is rendered conductive by the application of a negative signal to terminal 21.

The terminals 18 and 22 are coupled to the opposite ends of a balancing voltage divider R having an adjustable tap thereon which is shown coupled to second terminal 11. Terminals 18 and 22 are coupled to voltage sources V and +V through resistors R and R respectively so that a voltage gradient occurs along resistor R The voltage source -V is coupled also to terminal 17 through R Similarly voltage source +V is coupled also to terminal 21 through resistor R The switching signals are applied to terminals 12 and 13 which are coupled to terminals 17 and 21 through the parallel combinations of capacitor C and resistor R and of capacitor C and resistor R respectively. The signals are applied simultaneously to render the transistors Q and Q conductive. The magnitudes of resistors R and R are selected so that the application of a positive voltage at terminal 12 results in the voltage at switching signal terminal 17 changing from -V to a positive voltage. As a result, transistor Q is driven into conduction, preferably saturation. A similar result is obtained at switching signal terminal 18 with only the polarity being different.

Assuming a positive signal appearing at terminal 10, the application of the switching signals renders transistors Q and Q conductive. However, diode D cannot conduct current in the corresponding direction so that second means 15 is cut-off. First means 14 can conduct in this direction so that a low impedance path is provided between terminals 10 and 11. The impedance in the ON state is determined by the forward impedances of the diode and transistor and the portion of the impedance of the balancing potentiometer between terminals 18 and 11. In practice, this impedance is less than 50 ohms. For negative signals, the second means is conductive in the same manner so that the relatively low ON impedance of the switch is essentially independent of polarity.

In the absence of the switching signals, both first and second means 14 and 15 are nonconductive and the switch is in the OFF state. The OFF impedance of second means 15 is determined by the back resistance of diode D while that of the first means is determined by the impedance of the back-biased collector-base junction of transistor Q In practice, the OFF impedance exceeds 5X10 ohms. It shall be noted that for negative polarity signals at terminal 10, the OFF impedance of first means 14 is determined by diode D and the OFF impedance of second means 15 is determined by the impedance of the back-biased collector-base junction of transistor Q By employing similar diodes and transistors, the high OFF impedance of the switch is essentially independent of the polarity of the signal at terminal 10.

vThe state current-voltage characteristic of the switch is shown by the dotted line 30 of FIG. 2. This characteristic is the composite of the static characteristics 31 and 32 of first means 14 and 15 respectively. If the static characteristics of each branch are symmertical, the individual off-set voltage e and e are of the same magnitude and the composite characteristic passes through the origin. This corresponds to the positioning of the tap of voltage divider R at the point wherein equal magnitude and opposite polarity voltages are added to each branch.

However, if the characteristics of the branches are not symmetrical, corresponding to the use of unmatched elements therein, the position of the tap of voltage divider R may be varied so that the composite characteristic passes through the origin. This adjustment can be made to compensate for a change in operating temperature to insure that the off-set voltage of the switch remains essentially at zero. In addition, the use of complementary transistors Q and Q and similar diodes D and D minimizes any temperature variations since the net current is a function of the characteristics of both branches. Also, for certain applications the balancing divider R may be omitted if desired.

The curve of FIG. 4 shows the measured leakage current for one embodiment of the invention in the absence of switching signals, i.e. the switch is open. The signal applied at terminal 10 was 20 volts and the temperature was varied from 25 to C. For the typical operating temperature of less than 50 C., the leakage current was found to be less than 10 ramps.

Since this switch is to be operated at high rates for signals having a wide range of magnitudes, the transient response to switching is of primary interest. During the switching transient interval, the equivalent circuit of the switch may be represented by the capacitive bridge of FIG. 3 wherein Ccb Ceb Ccb and Ceb refer to the junction capacitances of transistors Q and Q Due to the fact that opposite polarity switching signals appear at terminals 17 and 21, there is a cancellation of both the turn-on and turn-off edges. The degree of this cancelling efiect depends on the match between the capacities of the transistors and the absence of any differences between the switching signal waveforms. In practice, the transient spikes occurring at turn-on and turn-off are found to be approximately 0.1 volt and about 0.5 microsecond in duration.

Typical component values for one embodiment tested and operated were as follows:

Diodes D D -Type IN 695 Transistor Q -Type 2N 221-8 Transistor Q Type 2N 2904 'Resistor R 20 ohms Resistors R R 'l50 ohms Resistors R R '12 kilohms Resistors R R '3.9 kilohms Capacitors C C '47 picofarads While the above description has referred to a specific embodiment of the invention, it will be apparent that many modifications and variations may be made therein without departing from the spirit and scope of the invention.

What is claimed is:

1. A bilateral analog switch comprising:

(a) first and second terminals;

(b) a first diode having first and second electrodes,

said first electrode being coupled to said first terminal, said diode being poled to pass current flowing from said first to said second electrode;

(0) a first transistor having third, fourth and fifth electrodes, said third electrode being coupled to the second electrode of said first diode, the application of a switching signal to said fourth electrode rendering said first transistor conductive as between its third and fifth electrodes;

(d) a second diode having first and second electrodes,

said second electrode being coupled to said first terminal, said diode being poled to pass current flowing from said first to said second electrode;

(e) a second transistor having third, fourth and fifth electrodes, said third electrode being coupled to the first electrode of said second diode, the application of a switching signal to said fourth electrode rendering said second transistor conductive as between its third and fifth electrodes;

'(f) voltage divider means having third, fourth and fifth terminals, said third and fifth terminals being coupled to the fifth electrode of said first transistor and the fifth electrode of said second transistor respectively, said fourth terminal being coupled to said second terminal; and

8 (g) first and second voltage sources of opposite po- References Cited larity, said first voltage source being coupled between the third and fourth terminals of said voltage UNITED STATES PATENTS divider means and said second voltage source being 3,437,842 4/1959 Bl-ouwer coupled between the fourth and fifth terminals of 3 031 588 4/1962 Hilsemath 307 255 X said voltage divider, said voltage sources establish- 5 ing a voltage gradient along said voltage divider 3,025,418 3/1962 Brahm 307 255 X means so that the net oflfset voltage between the first 3,077,545 2/1963 Rywak 307255 X and second terminals of said switch is substantially 3,237, 20 11 19 Tuszynski 307 255 X eliminated.

2. A bilateral analog switch in accordance with claim 10 DONALD D. FORRER, Primary Examiner 1 in which said first and second voltage sources are coupled to said voltage divider means through first and sec- WOODBRIDGE Asslstant Examiner 0nd resistors. US. Cl. X.R.

3. A bilateral analog switch in accordance with claim 15 253 2, in which said first and second transistors are NPN and PNP types respectively.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US3025418 *Dec 24, 1959Mar 13, 1962United Aircraft CorpQuadrature stripping circuit
US3031588 *Sep 22, 1959Apr 24, 1962Lockheed Aircraft CorpLow drift transistorized gating circuit
US3077545 *Mar 7, 1960Feb 12, 1963Northern Electric CoGates including (1) diodes and complementary transistors in bridge configuration, and (2) diodes with parallelled complementary transistors
US3287620 *Jun 13, 1962Nov 22, 1966Esterline Angus Instr CompanyChopper circuit
US3437842 *Oct 20, 1965Apr 8, 1969Lear Siegler IncFail safe bridge output switch
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US4132835 *Mar 25, 1977Jan 2, 1979Frye Copysystems, Inc.Pressure sensitive magnetic image transfer media
US4845446 *Dec 19, 1986Jul 4, 1989Ii Morrow, Inc.Dynamically variable attenuator
US5459425 *Dec 23, 1993Oct 17, 1995Mitsubishi Denki Kabushiki KaishaSignal processing circuit with voltage limiting function
US5745563 *Feb 25, 1992Apr 28, 1998Harris CorporationTelephone subscriber line circuit, components and methods
US6154069 *Nov 26, 1997Nov 28, 2000Citizen Watch Co., Ltd.Circuit for driving capacitive load
Classifications
U.S. Classification327/423, 327/576, 327/588, 327/484
International ClassificationH03K17/66, H03K17/60
Cooperative ClassificationH03K17/667, H03K17/668
European ClassificationH03K17/66D2D, H03K17/66D2C